Page 1
AS8202
TTP/C-C2 Communication
Controller
Preliminary Data Sheet
Rev. 1.0, October 2000
Page 2
TTP/C-C2 Communication Controller – Preliminary Data Sheet
AS8202
Key Features
• Dedicated controller supporting TTP/C (time trigger ed pr otocol class C)
• Suited for dependable distributed real-time systems with guaranteed response time
• Application fields: Automotive (by-wire braking, steering, vehicle dynamics control, drive
train control), Aerospace (aircr aft electronic systems), Industr ial system s, Railway systems
• TTP/C asynchronous data rate up to 5 MBit/s @ clock 40 MHz, synchronous data rate 25
MBit/s @ clock 40 MHz
• Single power supply 3.3V
• 0.35µm CMOS process
• Temperature range: -40°C to 125° C
• 2k x 16 RAM message, status and control area (communication network interface)
• RAM for instruction code and configurat ion dat a
• 16 Bit non-multiplexed host CPU interface
• 16 Bit RISC architecture
• 16k x 16 internal FLASH memory for fir m ware and scheduling information
• software tools, design-in support, development boards available ( http://www.tttech.com)
• 80 pin TQFP Package
General Description
The AS8202 communications controller is an integrated device supporting serial
communication according to the TTP/C specification. It perf or m s all communications tasks such
as reception and transmission of messages in a TTP
CPU.
provides mechanisms that allow the deployment in high-dependability distributed real-
TTP
time systems. It provides following services:
• predictable transmission of messag es with minimal jitter
• fault-tolerant distributed clock synchronisation
• consistent membership service with small delay
• masking of single faults
ram_data[15:0]
ram_address[11:0]
Host
Processor
Interface
led[1]/time_overflow
Quartz or
Oscillator
ram_ceb
ram_oeb
ram_web
ram_readyb
time_signalb
led[0]/time_tick
led[2]/microtick
xin0
xout0
resetb
plloff
Controller
network
interface
(CNI)
Reset &
Time
base
processor core
TTP/C
protocol
cluster without interaction of the host
Receiver
Bus
guardian
Transmitter
rxd[1:0]
rxclk[1:0]
rxdv[1:0]
rxer[1:0]
xin1
xout1
txd[1:0]
cts[1:0]
txclk[1:0]
TTP/C
Bus Media
Drivers
FLASH
memory
Instruction
RAM memory
Network
configuration
memory
(MEDL)
test_se
ftest
stest
fidis
mtest
Test
Interface
Figure 1 AS8202 Block Diagram
Rev. 1.0, October 2000 Page 2 of 2
Page 3
TTP/C-C2 Communication Controller – Preliminary Data Sheet
[
]
[
]
[
]
[
]
[
]
[
]
[
]
rxdv[0]
[
]
[
]
[
]
[
]
[
]
[
]
[
]
[
]
[
]
[
]
[
]
[
]
[
]
[
]
[
]
Vdd
[
]
[
]
[
]
[
]
[
]
[
]
[
]
[
]
AS8202
The CNI (communication network interface) forms a temporal firewall. It decouples the
controller network from the host subsystem by use of a dual ported RAM. This prevents the
propagation of control err ors. T he interf ace to the host CPU is implemented as 16 bit wide nonmultiplexed asynchronous bus interface.
TTP/C follows a conflict-free media access strategy called time-division-multiple access
(TDMA). This means, TTP/C deploys a time slot technique based on a global time which is
permanently synchronised. Each node is assigned a time slot in which it is allowed to perform
transmit operation. The sequence of time slots is called TDMA round, a set of TDMA rounds
forms a cluster cycle. After one cluster cycle the operation of the network repeats. The
sequence of interactions forming the cluster cycle is defined in a static time schedule, called
message-descriptor-list ( MEDL). The definition of the MEDL in conjunction with the g lobal time
determines the response time for a ser vice request.
The membership of all nodes in t he network is evaluated by the communication contr oller. This
information is presented in a consistent fashion to all correct cluster members. During
operation, the status of every other node is propagated within one TDMA round. The MEDL is
loaded into the configuration m em or y when the system starts up.
Package and Pin Assignment
Type: TQFP 80, plastic packag e
2
3
1
0
ram-data
ram-data
ram-data
ram-data
AS8202
TTP/C
Controller
(TOP VIEW)
0
0
0
0
cts
txd
rxer
txclk
Vdd
Vss
ram-data[8]
ram-data[9]
ram-data[10]
ram-data[11]
ram-data[12]
ram-data[13]
ram-data[14]
ram-data[15]
Vdd
Vss
ram-ceb
ram-oeb
ram-web
ram-readyb
to Vss
to Vdd
n.c.
n.c.
7
5
6
4
ram-data
ram-data
ram-data
ram-data
61
Communications
80
1 20
Vss
Vdd
xin0
xout0
10
11
9
8
Vss
ram-address
ram-address
ram-address
ram-address
0
0
1
Vss
Vdd
txd
rxd
rxclk
7
ram-address
1
cts
6
ram-address
1
txclk
3
5
4
Vss
ram-address
ram-address
ram-address
41 60
40
ram-address[2]
ram-address[1]
ram-address[0]
mtest
led[2]/time-overflow
led[1]/time-tick
led[0]/microtick
Vss
Vdd
time-signalb
resetb
fidis
ftest
plloff
stest
test-se
Vss
xin1
xout1
Vdd
21
1
1
1
1
rxd
rxer
rxdv
rxclk
Figure 2 TQFP 80 pin package and pin assignment
Rev. 1.0, October 2000 Page 3 of 3
Page 4
TTP/C-C2 Communication Controller – Preliminary Data Sheet
AS8202
Pin Description
Pin Name Dir Description
1,12,21,32,51,61,71 Vdd P positive power supply
4,13,24,33,43,52,62,72 Vss P Negative power supply
2 xout0 O Main clock: analog pad from oscillator / leave open
when providing external clock
3 xin0 I Main clock: analog pad from oscillator / use as input
when providing external clock
5 txd[0] OPU Transmit data channel 0
6 cts[0] OPD Transmit enable channel 0
7 txclk[0] IPD TTP/C synchronous: Transmit clock channel 0
8 rxer[0] IPU TTP/C synchronous: Receive error channel 0
9 rxclk[0] IPD TTP/C synchronous: Receive clock channel 0
10 rxdv[0] IPU TTP/C synchronous: Receive data valid channel 0
11 rxd[0] IPU Receive data channel 0
14 txd[1] OPU Transmit data channel 1
15 cts[1] OPD Transmit enable channel 1
16 txclk[1] IPD TTP/C synchronous: Transmit clock channel 1
17 rxer[1] IPU TTP/C synchronous: Receive error channel 1
18 rxclk[1] IPD TTP/C synchronous: Receive clock channel 1
19 rxdv[1] IPU TTP/C synchronous: Receive data valid channel 1
20 rxd[1] IPU Receive data channel 1
22 xout1 O Bus guardian clock: analog pad from oscillator / leave
open when providing external clock
23 xin1 I Bus guardian clock: analog pad from oscillator / use as
input when providing external clock
25 test_se IPD Test input, connect to Vss
26 stest IPD Test input, connect to Vss
27 plloff IPD PLL disable pin
28 ftest IPD Test input, connect to Vss
29 fidis IPD Test input, connect to Vss
30 resetb I main reset input signal, active low
31 time_signalb OPU CNI control signal, CNI time signal
34 led[0]/microtick OPD Configurable: either generic output port (f.e. to drive
LEDs) or timing signal TIME_TICK
35 led[1]/time_tick OPD Configurable: either generic output port (f.e. to drive
LEDs) or timing signal TIME_OVERFLOW
36 led[2]/time_overflow OPD Configurable: either generic output port (f.e. to drive
LEDs) or timing signal TIME_OVERFLOW
37 mtest IPD Test input, connect to Vss
38-42,44-50 ram_address[0:11] I Host interface (CNI) address bus
53-60,63-70 ram_data[0:15] I/O Host interface (CNI) data bus, tristate
73 ram_ceb IPU Host interface (CNI) chip enable, active low
74 ram_oeb IPU Host interface (CNI) output enable, active low
75 ram_web IPU Host interface (CNI) write enable, active low
76 ram_readyb OPU Host interface (CNI) transfer finish signal, active low
77 to Vss P Connect to Vss
78 to Vdd IPU Connect to Vdd
79 high Z Do not connect
80 high Z Do not connect
I Input CMOS IPU Input CMOS with pull up
IPD Input CMOS with pull down O Output CMOS
OPD Output with pull down when tristate OPU Output with pull up when tristate
I/O Input/Output CMOS tristate P Power Pin
Rev. 1.0, October 2000 Page 4 of 4
Page 5
TTP/C-C2 Communication Controller – Preliminary Data Sheet
AS8202
Electrical Specifications
Absolute Maximum Ratings (Non Operating)
SYMBOL PARAMETER MIN MAX NOTE
VDD DC Supply Voltage -0.3 V 5.0 V
Vin Input Voltage on any Pin - 0.3 V VDD + 0.3 V
Iin Input Current on any Pin -100 mA 100 mA 25°C
T
Storage Temperature
strg
T
Soldering Temperature
sold
t
Soldering Time 10 sec Reflow and Wave
sold
H Humidity 5 % 85 %
ESD Electrostatic Discharge 1000 V HBM: R = 1.5 k, C = 100 pF
1. 300 oC all ceramic packages and DIL plastic packages, 260 oC for surface mounting plastic packages
Note: Stresses above those listed under “Absolute Maxim um Ratings” m ay cause permanent dam age to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Expos ure
to absolute maxim um rating conditions for extended periods may effect device reliability (e.g. hot carrier
degradation).
o
-55
C 150
260
o
C
o
C
1)
Recommended Operating Conditions
PARAMETER SYMBOL MIN TYP MAX NOTE
DC Supply Voltage VDD 3.0 V 3.3 V 3.6 V
Circuit Ground VSS 0.0 V 0.0 V 0.0 V
Static Supply Current IDDS ----
700
µA 800 µA
Operating Supply Current IDD ---- 45 mA 56 mA fCLK = 40 MHz, VDD = 3.6 V
Main clock frequency CLK 5 MHz 20 MHz oscillator pins xin0, xout0
Bus Guardian clock
CLK2 4 MHz 16 MHz oscillatpr pins xin1, xout1
frequency
Ambient Temperature Ta
1. The input and output parameter values in this table are directly related to ambient temperature and DC supply
voltage. A temperature range other Ta
affect these values and must be evaluated extra.
2. Static supply current IDDS is exclusive of input/output drive requirements and is measured at maximum VDD
with the clocks stopped and all inputs tied to VDD or VSS, configured to draw minimum current.
3. Operating current is exclusive of input/output drive requirements and is measured at maximum VDD and
maximum clock frequency 40 MHz.
-40 oC
to Ta
min
or a supply voltage range other than VDD
max
+125 oC
1)
2)
3)
1)
to VDD
min
max
will
DC Characteristics and Voltage Levels
CMOS I/O levels for specified voltage and temperature range unless otherwise noted.
Inputs Pins
Pin Name Vil Vih Iil (1) Iih(2) NOTE
max min min max min max
All inputs and IO pins
without pull-up/down
Inputs with pull-up 30%
Inputs with pull-down 30%
1. Iil ist tested at VDDmax and Vin = 0
2. Iih ist tested at VDDmax and Vin = VDDmax
3. CMOS input levels are in percentage of VDD, for pull-up/down refer to pin description above.
30%
VDD
VDD
VDD
70%
VDD
70%
VDD
70%
VDD
NA -1.0
µA
-50
µA
-160
µA
NA NA 30
NA 1.0
µA
NA NA CMOS with
160
µA
µA
CMOS input (3)
pull up (3)
CMOS with
pull down (3)
Rev. 1.0, October 2000 Page 5 of 5
Page 6
TTP/C-C2 Communication Controller – Preliminary Data Sheet
AS8202
Output Pins
Pin Name Vol Voh Iol (1) Ioh(2) Ioz(3) NOTE
V V mA mA
txd[0,1],cts[0,1],led[0,2] 0.4 2.4 4.0 -4.0 NA CMOS output
All other output pins
(except xout0, xout1)
All I/O pins 0.4 2.4 2.0 -2.0 +/-10 CMOS output, Tristate
1. Vol, Iol is tested at VDD = 3.3V
2. Voh, Ioh is tested at VDD = 3.3V
3. Ioz is tested at VDD = 3.6V
0.4 2.4 2.0 -2.0 NA CMOS output
µA
AC Characteristics
PARA METER SYMBOL PIN MIN MAX NOTE
main clock external operating
frequency
main clock XTAL0 frequency clkxt0 xin0/xout0 1 MHz 20 MHz
main internal clock frequency clk0 --- --- 40 MHz pin plloff = low PLL
XTAL1 operating frequency clkxt1 xin1/xout1 1 MHz 20 MHz
1. XTAL frequency or external clock frequency for PLL input is fixed to 10 MHz, other frequencies applicable only
without PLL function in use.
clkext xin0 0 40 MHz pin plloff = high
PLL not used
oscillator cell 1
1)
in use
oscillator cell 2
1)
1)
Rev. 1.0, October 2000 Page 6 of 6
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TTP/C-C2 Communication Controller – Preliminary Data Sheet
Trb
AS8202
Application Information
Host CPU Interface
The host CPU interface also referred as CNI (communication network int erface) connects the
application circuitry to the TT P controller. All ram_-lines provide asynchronous read/writ e
access to a dual ported RAM. There are no setup/hold constr aint s r eferred to the microtick
(main clock “clk0”). The signals have to be applied for certain duration to be synchronized to
the main internal clock (microt ick). The time_-lines signal to host CPU the global synchronous
time of the TTP net work and det er mine when to deliver, resp. to fetch data f r om the host
interface. One of t he lines m ay be connected t o an interrupt input of the host CPU. Not e t hat
the microtick, time_overflow and the time_tick pins can be configured as g ener al purpose
output LED pins (see the LED Interface section below).
Host Interface Ports
Pin Name mode width comment
ram_address[0:11] in 12 DPRAM address bus, 12 bit
ram_data[0:15] inout (tri) 16 DPRAM data bus, 16 bit
ram_ceb In 1 DPRAM chip enable
ram_web In 1 DPRAM write enable
ram_oeb In 1 DPRAM output enable
ram_readyb out 1 DPRAM ready
time_overflow out 1 Overflow of global time (global time is Zero)
microtick out 1 Microtick (internal main clock)
time_signal out 1 CNI time signal
time_tick out 1 Macrotick (global time is incremented)
Asynchronous DPRAM interface
Signals ram_address[0:11] and ram _web have to be stable before the falling edge of ram_ceb
For a write access the host sets ceb, web, address and data until the DPRAM has tak en t he
data and set readyb active low. The next access may start with readyb inactive again. A read
cycle starts with valid address and ceb, the data is valid with readyb active low. A low level on
oeb and ceb switches the data bus from tristat e to output. Access times depend on the
controller clock rate and controller activity, typical values are:
controller cycle time Tc Min 25 ns (40 MHz)
write time Tw Min 4 Tc
read time Tr Min 5 Tc
readyb low time Trb Min 1 Tc
ceb
write read
addres
data
web
oeb
valid
valid
tristate
valid
xx
valid
ready
Tw Tr
Trb
Rev. 1.0, October 2000 Page 7 of 7
Page 8
TTP/C-C2 Communication Controller – Preliminary Data Sheet
AS8202
Reset and Oscillator
Pin Name mode width Comment
xin0 in 1 main oscillator input
xout0 out 1 main oscillator output
xin1 in 1 bus guardian oscillator input
xout1 out 1 bus guardian oscillator output
plloff in 1 PLL disable
resetb in 1 external reset
Table 1: Reset and Oscillator Ports
External Reset Signal
To issue a reset of the chip the r eset b port has to be driven low for at least
power-up the reset must overlap the build-up time of the oscillator circuit.
Integrated Power-On Reset
The Device has an internal Power-On Reset generator. When supply voltage ramps up, t he
internal reset signal is kept act ive (low) for about 33 µs typical.
Parameter Symbol Min Typ Max Unit
supply voltage slope dV/dt 250 - - kV/s
power on reset active time after VDD > 1,0V t
25 33 49 us
pon_res
Oscillator circuitry
The internal oscillator cell req uires an external quartz or an external oscillator r espectively. The
frequency applied on the main clock input ( xin0, xout0) can be r educed by a factor of four by
using the internal PLL. In order t o generate an internal freq uency of 40 MHz using the internal
PLL, an external quartz or quartz oscillator with a frequency of 10 MHz is connected and the
plloff input is tied low. The bus g uar dian clock has no internal PLL.
20MHz 16M Hz
‚1‘
xout0
xin0
xout1 xin1
plloff
20 MHz
Figure 3: Quartz Circuit PLL off Figure 4: Quartz Circuit PLL on
10MHz 16MHz
‚0‘
xout0
xin0
xout1 xin1
plloff
40 MHz
40MHz
oscillator
n.c. n.c.
xout0
Figure 5: Oscillator Circuit
µs. After
xin0
16MHz
oscillator
‚1‘
xout1 xin1
plloff
40 MHz
Rev. 1.0, October 2000 Page 8 of 8
Page 9
TTP/C-C2 Communication Controller – Preliminary Data Sheet
AS8202
TTP/C Asynchronous Bus Interface
The TTP/C asynchronous bus interf ace uses MFM patterns to tr ansmit/receive signals at a
maximum data rate of 5 MBit/s on a shared media (physical bus). The pins can either be
connected to drivers using recessive/dominant states on the wire as well as drivers using active
push/pull functionality.
Pin Name mode comment
txd[0] out Transmit data channel 0
cts[0] out Transmit enable channel 0
txclk[0] in no function (do not connect)
rxer[0] in no function (do not connect)
rxclk[0] in no function (do not connect)
rxdv[0] in no function (do not connect)
rxd[0] in Receive data channel 0
txd[1] out Transmit data channel 1
cts[1] out Transmit enable channel 1
txclk[1] in no function (do not connect)
rxer[1] in no function (do not connect)
rxclk[1] in no function (do not connect)
rxdv[1] in no function (do not connect)
rxd[1] in Receive data channel 1
Table 2: TTP/C Asynchronous Bus Interface Pins
TTP/C Synchronous Bus Interface
The TTP/C synchronous bus interf ace uses a synchronous t r ansfer method to transf er dat a at
a rate of 25 MBit/s. PHY drivers used in comm e r cial 100 MBit Ether net applications can be
connected to this interface.
Pin Name mode comment
txd[0] out Transmit data channel 0
cts[0] out Transmit enable channel 0
txclk[0] in Transmit clock channel 0
rxer[0] in Receive error channel 0
rxclk[0] in Receive clock channel 0
rxdv[0] in Receive data valid channel 0
rxd[0] in Receive data channel 0
txd[1] out Transmit data channel 1
cts[1] out Transmit enable channel 1
txclk[1] in Transmit clock channel 1
rxer[1] in Receive error channel 1
rxclk[1] in Receive clock channel 1
rxdv[1] in Receive data valid channel 1
rxd[1] in Receive data channel 1
Table 3: TTP/C Synchronous Bus Interface Pins
Rev. 1.0, October 2000 Page 9 of 9
Page 10
TTP/C-C2 Communication Controller – Preliminary Data Sheet
AS8202
Test Interface
The Test Interface supports the manufacturing t est and characterisation of the chip. In t he
application environment test pins and special pins have to be connected as following:
test_se, stest, ftest , fidis, mtest, Vpp : connect to Vss
Tmr : connect to Vdd
Tm0, Tm1 : do not connect
Warning:
Any other connection of this pins may cause permanent damage to t he device.
LED Signals
The LED signals can be used as a universal output port. The driver strength of the LED por t s is
4mA. Note that the pins can be configured as special-function host interface pins (see the Host
Interface section f or m or e details).
Ordering Information
Part Number: AS8202
Part Name: TTP/C-C2 Communication Controller
Package: TQFP 80
Support
Software tools, hardware development boards, evaluation systems and extensive support on
TTP system integration as well as consulting is pr ovided by:
TTTech Computertechnik AG
Time-Triggered Technology
and
TTChip GmbH – a TTTech Company
Schoenbrunnerstrasse 7
A1040 Vienna
Austria
Voice: +43 1 5853434 - 0
Fax: +43 1 5853434 - 90
email: office@tttech.com
web: http://www.tttech.com
Note: TTP
holders.
Copyright 2000 TTTech Computertec hnik AG
Copyright 2000, Austria Mik ro S ysteme International AG, Schloß Premstätten, 8141 Unterpremstätten, Austria.
Telefon +43-(0)3136-500-0, Telefax +43-(0)3136-52501, E-Mail info@am sint.com
All rights reserved. No part of this publication may be reproduced, stored in a retrieval syst em, or transmitt ed, i n any form or by any
means, without the prior permission in writing by the copyright holder. To the best of its knowledge, A ustria Mikro Systeme
International asserts that the information contained in this publication is accurate and correct.
is a registered trademark of FTS Computertechnik GmbH. All other trademark s are the property oftheir respective
Rev. 1.0, October 2000 Page 10 of 10
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