Datasheet AS7C4098-20TI, AS7C4098-20TC, AS7C4098-20JI, AS7C4098-20JC, AS7C4098-15TC Datasheet (Alliance Semiconductor Corporation)

March 2001

AS7C4098

AS7C34098

®

5V/3.3V 256K × 16 CMOS SRAM

Features

• AS7C4098 (5V version)

• AS7C34098 (3.3V version)

• Industrial and commercial temperature

• Organization: 262,144 words × 16 bits

• Center power and ground pins

• High speed

- 10/12/15/20 ns address access time

- 5/6/7/8 ns output enable access time

• Low power consumption: ACTIVE

- 1375 mW (AS7C4098)/max @ 12 ns

- 468 mW (AS7C34098)/max @ 12 ns

Logic block diagram

A0
A1

I/O1–I/O8

I/O9–I/O16

WE

UB

OE

LB
CE

A2
A3
A4
A6
A7

A8
A12
A13

Row Decoder

I/O

buffer

1024 × 256 × 16

Array

(4,194,304)

Control circuit

Column decoder

A5

A9

A10

A11

A14

• Low power consumption: STANDBY

- 110 mW (AS7C4098)/max CMOS

- 72 mW (AS7C34098)/max CMOS

• Individual byte read/write controls

• 2.0V data retention

• Easy memory expansion with CE

, OE inputs

• TTL- and CMOS-compatible, three-state I/O

• 44-pin JEDEC standard packages

-400-mil SOJ

-400-mil TSOP II

• ESD protection ≥ 2000 volts

• Latch-up current ≥ 200 mA

Pin arrangement

V

CC

GND

A15

A16

A17

44-pin SOJ, TSOP II (400 mil)

1A0

44

2A1

43

3A2

42

4A3

41

A4

CE

I/O1
I/O2
I/O3
I/O4

V
GND
I/O5
I/O6
I/O7
I/O8

WE

A5
A6
A7
A8
A9

5

40

6

39
38

7
8

37

9

36

10

35

11
12
13
14
15
16
17
18
19
20
21
22

34
33
32
31
30
29
28
27
26
25
24
23

CC

A17
A16
A15
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
GND
V

CC

I/O12
I/O11
I/O10

I/O9
NC

A14
A13
A12
A11
A10

Selection guide

AS7C4098

AS7C34098

–10

Maximum address
access time

Maximum output
enable access time

Maximum operating
current

Maximum CMOS
standby current

3/23/01; v.1.0 Alliance Semiconductor P. 1 of 9

AS7C4098 – 250 220 180 mA

AS7C34098 160 130 110 100 mA

AS7C4098 – 20 20 20 mA

AS7C34098 20 20 20 20 mA

10 12 15 20 ns

5679ns

AS7C34098

–12

AS7C4098

AS7C34098

–15

AS7C4098

AS7C34098

–20 Unit

Copyright © Alliance Semiconductor. All rights reserved.

AS7C4098

®

Functional description

The AS7C4098 and AS7C34098 are high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) devices
organized as 262,144 words × 16 bits. They are designed for memory applications where fast data access, low power, and
simple interfacing are desired.

Equal address access and cycle times (t
are ideal for high-performance applications. The chip enable input CE
memory systems.

When CE

is High the device enters standby mode. The standard AS7C4098 is guaranteed not to exceed 110 mW power

consumption in CMOS standby mode. Both devices offer 2.0V data retention.

A write cycle is accomplished by asserting write enable (WE
written on the rising edge of WE

(write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive

I/O pins only after outputs have been disabled with output enable (OE

A read cycle is accomplished by asserting output enable (OE
drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or
write enable is active, output drivers stay in high-impedance mode.

These devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to
be written and read. LB

controls the lower bits, I/O1–I/O8, and UB controls the higher bits, I/O9–I/O16.

All chip inputs and outputs are TTL- and CMOS-compatible, and operation is from either a single 5V (AS7C4098) or 3.3V
(AS7C34098) supply. Both devices are available in the JEDEC standard 400-mL, 44-pin SOJ and TSOP II packages.

, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5/6/7/8 ns

AA

permits easy memory expansion with multiple-bank

) and chip enable (CE). Data on the input pins I/O1–I/O16 is

) or write enable (WE).

) and chip enable (CE), with write enable (WE) High. The chip

AS7C34098

Absolute maximum ratings

Parameter Device Symbol Min Max Unit

Vol tag e o n V

relative to GND

CC

AS7C4098 V

AS7C34098 V

Voltage on any pin relative to GND V

Power dissipation P

Storage temperature (plastic) T

Ambient temperature with V

applied T

CC

DC current into outputs (low) I

Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.

t1

t1

t2

D

stg

bias

OUT

–0.50 +7.0 V

–0.50 +5.0 V

–0.50 VCC +0.50 V

–1.5W

–65 +150 °C
–55 +125 °C

–±20mA

Truth table

CE

H X X X X High Z High Z Standby (I

LHHXX

LXXHH

LHL

LLX

Key: X = Don’t care, L = Low, H = High.

WE OE LB UB I/O1–I/O8 I/O9–I/O16 Mode

High Z High Z Output disable (I

LH D

LL D

LH D

LL D

OUT

OUT

IN

IN

High Z

OUT

D

OUT

High Z

IN

D

IN

Read (I

Write (I

, I

)

SB

SB1

)

CC

)HL High Z D

CC

)HL High Z D

CC

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Recommended operating conditions

Parameter Symbol Min Typical Max Unit

AS7C4098 V

Supply voltage

AS7C34098 V

AS7C34098 V

AS7C4098 V

Input voltage

AS7C34098 V

commercial T

Ambient operating temperature

industrial T

min = –3.0V for pulse width less than tRC/2.

* V

IL

DC operating characteristics (over the operating range)1

Parameter Symbol Test conditions

= Max

Input leakage
current

Output leakage
current

Operating
power supply
current

Standby power
supply current

Output voltage

|I

|

|I

LI

|

LO

I

CC

I

SB

I

SB1

CE
– 0.2V or V

V

OL

V

OH

V

CC

V

= GND to V

IN

= Max

V

CC

CE

= VIH or OE = VIH

or WE

V

= GND to V

I/O

VCC = Max

CC

= VIL

CC

AS7C4098 – – – 250 – 220 – 180 mA

Min cycle, 100% duty

CE

= VIL, I

VCC = Max

CE

= VIH, f = Max

VCC = Max

≥ V

– 0.2V, V

CC

IN

= 0mA

OUT

≥ V

IN

≤ 0.2V, f = 0

AS7C34098 – 160 – 130 – 110 – 100 mA

AS7C4098 – – – 60 – 60 – 60 mA

AS7C34098 – 60 – 60 – 60 – 60 mA

AS7C4098 – – – 20 – 20 – 20 mA

CC

AS7C34098 – 20 – 20 – 20 – 20 mA

IOL = 8 mA, VCC = Min – 0.4 – 0.4 – 0.4 – 0.4 V

IOH = –4 mA, VCC = Min 2.4 – 2.4 – 2.4 – 2.4 – V

AS7C4098

AS7C34098

®

(10/12/15/20) 4.5 5.0 5.5 V

CC

(–10) 3.15 3.3 3.6 V

CC

(10/12/15/20) 3.0 3.3 3.6 V

CC

IH

IH

V

IL

A

A

–10 –12 –15 –20

–1– 1 –1–1µA

–1– 1 –1–1µA

2.2 – VCC + 0.5 V

2.0 – VCC + 0.5 V

*

–0.5

–0.8V

0– 70°C

–40 – 85 °C

UnitMin Max Min Max Min Max Min Max

Capacitance (f = 1MHz, T

= 25° C, V

a

= NOMINAL)2

CC

Parameter Symbol Signals Test conditions Max Unit

Input capacitance C

I/O capacitance C

3/23/01; v.1.0 Alliance Semiconductor P. 3 of 9

IN

I/O

A, CE, WE, OE, UB, LB VIN = 0V 6 pF

I/O VIN = V

= 0V 8 pF

OUT

AS7C4098

®

AS7C34098

Read cycle (over the operating range)

Parameter Symbol

Read cycle time t

Address access time t

Chip enable (CE) access time t

Output enable (OE

) access time t

Output hold from address change t

CE Low to output in low Z t

High to output in higfch Z t

CE

OE

Low to output in low Z t

High to output in high Z t

OE

LB, UB access time t

LB

, UB Low to output in low Z t

, UB High to output in high Z t

LB

Power up time t

Power down time t

RC

AA

ACE

OE

OH

CLZ

CHZ

OLZ

OHZ

BA

BLZ

BHZ

PU

PD

3,9

–10 –12 –15 –20

Unit NotesMin Max Min Max Min Max Min Max

10 – 12 – 15 – 20 – ns

– 10 – 12 – 15 – 20 ns

– 10 – 12 – 15 – 20 ns

– 5–6–7–8ns

3 –3–3–3–ns5

0 – 3–0–0–ns4, 5

– 5 –6–7–9ns4, 5

0 – 0–0–0–ns4, 5

– 5 –6–7–9ns4, 5

– 5–6–7–8ns

0 –0–0–0–ns

– 5–6–7–9ns

0 –0–0–0–ns5

– 10 – 12 – 15 – 20 ns 5

Key to switching waveforms

Read waveform 1 (address controlled)

Address

t

OH

Data

OUT

6,7,9

Read waveform 2 (CE, OE, UB, LB controlled)

Address

t

OE

t

OLZ

CE

t

t

LZ

AA

ACE

t

AA

6,8,9

Undefined/don’t careFalling inputRising input

t

RC

t

OH

Data validPrevious data valid

t

RC

t

t

OE

t

t

OHZ

OH

CHZ

LB, UB

t

t

BLZ

Data

OUT

3/23/01; v.1.0 Alliance Semiconductor P. 4 of 9

BA

Data valid

t

BHZ

AS7C4098

AS7C34098

®

Write cycle (over the operating range)

Parameter Symbol

Write cycle time t

Chip enable (CE

) to write end t

Address setup to write end t

Address setup time t

Write pulse width (OE

Write pulse width (OE

= High) t

= Low) t

Address hold from end of write t

Data valid to write end t

Data hold time t

Write enable to output in High-Z t

Output active from write end t

Byte enable Low to write end t

Write waveform 1(WE controlled)

Address

CE

LB, UB

WE

Data

IN

Data

OUT

WC

CW

AW

AS

WP1

WP2

AH

DW

DH

WZ

OW

BW

10,11

t

11

–10 –12 –15 –20

Unit NoteMin Max Min Max Min Max Min Max

10 – 12 – 15 – 20 – ns

7–8–10–12–ns

7–8–10–12–ns

0–0–0–0–ns

7–8–10–12–ns

10 – 12 – 15 – 20 – ns

0–0–0–0–ns

5 6 7–9–ns

0–0–0–0–ns4, 5

05060709ns4, 5

3–3–3–3–ns4, 5

7 – 8 – 10 – 12 – ns 4, 5

t

WC

t

t

DH

High Z

t

AH

OW

AS

Data undefined

t

CW

t

BW

t

AW

t

WZ

t

WP

t

DW

Data valid

Write waveform 2 (CE controlled)

10,11

t

WC

Address

t

AH

CE

t

AS

t

CW

t

AW

t

BW

LB, UB

t

WP

WE

Data

Data

OUT

t

DW

IN

t

CLZ

High Z High Z

Data undefined

t

WZ

Data valid

t

DH

t

OW

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AS7C4098

®

AS7C34098

Write waveform 3

10,11

Address

t

AS

CE

LB, UB

WE

Data

IN

Data

OUT

Data retention characteristics

High Z High Z

13

Parameter Symbol Test conditions Min Max Unit

V

for data retention V

CC

Data retention current I
Chip deselect to data retention time t
Operation recovery time t
Input leakage current |I

Data retention waveform

V

CC

CE

V

CC

t

CDR

V

IH

AC test conditions

- Output load: see Figure B or Figure C.

- Input pulse level: GND to 3.0V. See Figure A.

- Input rise and fall times: 2 ns. See Figure A.

- Input and output timing reference levels: 1.5V.

+3.0V

GND

90%

10%

2 ns

Figure A: Input pulse

90%

10%

t

WC

t

t

CW

t

AW

t

BW

t

WP

t

DW

t

WZ

Data valid

AH

t

DH

Data undefined

DR

CCDR

CDR

R

|–1µA

LI

VCC = 2.0V

≥ V

CE

V

≥ V

IN

V

CC

– 0.2V or

CC

≤ 0.2V

IN

– 0.2V

2.0 – V

–500µA

0–ns

t

RC

–ns

Data retention mode

VDR ≥ 2.0V

V

DR

Thevenin equivalent:

+5V

480W

D

OUT

255W C(14)

GND

Figure B: 5V Output load

D

168W

OUT

V

CC

t

R

V

IH

+1.728V (5V and 3.3V)

+3.3V

320W

D

OUT

350W

C(14)

GND

Figure C: 3.3V Output load

Notes

1During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.
2 This parameter is sampled, but not 100% tested.
3 For test conditions, see AC Test Conditions, Figures A, B, C.

and t

4t

CLZ

5 This parameter is guaranteed, but not tested. 6WE

is High for read cycle.

and OE are Low for read cycle.

7CE
8 Address valid prior to or coincident with CE
9 All read cycle timings are referenced from the last valid address to the first transitioning address.

or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle.

10 CE
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 Not applicable.
13 2V data retention applies to commercial temperature range operation only.
14 C = 30pF, except on High Z and Low Z parameters, where C = 5pF.

3/23/01; v.1.0 Alliance Semiconductor P. 6 of 9

are specified with CL = 5pF as in Figure C. Transition is measured ±500mV from steady-state voltage.

CHZ

transition Low.

AS7C4098

AS7C34098

®

Typical DC and AC characteristics

Normalized supply current ICC, ISB

vs. supply voltage VCC

I

CC

I

SB

MIN

NOMINAL

Supply voltage (V)

Normalized access time t

vs. supply voltage V

MAX

AA

CC

SB

, I

CC

Normalized I

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

1.5

1.4

1.3

1.2

12

Normalized supply current ICC, I

vs. ambient temperature T

1.4

1.2

SB

1.0

, I

CC

0.8

0.6

0.4

Normalized I

0.2

0.0
–55 80

35–10

Ambient temperature (°C)

Normalized access time t

vs. ambient temperature T

1.5

1.4

VCC = VCC(NOMINAL)Ta = 25° C

1.3

1.2

SB

a

I

CC

Normalized supply current I

vs. ambient temperature T

625

VCC = VCC(NOMINAL)

SB1
a

25

5

1

I

SB

125

0.2

0.04

Normalized ISB1 (log scale)

–55 80

35–10

125

Ambient temperature (°C)

AA

a

Normalized supply current I

vs. cycle frequency 1/tRC, 1/t

1.4

CC

WC

1.2
VCC = VCC(NOMINAL)

1.0

CC

Ta = 25° C

0.8

1.1

1.0

Normalized access time

0.9

0.8
MIN

NOMINAL

MAX

Supply voltage (V)

Output source current I

vs. output voltage V

140

OH

OH

120

VCC = VCC(NOMINAL)PL

100

Ta = 25° C

80

60

40

20

Output source current (mA)

0

0 750

V

Output voltage (V)

1.1

1.0

Normalized access time

0.9

0.8
–55 80

35–10

125

Ambient temperature (°C)

Output sink current I

vs. output voltage V

140

OL

OL

120

VCC = VCC(NOMINAL)

100

Ta = 25° C

80

60

40

Output sink current (mA)

20

0

CC

00

V

Output voltage (V)

0.6

Normalized I

0.4

0.2

0.0
075

Cycle frequency (MHz)

Typical access time change ∆t

vs. output capacitive loading

35

30

VCC = VCC(NOMINAL)

25

(ns)

AA

20

15

10

Change in t

5

0

CC

Capacitance (pF)

5025

500250

100

AA

1000

3/23/01; v.1.0 Alliance Semiconductor P. 7 of 9

Package dimensions

O

44 43424140393837363534333231

44-pin TSOP II

1234567891011121314

A

A

1

b

e

44-pin SOJ

Pin 1

B

A1

b

AS7C4098

AS7C34098

®

3029

28

272625

23

c

A1.2
A

H

e

e

1

A

2

b 0.25 0.45
c 0.15 (typical)

1516

1718 1920

d

212422

d 18.28 18.54
e 10.06 10.26
H

e

E 0.80 (typical)

A

2

E

D

0–5

°

l

l 0.40 0.60

A 0.128 0.148
A1 0.025 -

E1

E2

A2 1.105 1.115
B 0.026 0.032
b 0.015 0.020
c 0.007 0.013

Seating

Plane

c

A2

A

E2

D 1.120 1.130
E0.370 NOM
E1 0.395 0.405
E2 0.435 0.445
e0.050 NOM

44-pin TSOP II

Min (mm) Max (mm)

0.05

0.95 1.05

11.56 11.96

44-pin SOJ 400 mils

Min(mils) Max(mils)

rdering Codes

Package Version 10 ns 12 ns 15 ns 20 ns

5V commercial NA AS7C4098-12JC AS7C4098-15JC AS7C4098-20JC

SOJ

TSOP II

: not available.

NA

3/23/01; v.1.0 Alliance Semiconductor P. 8 of 9

5V industrial NA AS7C4098-12JI AS7C4098-15JI AS7C4098-20JI

3.3V commercial AS7C34098-10JC AS7C34098-12JC AS7C34098-15JC AS7C34098-20JC

3.3V industrial NA AS7C34098-12JI AS7C34098-15JI AS7C34098-20JI

5V commercial NA AS7C4098-12TC AS7C4098-15TC AS7C4098-20TC

5V industrial NA AS7C4098-12TI AS7C4098-15TI AS7C4098-20TI

3.3V commercial AS7C34098-10TC AS7C34098-12TC AS7C34098-15TC AS7C34098-20TC

3.3V industrial NA AS7C34098-12TI AS7C34098-15TI AS7C34098-20TI

®

Part numbering system

AS7C X 4098 –XX J, T X

SRAM prefix

Blank: 5V CMOS

3: 3.3V CMOS

Device

number

Access time

Packages:

J: SOJ 400 mil

T: TSOP II 400 mil

Temperature ranges:

C: Commercial, 0°C to 70°C

I: Industrial, –40°C to 85°C

AS7C4098

AS7C34098

3/23/01; v.1.0 Alliance Semiconductor P. 9 of 9

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