Page 1
查询AS7C4096A-10JC供应商
May 2005
Preliminary
AS7C4096A
®
5.0V 512K × 8 CMOS SRAM
Features
• Pin compatible to AS7C4096
• Industrial and commercial temperature
• Organization: 524,288 words × 8 bits
• Center power and ground pins
• High speed
- 10/12/15/20 ns address access time
- 5/6 ns output enable access time
• Low power consumption: ACTIVE
- 880mW/max @ 10 ns
• Low power consumption: STANDBY
- 55mW/max CMOS
Logic block diagram
V
CC
GND
Input buffer
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Row decoder
Column decoder
524,288 × 8
Array
(4,194,304)
Sense amp
Control
Circuit
WE
OE
CE
I/O1
I/O8
• Equal access and cycle times
• Easy memory expansion with
CE, OE
• TTL-compatible, three-state I/O
• JEDEC standard packages
- 400 mil 36-pin SOJ
- 44-pin TSOP 2
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Pin arrangements
36-pin SOJ (400 mil) 44-pin TSOP 2
A0
A1
A2
A3
A4
CE
I/O1
I/O2
V
GND
I/O3
I/O4
WE
A5
A6
A7
A8
A9
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A18
A17
A16
A15
OE
I/O8
I/O7
GND
V
CC
I/O6
I/O5
A14
A13
A12
A11
A10
NC
NC
NC
A0
A1
A2
A3
A4
CE
I/O1
I/O2
V
GND
I/O3
I/O4
WE
A5
A6
A7
A8
A9
NC
NC
CC
inputs
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
A18
A17
A16
A15
OE
I/O8
I/O7
GND
V
CC
I/O6
I/O5
A14
A13
A12
A11
A10
NC
NC
NC
A10
A11
A12
A13
A14
A15
A16
A17
A18
Selection guide
–10 –12 –15 –20 Unit
Maximum address access time 10 12 15 20 ns
Maximum outputenable access time 5 6 6 6 ns
Maximum operating current 160 140 120 100 mA
Maximum CMOS standby current 10 10 10 10 mA
5/27/05, v. 1.1 Alliance Semiconductor P. 1 of 10
Copyright © Alliance Semiconductor. All rights reserved.
Page 2
AS7C4096A
®
Functional description
The AS7C4096A is a high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as
524,288 words × 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are
desired.
Equal address access and cycle times (t
for high-performance applications. The chip enable input CE
systems.
When CE
standby mode.
A write cycle is accomplished by asserting write enable (WE
on the rising edge of WE
only after outputs have been disabled with output enable (OE
A read cycle is accomplished by asserting output enable (OE
drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write
enable is active, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible, and operation is from a single 5.0V supply voltage. This device is available as
per industry standard 400-mil 36-pin SOJ and 44-pin TSOP 2 packages.
is high the device enters standby mode. The device is guaranteed not to exceed 55mW power consumption in CMOS
(write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins
, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5/6 ns are ideal
AA
permits easy memory expansion with multiple-bank memory
) and chip enable (CE). Data on the input pins I/O1–I/O8 is written
) or write enable (WE).
) and chip enable (CE), with write enable (WE) high. The chip
Absolute maximum ratings
Parameter Symbol Min Max Unit
Voltage on V
Voltage on any pin relative to GND V
Power dissipation P
Storage temperature (plastic) T
Temperature with V
DC current into output (low) I
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
relative to GND V
CC
applied T
CC
t1
t2
D
stg
bias
OUT
–0.5 +7.0 V
–0.5 VCC +0.5 V
–1.0W
–65 +150 °C
–55 +125 °C
–20mA
Truth table
CE WE OE Data Mode
H X X High Z
L H H High Z
LHL
D
OUT
Standby (ISB, I
Output disable (ICC)
Read (ICC)
SB1
)
LLX
5/27/05, v. 1.1 Alliance Semiconductor P. 2 of 10
D
IN
Write (ICC)
Page 3
®
Recommended operating condition
Parameter Symbol Min Nominal Max Unit
Supply voltage V
Input voltage
Ambient operating
temperature
*
max = V
V
IH
**
min = –1.0V for pulse width less than 5 nS.
V
IL
.
+ 1.5V for pulse width less than 5 nS.
CC
commercial T
industrial T
(10/12/15/20) 4.5 5.0 5.5 V
CC
*
V
IH
**
V
IL
A
A
DC operating characteristics (over the operating range)1
Parameter Symbol Test conditions
Input leakage
current
Output leakage
current
Operating power
supply current
Standby power
supply current
Output voltage
|I
V
V
|I
I
I
I
SB1
LI
LO
CC
SB
OL
OH
|
V
= Max, VIN = GND to V
CC
= Max, CE = V
V
|
V
CC
OUT
= GND to V
VCC = Max, CE < V
f = f
Max
, I
OUT
= 0mA
VCC = Max, CE > V
f = f
Max
, I
OUT
= 0mA
CC
IH
CC
IL
IH
–1–1–1–1µA
–1–1–1–1µA
–160–140–120–100mA
–60–55–50–40mA
VCC = Max,
CE
≥ V
– 0.2V,
V
≤ 0.2V or VIN ≥ VCC – 0.2V,
IN
CC
–10–10–10–10mA
f = 0
IOL = 6 mA, VCC = Min
I
= 8 mA, VCC = Min
OL
IOH = –4 mA, VCC = Min
–0.4–0.4–0.4–0.4
–0.5–0.5–0.5–0.5
2.4–2.4–2.4–2.4– V 4
AS7C4096A
2.2 – VCC + 0.5 V
–0.5 – 0.8 V
0– 70°C
–40 – 85 °C
–10 –12 –15 –20
Unit NotesMin Max Min Max Min Max Min Max
V4
Capacitance (f = 1MHz, Ta = 25° C, VCC = NOMINAL)
4
Parameter Symbol Signals Te st c o nd i tio n s Max Unit
Input capacitance C
I/O capacitance C
5/27/05, v. 1.1 Alliance Semiconductor P. 3 of 10
IN
I/O
A, CE, WE, OE
I/O
VIN = 0V 5 pF
= V
V
IN
= 0V 7 pF
OUT
Page 4
AS7C4096A
®
Read cycle (over the operating range)
Parameter Symbol
Read cycle time
Address access time
Chip enable (CE
Output enable (OE
) access time
) access time
Output hold from address change
CE
Low to output in low Z
CE
High to output in high Z
OE
Low to output in low Z
OE
High to output in high Z
Power up time
Power down time
t
t
AA
t
ACE
t
OE
t
OH
t
CLZ
t
CHZ
t
OLZ
t
OHZ
t
PU
t
PD
RC
Key to switching waveforms
2,8
–10 –12 –15 –20
Unit NotesMin Max Min Max Min Max Min Max
10–12–15–20–ns
–10–12–15–20ns2
–10–12–15–20ns2
–5–6–6–6ns
3–3–3–3–ns4
3–3–3–3–ns3,4
–5–6–7–9ns3,4
0–0–0–0–ns3,4
–5–6–7–9ns3,4
0–0–0–0–ns3,4
–10–12–15–20ns3,4
Undefined/don’t careFalling inputRising input
Read waveform 1 (address controlled)
Address
t
AA
D
OUT
Read waveform 2 (CE
CE
OE
D
OUT
Supply
current
, OE controlled)
t
OE
t
OLZ
t
ACE
t
CLZ
t
PU
50% 50%
t
RC1
2,5,6,8
t
RC
2,5,7,8
Data valid
Data valid
t
OH
t
OHZ
t
CHZ
t
PD
I
CC
I
SB
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Page 5
AS7C4096A
®
Write cycle (over the operating range)
Parameter Symbol
Write cycle time
Chip enable (CE
) to write end
Address setup to write end
Address setup time
Write pulse width (OE
Write pulse width (OE
= high)
= low
Address hold from end of write
Write recovery time
Data valid to write end
Data hold time
Write enable to output in high Z
Output active from write end
t
t
t
t
t
WP1
t
WP2
t
t
t
DW
t
t
t
OW
WC
CW
AW
AS
AH
WR
DH
WZ
10–12–15–20–ns
10–12–15–20–ns
Write waveform 1 (WE controlled)9
Address
WE
t
AS
D
IN
t
WZ
D
OUT
9
–10 –12 –15 –20
Unit NotesMin Max Min Max Min Max Min Max
7–8–10–12–ns
7–8–10–12–ns
0–0–0–0–ns
7–8–10–12–ns
0–0–0–0–ns
0–0–0–0–ns
5–6–7–9–ns
0–0–0–0–ns3,4
25262729ns3,4
3–3–3–3–ns3,4
t
t
AW
WC
t
WP
t
DW
Data valid
t
OW
t
t
t
WR
AH
DH
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Page 6
Write waveform 2 (CE controlled)9
Address
t
AS
CE
WE
D
IN
AC test conditions
- Output load: see Figure B.
- Input pulse level: GND to V
- Input rise and fall times: 2 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
- 0.5V. See Figures A and B.
CC
t
AW
t
WP
t
CW
t
WC
t
DW
Data valid
®
+5.0V
t
WR
t
AH
AS7C4096A
t
DH
Thevenin equivalent:
480
10
C
GND
Ω
V
CC
- 0.5V
GND
90%
10%
2 ns
Figure A: Input pulse
90%
10%
D
OUT
255
Ω
Figure B: 5.0V Output load
Notes
1During V
2 For test conditions, see AC Test Conditions.
3t
CLZ
4 This parameter is guaranteed, but not tested.
5WE
6CE
and OE are LOW for read cycle.
7 Address valid prior to or coincident with CE
8 All read cycle timings are referenced from the last valid address to the first transitioning address.
9 All write cycle timings are referenced from the last valid address to the first transitioning address.
10 C = 30pF, except at high Z and low Z parameters, where C = 5pF.
power-up, a pull-up resistor to V
CC
and t
is HIGH for read cycle.
are specified with CL = 5pF as in Figure B. Transition is measured ±500 mV from steady-state voltage.
CHZ
on CE is required to meet ISB specification.
CC
transition Low.
D
OUT
168
Ω
+1.728V
5/27/05, v. 1.1 Alliance Semiconductor P. 6 of 10
Page 7
Package dimensions
AS7C4096A
®
44434241403938 37 36 35 34333231
44-pin TSOP 2
12
3 4 5 6 7 8 9 10111213 14
A
A
1
b
D
e
36-pin SOJ
Pin 1
30 29
28 2726
25
24
23
c
44-pin TSOP 2
Min(mm) Max(mm)
A 1.2
E
E
1
A
A
0.05 0.15
1
0.95 1.05
2
b 0.30 0.45
21
15 16
17 18 19 20
22
d
A
2
0–5°
e
L
c 0.12
d 18.31 18.52
E
10.06 10.26
1
E 11.68 11.94
e 0.80 (typical)
L 0.40 0.60
0.21
36-pin SOJ 400
Min(mils) Max(mils)
A 0.128 0.148
A2
A
1
A
2
b
1
E
E
2
1
A1
b
c
E
Seating
Plane
A
b 0.015 0.020
b
1
c 0.007 0.013
D .920 .930
e 0.045 0.055
E 0.370 BSC
E
1
E
2
0.025 –
0.105 0.115
0.026 0.032
0.395 0.405
0.435 0.445
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Page 8
AS7C4096A
®
Ordering codes
Package Ver si on 10 ns 12 ns 15 ns 20 ns
SOJ
TSOP 2
Note: Add suffix ‘N’ to the above part number for Lead Free Parts. (Ex: AS7C4096A - 10 TIN)
Part numbering system
AS7C 4096A –XX J or T X X
SRAM
prefix
Commercial AS7C4096A-10JC AS7C4096A-12JC AS7C4096A-15JC AS7C4096A-20JC
Industrial AS7C4096A-10JI AS7C4096A-12JI AS7C4096A-15JI AS7C4096A-20JI
Commercial AS7C4096A-10TC AS7C4096A-12TC AS7C4096A-15TC AS7C4096A-20TC
Industrial AS7C4096A-10TI AS7C4096A-12TI AS7C4096A-15TI AS7C4096A-20TI
Device
number
Access time
Packages:
J: SOJ 400 mil
T: TSOP 2
Temperature ranges:
C: Commercial, 0°C to 70°C
I: Industrial, –40°C to 85°C
N=Lead Free Parts
5/27/05, v. 1.1 Alliance Semiconductor P. 8 of 10
Page 9
AS7C4096A
®
Revision History
Rev. No. History Revised Date
v1.0 Initial release 11/08/04
v1.1
Included I
Corrected the following: T
, ISB & I
CC
parameters
SB1
OE
, V
IH, VOL
& t
05/27/05
WZ
5/27/05, v. 1.1 Alliance Semiconductor P. 9 of 10
Page 10
®
AS7C4096A
®
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel: 408 - 855 - 4900
Copyright © Alliance Semiconductor
All Rights Reserved
Part Number: AS7C4096A
Document Version: v. 1.1
Fax: 408 - 855 - 4999
www.alsc.com
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered
trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make
changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document.
The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at
any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in
this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any
guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product
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