Datasheet AS7C4096-12TI, AS7C4096-12TC, AS7C4096, AS7C4096-20TI, AS7C4096-20TC Datasheet (Alliance Semiconductor Corporation)

March 2001

5V/3.3V 512K × 8 CMOS SRAM

Features

• AS7C4096 (5V version)

• AS7C34096 (3.3V version)

• Industrial and commercial temperature

• Organization: 524,288 words × 8 bits

• Center power and ground pins

• High speed

- 10/12/15/20 ns address access time

- 5/6/7/8 ns output enable access time

• Low power consumption: ACTIVE

- 1375 mW (AS7C4096) / max @ 12 ns

- 468 mW (AS7C34096) / max @ 12 ns

®

• Low power consumption: STANDBY

- 110 mW (AS7C4096) / max CMOS

- 72 mW (AS7C34096) / max CMOS

• 2.0V data retention

• Equal access and cycle times

• Easy memory expansion with CE

, OE inputs

• TTL-compatible, three-state I/O

• JEDEC standard packages

- 400 mil 36-pin SOJ

- 400 mil 44-pin TSOP II

• ESD protection ≥ 2000 volts

• Latch-up current ≥ 200 mA

AS7C4096

AS7C34096

Logic block diagram

V

CC

GND

Input buffer

A0
A1
A2
A3
A4
A5
A6
A7
A8

A9

Row decoder

Column decoder

A10

524,288 × 8

(4,194,304)

A11

Selection guide

Maximum address
access time

Maximum output
enable access time

Maximum operating
current

Maximum CMOS standby
current

Pin arrangement

36-pin SOJ (400 mil) 44-pin TSOPII(400 mil)

NC

1

NC

1

36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19

–15

NC
A18
A17
A16
A15
OE
I/O8
I/O7
GND

V

CC

I/O6
I/O5
A14
A13
A12
A11
A10
NC

A0
A1
A2
A3
A4

CE
I/O1
I/O2

V

GND
I/O3
I/O4

WE

A5
A6
A7
A8
A9

Array

A12

A0
A1
A2
A3
A4

I/O1

Sense amp

Control

Circuit

A13

A14

A15

A16

A17

A18

I/O8

WE
OE
CE

CE
/O1
/O2

V

ND
/O3
/O4

WE

A5
A6
A7
A8
A9

AS7C4096

AS7C34096

–10

AS7C34096

–12

2
3
4
5
6
7
8
9

CC

10
11
12
13
14
15
16
17
18

AS7C4096

AS7C34096

10 12 15 20 ns

56 7 9ns

AS7C4096 – 250 220 180 mA

AS7C34096 160 130 110 100 mA

AS7C4096 – 20 20 20 mA

AS7C34096 20 20 20 20 mA

2
3
4
5
6
7
8
9
10
11

CC

12
13
14
15
16
17
18
19
20

NC

21

NC

22

AS7C4096

AS7C34096

–20 Unit

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

NC
NC
NC

A18
A17

A16
A15
OE
I/O8
I/O7
GND

V

CC

I/O6
I/O5
A14
A13
A12
A11
A10
NC
NC
NC

3/23/01; v.1.1 Alliance Semiconductor P. 1 of 10

Copyright © Alliance Semiconductor. All rights reserved.

AS7C4096

AS7C34096

®

Functional description

The AS7C4096 and AS7C34096 are high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) devices
organized as 524,288 words × 8 bits. They are designed for memory applications where fast data access, low power, and simple
interfacing are desired.

Equal address access and cycle times (t
ideal for high-performance applications. The chip enable input CE
systems.

When CE

is high the device enters standby mode. The AS7C4096 is guaranteed not to exceed 110 mW power consumption in

CMOS standby mode. Both devices offer 2.0V data retention.

A write cycle is accomplished by asserting write enable (WE
on the rising edge of WE

(write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins

only after outputs have been disabled with output enable (OE

A read cycle is accomplished by asserting output enable (OE
I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write
enable is active, output drivers stay in high-impedance mode.

All chip inputs and outputs are TTL-compatible, and operation is from a single supply voltage. Both devices are available in the
industry standard 400-mil 36-pin SOJ and 44-pin TSOP II packages.

, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5/6/7/8 ns are

AA

permits easy memory expansion with multiple-bank memory

) and chip enable (CE). Data on the input pins I/O1–I/O8 is written

) or write enable (WE).

) and chip enable (CE), with write enable (WE) high. The chip drives

Absolute maximum ratings

Parameter Device Symbol Min Max Unit

Vol tag e o n V

relative to GND

CC

AS7C4096 V

AS7C34096 V
Voltage on any pin relative to GND V
Power dissipation P
Storage temperature (plastic) T
Te m p er a t u re w i t h V

applied T

CC

DC current unto output (low) I

NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional oper-
ation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.

t1

t1

t2

D

stg

bias

OUT

–1 +7.0 V –0.5 +5.0 V –0.5 VCC +0.5 V

–1.0W

–65 +150 °C –55 +125 °C

–20mA

Truth table

CE

HXX High Z Standby (I

LHH High Z Output disable (I
LHL D
LLX D

Key: X = Don’t care, L = Low, H = High

WE OE Data Mode

OUT

IN

Read (ICC)

Write (ICC)

, I

)

SB

SB1

)

CC

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Recommended operating condition

Parameter Device Symbol Min Nominal Max Unit

Supply voltage

Input voltage

Ambient operating
temperature

†

VIL min = –3.0V for pulse width less than tRC/2.

commercial T
industrial T

AS7C4096 V AS7C34096 V AS7C34096 V

(12/15/20) 4.5 5.0 5.5 V

CC

CC

(12/15/20) 3.0 3.3 3.6 V

CC

AS7C4096 V AS7C34096 V

AS7C4096

AS7C34096

®

(–10) 3.15 3.30 3.6 V

IH

IH

V

IL

A

A

2.2 – VCC + 0.5 V

2.0 – VCC + 0.5 V

†

–0.5

–0.8V

0– 70°C

–40 – 85 °C

DC operating characteristics (over the operating range)

Parameter Symbol Test conditions Device

Input leakage

current
Output

leakage
current

Operating

power supply

current

Standby

power supply

current

Output voltage

Capacitance (f = 1MHz, T

Input capacitance C
I/O capacitance C

|I

|VCC = Max, VIN = GND to V

|I

LI

= Max, CE = V

V

|

LO

I

CC

I

SB

CC

V

= GND to V

OUT

VCC = Max, CE < V

f = f

Max

, I

OUT

= 0mA

VCC = Max, CE = V
f = f

Max

, I

OUT

= 0mA

VCC = Max,

I

CE

≥ V

SB1

V

OL

V

OH

– 0.2V, V

CC

V

CC

IOL = 8 mA, VCC = Min – 0.4 – 0.4 – 0.4 – 0.4 V

IOH = –4 mA, VCC = Min 2.4 – 2.4 – 2.4 – 2.4 – V

= 25° C, V

a

≤ 0.2V or VIN ≥

IN

– 0.2V, f = 0

CC

CC

IH

CC

AS7C4096 – – – 250 – 220 – 180 mA

IL

AS7C34096 – 160 – 130 – 110 – 100

IH

AS7C4096 – – – 60 – 60 – 60

AS7C34096 – 60 – 60 – 60 – 60

AS7C4096 – – – 20 – 20 – 20

AS7C34096 – 20 – 20 – 20 – 20

= NOMINAL)2

Parameter Symbol Signals Test conditions Max Unit

IN

I/O

A, CE, WE, OE VIN = 0V 5 pF

1

–10 –12 –15 –20

–1–1–1–1µA

–1–1–1–1µA

I/O VIN = V

= 0V 7 pF

OUT

UnitMin Max Min Max Min Max Min Max

mA

mA

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AS7C4096

AS7C34096

®

Read cycle (over the operating range)

Parameter Symbol

Read cycle time t
Address access time t
Chip enable (CE
Output enable (OE

) access time t

) access time t

Output hold from address change t

Low to output in low Z t

CE
CE

High to output in high Z t

OE

Low to output in low Z t

OE

High to output in high Z t
Power up time t
Power down time t

RC

AA

ACE

OE

OH

CLZ

CHZ

OLZ

OHZ

PU

PD

Key to switching waveforms

Read waveform 1 (address controlled)

Address

3,9

–10–12–15–20

Unit NotesMin Max Min Max Min Max Min Max

10 – 12 – 15 – 20 – ns

–10–12–15–20ns3 –10–12–15–20ns3 –5–6–7–8ns 3–3–3–3–ns5 3–3–0–0–ns4, 5 –5–6–7–9ns4, 5 0–0–0–0–ns4, 5 –5–6–7–9ns4, 5 0–0–0–0–ns4, 5 –10–12–15–20ns4, 5

Undefined/don’t careFalling inputRising input

3,6,7,9

t

RC

t

AA

D

OUT

Read waveform 2 (CE, OE controlled)

CE

t

OE

t

ACE

D

OUT

t

CLZ

Supply

current

t

PU

3,6,8,9

t

RC1

OE

t

OLZ

50% 50%

Write cycle (over the operating range)11

Parameter Symbol

Write cycle time t
Chip enable (CE

) to write end t

WC

CW

10 – 12 – 15 – 20 – ns

7–8–10–12–ns

t

OH

Data valid

t

OHZ

t

CHZ

Data valid

t

PD

–10 –12 –15 –20

I

CC

I

SB

Unit NotesMin Max Min Max Min Max Min Max

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Parameter Symbol

Address setup to write end t
Address setup time t
Write pulse width (OE
Write pulse width (OE

= high) t

= low t
Address hold from end of write t
Data valid to write end t
Data hold time t
Write enable to output in high Z t
Output active from write end t

AW

AS

WP1

WP2

AH

DW

DH

WZ

OW

AS7C4096

AS7C34096

®

–10–12–15–20

Unit NotesMin Max Min Max Min Max Min Max

7–8–10–12–ns
0–0–0–0–ns
7–8–10–12–ns

10 – 12 – 15 – 20 – ns

0–0–0–0–ns 5–6–7–9–ns 0–0–0–0–ns4, 5 05060709ns4, 5 3–3–3–3–ns4, 5

Write waveform 1 (WE controlled)

Address

WE

t

AS

D

IN

D

OUT

Write waveform 2 (CE controlled)

Address

t

AS

CE

WE

D

IN

10,11

10,11

t

t

WZ

WZ

t

WC

t

AW

t

WP

t

DW

Data valid

t

WC

t

AW

t

CW

t

WP

t

DW

Data valid

t

AH

t

DH

t

OW

t

AH

t

DH

D

OUT

Data retention characteristics (over the operating range)13

Parameter Symbol Test conditions Min Max Unit

for data retention V

V

CC

Data retention current I
Chip deselect to data retention time t
Operation recovery time t
Input leakage current |I

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DR

CCDR

CDR

R

|–1µA

LI

VCC = 2.0V

CE

≥ V

V

≥ V

IN

V

CC

CC

≤ 0.2V

IN

– 0.2V

– 0.2V or

2.0 – V

– 500 µA

0–ns

t

RC

–ns

Data retention waveform

AS7C4096

AS7C34096

®

Data retention mode

V

CC

CE

V

CC

t

CDR

V

IH

VDR ≥ 2.0V

V

DR

AC test conditions

- Output load: see Figure B or Figure C.

- Input pulse level: GND to 3.0V. See Figures A, B, and C.

- Input rise and fall times: 2 ns. See Figure A.

- Input and output timing reference levels: 1.5V.

+3.0V

GND

90%

10%

2 ns

Figure A: Input pulse

90%

10%

D

OUT

255W C(14)

Figure B: 5V Output load

Notes

1During V
2 This parameter is sampled, but not 100% tested.
3 For test conditions, see AC Test Conditions.
4t

CLZ

5 This parameter is guaranteed, but not tested. 6WE 7CE 8 Address valid prior to or coincident with CE 9 All read cycle timings are referenced from the last valid address to the first transitioning address. 10 CE 11 All write cycle timings are referenced from the last valid address to the first transitioning address. 12 Not applicable. 13 2V data retention applies to commercial temperature range operation only. 14 C = 30pF, except at high Z and low Z parameters, where C = 5pF.

power-up, a pull-up resistor to V

CC

and t

is HIGH for read cycle.

and OE are LOW for read cycle.

or WE must be HIGH during address transitions. Either CE or WE asserting high terminates a write cycle.

are specified with CL = 5pF as in Figure C. Transition is measured ±500 mV from steady-state voltage.

CHZ

on CE is required to meet ISB specification.

CC

transition Low.

+5V

480W

GND

V

CC

t

R

V

IH

Thevenin equivalent:

OUT

168W

+1.728V

D

+3.3V

320W

D

OUT

350W C(14)

GND

Figure C: 3.3V Output load

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AS7C4096

AS7C34096

®

Typical DC and AC characteristics

Normalized supply current ICC, I

vs. supply voltage V

1.4

1.2
I

SB

1.0

, I

CC

0.8

CC

0.6
I

0.4

Normalized I

SB

0.2

0.0

MIN

NOMINAL

Supply voltage (V)

Normalized access time t

vs. supply voltage V

1.5

1.4

Ta = 25° C

1.3

1.2

SB

CC

MAX

AA

CC

12

Normalized supply current ICC, I

vs. ambient temperature T

1.4

1.2

SB

1.0

, I

CC

0.8

0.6

0.4

Normalized I

0.2

0.0
–55 80 12535–10

Ambient temperature (°C)

Normalized access time t
vs. ambient temperature T

1.5

VCC = VCC(NOMINAL) VCC = VCC(NOMINAL)

1.4

1.3

1.2

SB

a

I

CC

Normalized supply current I

vs. ambient temperature T

625

VCC = VCC(NOMINAL)

SB1
a

25

(log scale)

5

SB1

1

I

SB

0.2

Normalized I

0.04

–55 80

35–10

125

Ambient temperature (°C)

AA

a

Normalized supply current I

vs. cycle frequency 1/tRC, 1/t

1.4

CC

WC

1.2

1.0

Ta = 25° C

CC

0.8

Normalized access time

1.1

1.0

0.9

0.8
MIN

NOMINAL

MAX

Supply voltage (V)

Output source current I

vs. output voltage V

140

VCC = VCC(NOMINAL) VCC = VCC(NOMINAL) VCC = VCC(NOMINAL)

120

Ta = 25° C Ta = 25° C

100

OH

OH

1.1

1.0

Normalized access time

0.9

0.8
–55 80

35–10

Ambient temperature (°C)

Output sink current I

vs. output voltage V

140

120

100

OL

OL

125

0.6

Normalized I

0.4

0.2

0.0

35

30

25

(ns)

80

60

40

20

Output source current (mA)

0

0 750 1000500250

Output voltage (V)

V

CC

80

60

40

Output sink current (mA)

20

0

00

Output voltage (V)

V

20

AA

15

10

Change in t

5

0

CC

075

5025

100

Cycle frequency (MHz)

Typical access time change ∆t

vs. output capacitive loading

AA

Capacitance (pF)

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Package dimensions

44434241403938 373635 34333231

44-pin TSOP II

1234567891011121314

A

A

1

b

AS7C4096

AS7C34096

®

44-pin TSOP II

3029

282726

25

24

23

c

A1.2
A
A

E

E

1

b 0.30 0.45 c 0.15 (typical) d 18.28 18.54

21

1516

171819 20

d

22

E E 11.56 11.96 e 0.80 (typical)

A

2

e

0–5°

L

L 0.40 0.60

Min(mm) Max(mm)

1

2

1

0.05 0.15

0.95 1.05

10.03 10.16

36-pin SOJ 400

Min(mils) Max(mils)

A .128 0.148 A

1

A

2

0.027 –

0.102 NOM b 0.015 0.020 b

1

0.026 0.032

c 0.007 0.013

Pin 1

D

e

E1E

36-pin SOJ

2

A1

b

A

b

1

Seating

Plane

D .920 .930

c

A2

E

e 0.045 0.055 E 0.400 NOM E 0.435 0.445

Ordering codes

Package Version 10 ns 12 ns 15 ns 20 ns

5V commercial NA AS7C4096-12JC AS7C4096-15JC AS7C4096-20JC

SOJ

TSOP II

NA: not available.

5V industrial NA AS7C4096-12JI AS7C4096-15JI AS7C4096-20JI

3.3V commercial AS7C4096-10JC AS7C34096-12JC AS7C34096-15JC AS7C34096-20JC

3.3V industrial NA AS7C34096-12JI AS7C34096-15JI AS7C34096-20JI

5V commercial NA AS7C4096-12TC AS7C4096-15TC AS7C4096-20TC

5V industrial NA AS7C4096-12TI AS7C4096-15TI AS7C4096-20TI

3.3V commercial AS7C4096-10TC AS7C34096-12TC AS7C34096-15TC AS7C34096-20TC

3.3V industrial NA AS7C34096-12TI AS7C34096-15TI AS7C34096-20TI

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®

Part numbering system

AS7C X 4096 –XX J, T X

SRAM

prefix

Blank: 5V CMOS

3: 3.3V CMOS

Device

number

Access

time

Package:

J: 400-mil SOJ

T: 400-mil TSOP II

Temperature ranges:

C: Commercial, 0° C to 70° C

I: Industrial, -40° C to 85° C

AS7C4096

AS7C34096

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© Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names
may be the trademarks of their respective companies. Alliance re serves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors
that may appear in this document. The da ta c ontaine d herein represents Alliance’s be s t data a nd/or e s timate s at the time of issuance. Alliance reserves the right to change or correct this data at any time, without
notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information
for potential customers and users, and is not intended to operate as, or provide, any guarantee or warra ntee to any user or customer. Alliance does not assume any responsibility or liability arising out of the
application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products i ncluding lia bility or warranties related to fi tne ss for a par­ticular purpose, merchantability , or infringement of any intellectual property rights , except as express agreed to in Alliance’s Ter ms and Conditions of Sale (which are available from Alliance ). All sales of Alli­ance products are made exclusively according to A lliance’s Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights, mask works
rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or
failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and
agrees to indemnify Alliance against all claims arising from such use.

AS7C4096

AS7C34096

®

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