Datasheet AS7C3513, AS7C3513-20TC, AS7C3513-20JC, AS7C3513-15TC, AS7C3513-15JC Datasheet (Alliance Semiconductor Corporation)

March 2001

Features

• AS7C513 (5V version)

• AS7C3513 (3.3V version)

• Industrial and commercial temperature

• Organization: 32,768 words × 16 bits

• Center power and ground pins

•High speed

- 12/15/20 ns address access time

- 6,7,8 ns output enable access time

• Low power consumption: ACTIVE

- 800 mW (AS7C513) / max @ 12 ns

- 432 mW (AS7C3513) / max @ 12 ns

®

5V/3.3V 32K×16 CMOS SRAM

• Low power consumption: STANDBY

- 28 mW (AS7C513) / max CMOS

- 18 mW (AS7C3513) / max CMOS

• 2.0V data retention

• Easy memory expansion with CE

• TTL-compatible, three-state I/O

• 44-pin JEDEC standard package

-400 mil SOJ

-400 mil TSOP II

• ESD protection ≥ 2000 volts

• Latch-up current ≥ 200 mA

AS7C513

AS7C3513

, OE inputs

Logic block diagram

A0

A1

A2

A3

A4

A5

A6

A7

I/O0–I/O7

I/O8–I/O15

WE

UB

OE

LB

CE

Row decoder

I/O

buffer

32K × 16

Array

Control circuit

Column decoder

A8

A9

A10

A11

A12

A13

A14

V

CC

GND

Pin arrangement

44-Pin SOJ, TSOP II (400 mil)

1NC

44

A4

43

A5

42

A6

41

OE
UB

40

LB

39

I/O15

38

I/O14

37

I/O13

36

I/O12

35

GND

34

V

33

CC

I/O11

32

I/O10

31

I/O9

30

I/O8

29

NC

28

A7

27

A8

26

A9

25

A10

24

NC

23

I/O0
I/O1
I/O2
I/O3

V
GND
I/O4
I/O5
I/O6
I/O7

WE

A14
A13
A12
A11

2A3
3A2
4A1
5

A0

6

CE

7
8
9
10
11

CC

12
13

AS7C513

AS7C3513

14
15
16
17
18
19
20
21
22

NC

Selection guide

AS7C513-12

AS7C3513-12

Maximum address access time 12 15 20 ns

Maximum output enable access time 5 7 9 ns

AS7C513 160 150 140 mA

Maximum operating current

AS7C3513 120 110 100 mA

AS7C513 5 5 5 mA

Maximum CMOS standby current

AS7C3513 5 5 5 mA

Shaded areas indicate advance information.

AS7C513-15

AS7C3513-15

AS7C513-20

AS7C3513-20 Unit

3/23/01; v.1.0

Alliance Semiconductor

P. 1 of 10

Copyright © Alliance Semiconductor. All rights reserved.

AS7C513

AS7C3513

®

Functional description

The AS7C513 and the AS7C3513 are high performance CMOS 524,288-bit Static Random Access Memory (SRAM) devices organized as
32,768 words × 16 bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired.

Equal address access and cycle times (tAA, tRC, tWC) of 12/15/20 ns with output enable access times (tOE) of 6,7,8 ns are ideal for high
performance applications. The chip enable input CE

When CE
consumption in CMOS standby mode. The devices also offer 2.0V data retention.

A write cycle is accomplished by asserting write enable (WE), (UB) and/or (LB), and chip enable (CE). Data on the input pins I/O0-I/O7,
and/or I/O8–I/O15, is written on the rising edge of WE
should drive I/O pins only after outputs have been disabled with output enable (OE

A read cycle is accomplished by asserting output enable (OE
drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is
active, or (UB) and (LB), output drivers stay in high-impedance mode.

The devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and
read. LB controls the lower bits, I/O0–I/O7, and UB controls the higher bits, I/O8–I/O15.

All chip inputs and outputs are TTL-compatible. The AS7C513 and AS7C3513 are packaged in common industry standard packages.

is high, the devices enter standby mode. The AS7C513 and AS7C3513 are guaranteed not to exceed 28/18 mW power

permits easy memory expansion with multiple-bank memory systems.

(write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices

) or write enable (WE).

), (UB) and (LB), and chip enable (CE), with write enable (WE) high. The chips

Absolute maximum ratings

Parameter Device Symbol Min Max Unit

Vo l t ag e o n V

relative to GND

CC

AS7C3513 V

Voltage on any pin relative to GND V

Power dissipation P

Storage temperature (plastic) T

AS7C513 V

Ambient temperature with V

applied T

CC

DC current into outputs (low) I

NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.

t1

t1

t2

D

stg

bias

OUT

–0.50 +7.0 V

–0.50 +5.0 V

–0.50 VCC +0.50 V

–1.0W

–65 +150

–55 +125

o

C

o

C

–50mA

Truth table

CE

H X X X X High Z High Z Standby (I

LHLLHD

LHLHLHigh ZD

LHLLLD

LLXLLD

LLXLHD

LLXHLHigh ZD

L
L

Key: X = Don’t care; L = Low; H = High

3/23/01; v. 1.0

WE OE LB UB I/O0–I/O7 I/O8–I/O15 Mode

OUT

OUT

IN

IN

H
X

H
X

X
H

X
H

High Z High Z Output disable (I

High Z Read I/O0–I/O7 (ICC)

Read I/O8–I/O15 (ICC)

Read I/O0–I/O15 (ICC)

Write I/O0–I/O15 (ICC)

D

D

OUT

OUT

IN

High Z Write I/O0–I/O7 (ICC)

IN

Write I/O8–I/O15 (ICC)

Alliance Semiconductor

, I

)

SB

SBI

)

CC

P. 2 of 10

AS7C513

AS7C3513

®

Recommended operating conditions

Parameter Device Symbol Min Typical Max Unit

Supply voltage

Input voltage

commercial T

Ambient operating temperature

industrial T

†

VIL min = –3.0V for pulse width less than tRC/2.

AS7C513 V

AS7C3513 V

AS7C513 V

AS7C3513 V

CC

CC

IH

IH

V

IL

A

A

4.5 5.0 5.5 V

3.0 3.3 3.6 V

2.2 – VCC + 0.5 V

2.0 – VCC + 0.5

–0.5†–0.8V

0– 70 ° C

–40 – 05 ° C

DC operating characteristics (over the operating range)1

-12 -15 -20

Parameter Symbol Test conditions Device

Input leakage current | I

Output leakage current | I

Operating power supply
current

|

LI

|

LO

I

CC

I

SB

Standby power supply
current

I

SB1

V

Output voltage

Shaded areas indicate advance information.

OL

V

OH

V

= Max

CC

V

= GND to V

IN

V

= Max

CC

V

= GND to V

OUT

V

= Max, CE ≤ V

CC

f = f

V
f = f

V
V
V

, I

Max

OUT

= Max, CE ≤ V

CC

, I

Max

OUT

= Max, CE ≥ V

CC

≤ GND + 0.2V or

IN

≥ V

IN

–0.2V, f = 0

CC

CC

CC

IL

= 0mA

IL

= 0mA

CC

–0.2V

AS7C513 – 160 – 150 – 140

AS7C3513 – 120 – 110 – 100

AS7C513 – 40 – 40 – 40

AS7C3513 – 40 – 40 – 40

AS7C513 – 3 – 3 – 3

AS7C3513–3–3–3

–1–1–1µA

–1–1–1µA

IOL = 8 mA, VCC = Min – 0.4 – 0.4 – 0.4 V

IOH = –4 mA, VCC = Min 2.4–2.4–2.4– V

UnitMin Max Min Max Min Max

mA

mA

mA

Capacitance (f = 1MHz, Ta = 25o C, VCC = NOMINAL)

2

Parameter Symbol Signals Test conditions Max Unit

Input capacitance C

I/O capacitance C

3/23/01; v. 1.0

IN

I/O

A, CE, WE, OE, LB, UB

I/O Vin = V

Alliance Semiconductor

Vin = 0V 5 pF

= 0V 7 pF

out

P. 3 of 10

AS7C513

AS7C3513

®

Read cycle (over the operating range)

3,9

Parameter Symbol

Read cycle time t

Address access time t

Chip enable (CE

Output enable (OE

) access time t

) access time t

Output hold from address change t

Low to output in low Z t

CE

CE

High to output in high Z t

OE

Low to output in low Z t

Byte select access time t

Byte select Low to low Z t

Byte select High to high Z t

High to output in high Z t

OE

Power up time t

Power down time t

Shaded areas indicate advance information.

RC

AA

ACE

OE

OH

CLZ

CHZ

OLZ

BA

BLZ

BHZ

OHZ

PU

PD

Key to switching waveforms

Read waveform 1 (address controlled)

Address

t

OH

Data OUT

3,6,7,9

t

AA

-12 -15 -20

Unit NotesMinMaxMinMaxMinMax

12 – 15 – 20 – ns

–12–15–20ns3

–12–15–20ns3

–6–7–8ns

3–4–4–ns5

0 – 0 – 0 – ns 4, 5

–6–7–8ns4, 5

0 – 0 – 0 – ns 4, 5

–6–7–8ns

0 – 0 – 0 – ns 4,5

–6–7–9ns4,5

–6–7–9ns4, 5

0 – 0 – 0 – ns 4, 5

–12–15–20ns4, 5

Undefined output/don’t careFalling inputRising input

t

RC

t

OH

Data validPrevious data valid

Read waveform 2 (CE, OE, UB, LB controlled)

Address

t

AA

OE

t

OLZ

CE

t

ACE

t

LZ

LB, UB

t

BLZ

Data OUT

3/23/01; v. 1.0

Alliance Semiconductor

3,6,8,9

t

OE

t

BA

t

RC

t

OH

t

OHZ

t

HZ

t

BHZ

Data valid

P. 4 of 10

AS7C513

AS7C3513

®

Write cycle (over the operating range)

11

Parameter Symbol

Write cycle time t

Chip enable (CE

) to write end t

Address setup to write end t

Address setup time t

Write pulse width t

Address hold from end of write t

Data valid to write end t

Data hold time t

Write enable to output in high Z t

Output active from write end t

Byte select Low to end of write t

Shaded areas indicate advance information.

Write waveform 1(WE controlled)

10,11

WC

CW

AW

AS

WP

AH

DW

DH

WZ

OW

BW

-12 -15 -20

Unit NotesMin Max Min Max Min Max

12 – 15 – 20 – ns

9 – 10 – 12 – ns

8 – 10 – 12 – ns

0–0–0– ns

8 – 10 – 12 – ns

0–0–0– ns

6–8–10– ns

0–0–0– ns 5

–6–7–9 ns 4, 5

3–3–3– ns 4, 5

8–9–12– ns

t

WC

Address

LB, UB

WE

Data IN

Data OUT

Write waveform 2 (CE controlled)

Address

t

AS

CE

LB, UB

WE

Data IN

t

CLZ

Data OUT

High-Z High-Z

t

AS

Data undefined

10,11

Data undefined

t

BW

t

AW

t

WP

t

DW

t

DH

Data valid

t

WZ

t

OW

High-Z

t

WC

t

t

CW

t

AW

t

BW

t

WP

t

DW

AH

t

DH

Data valid

t

WZ

t

OW

3/23/01; v. 1.0

Alliance Semiconductor

P. 5 of 10

AS7C513

AS7C3513

®

Data retention characteristics (over the operating range)13

Parameter Symbol Test conditions Min Max Unit

V

for data retention V

CC

Data retention current I

Chip deselect to data retention time t

Operation recovery time t

Input leakage current | I

DR

CCDR

CDR

R

| –1µA

LI

VCC = 2.0V

CE

≥ V

≥ V

V

IN

V

IN

–0.2V

CC

–0.2V

CC

≤ 0.2V

2.0 – V

– 500 µA

0–ns

or

t

RC

–ns

Data retention waveform

Data retention mode

V

CC

CE

V

CC

t

CDR

V

IH

V

≥ 2.0V

DR

V

DR

AC test conditions

- Output load: see Figure B or Figure C.

- Input pulse level: GND to 3.0V. See Figure A.

- Input rise and fall times: 2 ns. See Figure A.

- Input and output timing reference levels: 1.5V.

+3.0V

GND

90%

10%

Figure A: Input pulse

2 ns

90%

10%

D

out

255

Ω

Figure B: 5V Output load

+5V

480

C

(14)

GND

Ω

Notes

1During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.

2 This parameter is sampled, but not 100% tested.

3 For test conditions, see AC Test Conditions, Figures A, B, and C.

4 These parameters are specified with C

5 This parameter is guaranteed, but not 100% tested.

6WE

is High for read cycle.

and OE are Low for read cycle.

7CE

8 Address valid prior to or coincident with CE

9 All read cycle timings are referenced from the last valid address to the first transitioning address.

10 CE

or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle.

11 All write cycle timings are referenced from the last valid address to the first transitioning address.

12 Not applicable.

13 2V data retention applies to the commercial operating range only.

14 C=30pF, except on High Z and Low Z parameters, where C=5pF.

= 5pF, as in Figures B or C. Transition is measured ±500mV from steady-state voltage.

L

transition Low.

V

CC

t

R

V

IH

Thevenin equivalent:

168

D

out

Ω

+1.728V (5V and 3.3V)

+3.3V

320

D

out

350

Ω

Ω

C

(14)

GND

Figure C: 3.3V Output load

3/23/01; v. 1.0

Alliance Semiconductor

P. 6 of 10

Typical DC and AC characteristics

Normalized supply current ICC, I

vs. supply voltage V

1.4

SB

CC

®

Normalized supply current ICC, I

vs. ambient temperature T

1.4

AS7C513

AS7C3513

SB

a

Normalized supply current ISB1

vs. ambient temperature T

a

1.2

SB

1.0

, I

CC

0.8

0.6

0.4

Normalized I

0.2

0.0

1.5

1.4

1.3

1.2

1.1

1.0

Normalized access time

0.9

I

CC

I

SB

MIN

NOMINAL

Supply voltage (V)

Normalized access time t

vs. supply voltage V

CC

AA

MAX

1.2

SB

1.0

, I

CC

0.8

0.6

0.4

Normalized I

0.2

0.0
–55 80

Ambient temperature (°C)

Normalized access time t
vs. ambient temperature T

1.5

1.4

VCC = VCC(NOMINAL)Ta = 25°C

1.3

1.2

1.1

1.0

Normalized access time

0.9

I

CC

625

VCC = VCC(NOMINAL)

25

(log scale)

5

SB1

1

I

SB

35–10

125

0.2

Normalized I

0.04

-55 80

35-10

125

Ambient temperature (°C)

AA

a

Normalized supply current I

vs. cycle frequency 1/tRC, 1/t

1.4

CC

WC

1.2
VCC = VCC(NOMINAL)

1.0

CC

Ta = 25°C

0.8

0.6

Normalized I

0.4

0.2

0.8
MIN

NOMINAL

MAX

Supply voltage (V)

Output source current I

vs. output voltage V

140

OH

OH

120

VCC = VCC(NOMINAL)PL

100

Ta = 25°C

80

60

40

20

Output source current (mA)

0

0 750

V

Output voltage (V)

CC

0.8
–55 80

35–10

125

Ambient temperature (°C)

Output sink current I

vs. output voltage V

140

OL

OL

120

VCC = VCC(NOMINAL)

100

Ta = 25°C

80

60

40

Output sink current (mA)

20

0

00

V

Output voltage (V)

0.0
075

Cycle frequency (MHz)

Typical access time change ∆t

vs. output capacitive loading

35

30

VCC = V

25

CC(NOMINAL)

(ns)

20

AA

15

10

Change in t

5

0

CC

Capacitance (pF)

5025

500250

100

AA

1000

3/23/01; v. 1.0

Alliance Semiconductor

P. 7 of 10

Package dimensions

44 43 42 41 40 39 38 37 36 35 34 33 32 31

44-pin TSOP II

1234567891011121314

A

A

1

b

e

44-pin SOJ

Pin 1

A1

B

b

AS7C513

AS7C3513

®

c

A1.2

A

1

A

2

b0.250.45

c 0.15 (typical)

d 18.28 18.54

e 10.06 10.26

H

e

l

E 0.80 (typical)

l0.400.60

212422

23

H

e

e

30 29

15 16

28 27 26 25

17 18 19 20

d

A

2

0–5°

E

D

A

A1

A2 1.105 1.115

B 0.026 0.032

b 0.015 0.020

c

D 1.120 1.130

E 0.370 NOM

E1 0.395 0.405

E2 0.435 0.445

e 0.050 NOM

Seating

Plane

E1

E2

c

A2

A

E2

44-pin TSOP II

Min (mm) Max (mm)

0.05

0.95 1.05

11.56 11.96

44-pin SOJ

400 mil

Min Max

0.128 0.148

0.025 -

0.007 0.013

Ordering codes

Package\Access time Volt/Temp 12 ns 15 ns 20 ns

Plastic SOJ, 400 mil

TSOP II, 18.4×10.2 mm

NA: n ot available.

5V commercial AS7C513-12JC AS7C513-15JC AS7C513-20JC

3.3V commercial AS7C3513-12JC AS7C3513-15JC AS7C3513-20JC

5V commercial AS7C513-12TC AS7C513-15TC AS7C513-20TC

3.3V commercial AS7C3513-12TC AS7C3513-15TC AS7C3513-20TC

Part numbering system

AS7C X 513 –XX X C

Commercial temperature
range: 0

Industrial temperature
range: -40C to 85C

SRAM prefix

3/23/01; v. 1.0

Voltage:Blank = 5V CMOS

3 = 3.3V CMOS

Device number Access time

Alliance Semiconductor

Package: J = SOJ 400 mil

T=TSOP II,

18.4×10.2 mm

o

C to 70 0C

P. 8 of 10

AS7C513

AS7C3513

®

3/23/01; v.1.0

© Copyright Alliance Semiconductor Corporation. All rights reser ved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other br and and product names may
be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may
appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If
the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential
customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibili ty or liability arising out of the application or use
of any product descr ibed herein, an d disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose,
merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which a re available from Alliance). All sales of Alliance prod ucts are made
exclusively according to Al liance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other
intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as cr itical components in life-supporting systems where a malfunction or failure may reasonably be expected
to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against
all claims arising from such use

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AS7C513

AS7C3513

®

3/23/01; v. 1.0

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