Datasheet AS7C33256PFS16A-133TQC, AS7C33256PFS16A-100TQI, AS7C33256PFS16A, AS7C33256PFS18A-150TQC, AS7C33256PFS18A-150TQI Datasheet (Alliance Semiconductor Corporation)

March 2001

AS7C33256PFS16A
AS7C33256PFS18A

®

3.3V 256K ×

× 16/18 pipeline burst synchronous SRAM

× ×

Features

• Organization: 262,144 words × 16 or 18 bits

• Fast clock speeds to 166 MHz in LVTTL/LVCMOS

• Fast clock to data access: 3.5/3.8/4.0/5.0 ns

•Fast OE

access time: 3.5/3.8/4.0/5.0 ns

• Fully synchronous register-to-register operation

• “Flow-through” mode

• Single-cycle deselect

- Dual-cycle deselect also available (AS7C33256PFD16A/
AS7C33256PFD18A)

Logic block diagram

LBO

CLK

ADV
ADSC
ADSP

A[17:0]

GWE

BW

BWE

BW

CE0
CE1

CE2

18

b

a

Power

ZZ

down

OE

CLK
CS

Burst logic

CLR

D

CS

CLK

Byte Write

Byte Write

Q

Address
register

DQ

DQb

registers

CLK

DQ

DQa

registers

CLK

DQ

Enable

register

CE
CLK

DQ

Enable

delay

register

CLK

18

16

256K × 16/18

18

16/18

2

OE

Output
registers

CLK

FT

Memory

array

16/18

Input

registers

CLK

DATA [17:0]

DATA [15:0]

•Pentium®

*

compatible architecture and timing

• Asynchronous output enable control

• Economical 100-pin TQFP package

• Byte write enables

• Multiple chip enables for easy expansion

• 3.3V core power supply

• 2.5V or 3.3V I/O operation with separate V

DDQ

• 30 mW typical standby power in power down mode

•NTD™

*

pipeline architecture available

(AS7C33256NTD16A/AS7C33256NTD18A)

Pin arrangement

DD

V

BWb

BWa

CE2

VSSCLK

GWE

BWEOEADSC

TQFP 14 × 20mm

SS

DD

A0

V

NC

NC

NC

NC

V

A10

A11

A12

ADSP

A13

ADVA8A9

A14

A15

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

50

A16

A17
NC
NC
V

DDQ

V

SSQ

NC
DQpa/NC
DQa
DQa
V

SSQ

V

DDQ

DQa
DQa
VSS
NC
V

DD

ZZ
DQa
DQa
V

DDQ

V

SSQ

DQa
DQa
NC
NC
V

SSQ

V

DDQ

NC
NC
NC

V

DDQ

V

DQb
DQb
V

V

DDQ

DQb
DQb

V

DQb
DQb

V

DDQ

V
DQb
DQb

DQpb/NC

V

V

DDQ

A6A7CE0

CE1NCNC

99989796959493929190898887868584838281

100

NC

1

NC

2

NC

3
4
5

SSQ

NC

6

NC

7
8
9
10

SSQ

11
12
13

FT

14
15

DD

NC

16

V

17

SS

18
19
20
21

SSQ

22
23
24

NC

25
26

SSQ

27

NC

28

NC

29

NC

30

31323334353637383940414243444546474849

A5A4A3A2A1

LBO

Note: pins 24, 74 are NC for ×16.

Selection guide

AS7C33256PFS16A

–166

Minimum cycle time 6 6.7 7.5 10 ns

Maximum pipelined clock frequency 166 150 133 100 MHz
Maximum pipelined clock access time 3.5 3.8 4 5 ns

Maximum operating current 475 450 425 325 mA
Maximum standby current 130 110 100 90 mA

Maximum CMOS standby current (DC) 30 30 30 30 mA

*

Pentium® is a registered trademark of Intel Corporation. NTD™ is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are

the property of their respective owners.

3/14/01; V.1.0 Alliance Semiconductor P. 1 of 11

AS7C33256PFS16A

–150

AS7C33256PFS16A

–133

Copyright © Alliance Semiconductor. All rights reserved.

AS7C33256PFS16A

–100 Units

AS7C33256PFS16A
AS7C33256PFS18A

®

Functional description

The AS7C33256PFS16A and AS7C33256PFS18A are high performance CMOS 4 Mbit synchronous Static Random Access Memory (SRAM)
devices organized as 262,144 words × 16 or 18 bits and incorporate a pipeline for highest frequency on any given technology.

Timing for this device is compatible with existing Pentium® synchronous cache specifications. This architecture is suited for ASIC, DSP
(TMS320C6X), and PowerPC

Fast cycle times of 6/6.7/7.5/10 ns with clock access times (t
Three chip enable inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC
or the processor address strobe (ADSP

Read cycles are initiated with ADSP
When ADSP
accessed by the current address, registered in the address registers by the positive edge of CLK, are carried to the data-out registers and driven
on the output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted but is sampled on all
subsequent clock edges. Address is incremented internally for the next access of the burst when ADV
are HIGH. Burst operation is selectable with the
sequence. With

Write cycles are performed by disabling the output buffers with OE
18 bits regardless of the state of individual BW[a:b]
BWE

BWn
BWn
internally to the next burst address if BWn

Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP follow.

• ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.

WE

•

• Master chip select CE0 blocks ADSP, but not ADSC.

The AS7C33256PFS16A and AS7C33256PFS18A operate from a 3.3V supply. I/Os use a separate power supply that can operate at 2.5V or 3.3V.
These devices are available in a 100-pin 14×20 mm TQFP packaging.

is sampled LOW, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation the data

LBO

driven LOW the device uses a linear count sequence suitable for PowerPC™ and many other applications.

and the appropriate individual byte BWn signal(s).

is ignored on the clock edge that samples ADSP LOW, but is sampled on all subsequent clock edges. Output buffers are disabled when
is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled LOW. Address is incremented

signals are sampled on the clock edge that samples ADSC LOW (and ADSP HIGH).

*

™

-based systems in computing, datacomm, instrumentation, and telecommunications systems.

) of 3.5/3.8/4.0/5.0 ns enable 166, 150, 133 and 100 MHz bus frequencies.

CD

). The burst advance pin (ADV) allows subsequent internally generated burst addresses.

(regardless of WE and ADSC) using the new external address clocked into the on-chip address register.

is sampled LOW and both address strobes

LBO

input. With

inputs. Alternately, when GWE is HIGH, one or more bytes may be written by asserting

and ADV are sampled LOW.

LBO

unconnected or driven HIGH, burst operations use a Pentium® count

and asserting a write command. A global write enable GWE writes all 16/

),

*PowerPC™ is a tradenark International Business Machines Corporation.

Capacitance

Parameter Symbol Signals Test conditions Max Unit

Input capacitance C
I/O capacitance C

IN

I/O

Address and control pins VIN = 0V 5 pF

I/O pins VIN = V

= 0V 7 pF

OUT

Write enable truth table (per byte)

GWE BWE BWn WEn

LXXT
HLLT
HHXF*
HLHF*

Key:
X = Don’t Care, L = Low, H = High, T=True, F=False
* valid read
n = a,b

WE, WEn

= internal write signal

3/14/01; V.1.0 Alliance Semiconductor P. 2 of 11

®

Signal descriptions

Signal I/O Properties Description

CLK I CLOCK Clock. All inputs except OE
A0–A17 I SYNC Address. Sampled when all chip enables are active and ADSC
DQ[a,b] I/O SYNC Data. Driven as output when the chip is enabled and OE

Master chip enable. Sampled on clock edges when ADSP

CE0

ISYNC

CE0

is inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more

information.

CE1,

ADSP

ADSC

ADV

GWE

BWE

CE2

ISYNC

ISYNC

ISYNC

I SYNC Burst advance. Asserted LOW to continue burst read/write.

ISYNC

ISYNC

Synchronous chip enables. Active HIGH and active LOW, respectively. Sampled on
clock edges when ADSC

Address strobe (processor). Asserted LOW to load a new address or to enter
standby mode.

Address strobe (controller). Asserted LOW to load a new address or to enter
standby mode.

Global write enable. Asserted LOW to write all 16/18 bits. When HIGH, BWE
BW[a,b]

control write enable.

Byte write enable. Asserted LOW with GWE
inputs.

Write enables. Used to control write of individual bytes when GWE = HIGH and

BW[a,b]

ISYNC

BWE = LOW. If any of BW[a,b] is active with GWE = HIGH and BWE = LOW the
cycle is a write cycle. If all BW[a,b]

OE

LBO

FT

IASYNC

STATIC default =

I

HIGH

ISTATIC

ZZ I ASYNC

Asynchronous output enable. I/O pins are driven when OE
in read mode.

Count mode. When driven HIGH, count sequence follows Intel XOR convention.
When driven LOW, count sequence follows linear convention. This signal is
internally pulled HIGH.

Flow-through mode.When LOW, enables single register flow-through mode.
Connect to V

if unused or for pipelined operation.

DD

Sleep. Places device in low power mode; data is retained. Connect to GND if
unused.

, FT, ZZ,

LBO

are synchronous to this clock.

is active or when CE0 and ADSP are active.

= HIGH to enable effect of BW[a,b]

are inactive, the cycle is a read cycle.

AS7C33256PFS16A
AS7C33256PFS18A

or ADSP are asserted.
is active.
or ADSC is active. When

and

is active and the chip is

Absolute maximum ratings

Parameter Symbol Min Max Unit

Power supply voltage relative to GND V
Input voltage relative to GND (input pins) V
Input voltage relative to GND (I/O pins) V
Power dissipation P
DC output current I
Storage temperature (plastic) T
Temperature under bias T

Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions may affect reliability.

3/14/01; V.1.0 Alliance Semiconductor P. 3 of 11

DD

, V

IN

IN

D

OUT

stg

bias

DDQ

–0.5 +4.6 V
–0.5 VDD + 0.5 V
–0.5 V

+ 0.5 V

DDQ

–1.8W
–50mA

–65 +150 °C
–65 +135 °C

Synchronous truth table

AS7C33256PFS16A
AS7C33256PFS18A

®

CE0

CE1

CE2 ADSP ADSC ADV WEn1 OE

Address accessed CLK Operation DQ

H X X X L X X X NA L to H Deselect Hi−Z

L L X L X X X X NA L to H Deselect Hi−Z
L L X H L X X X NA L to H Deselect Hi−Z
L X H L X X X X NA L to H Deselect Hi−Z
L X H H L X X X NA L to H Deselect Hi−Z
L H L L X X X L External L to H Begin read Hi−Z
L H L L X X X H External L to H Begin read Hi−Z
L H L H L X F L External L to H Begin read Hi−Z
L H L H L X F H External L to H Begin read Hi−Z

X X X H H L F L Next L to H Cont. read Q

X X X H H L F H Next L to H Cont. read Hi−Z

X X X H H H F L Current L to H Suspend read Q

X X X H H H F H Current L to H Suspend read Hi−Z

H X X X H L F L Next L to H Cont. read Q

H X X X H L F H Next L to H Cont. read Hi−Z

H X X X H H F L Current L to H Suspend read Q

H X X X H H F H Current L to H Suspend read Hi−Z

L H L H L X T X External L to H Begin write D

X X X H H L T X Next L to H Cont. write D

H X X X H L T X Next L to H Cont. write D

X X X H H H T X Current L to H Suspend write D

H X X X H H T X Current L to H Suspend write D

Key: X = Don’t Care, L = Low, H = High.

1

See “Write enable truth table” on page 2 for more information.

2

Q in flow through mode

3

For write operation following a READ,

OE must be HIGH before the input data set up time and held HIGH throughout the input hold

time.

2

2

3

Recommended operating conditions

Parameter Symbol Min Nominal Max Unit

V

V

V

V

V

DD

V

DDQ

SSQ

DDQ

SSQ

V

IH

V

V

IH

V

SS

IL

IL

A

Supply voltage

3.3V I/O supply
voltage

2.5V I/O supply
voltage

Address and

Input voltages

†

control pins

I/O pins

Ambient operating temperature T

min = –2.0V for pulse width less than 0.2 × tRC.

* V

IL

† Input voltage ranges apply to 3.3V I/O operation. For 2.5V I/O operation, contact factory for input specifications.

3/14/01; V.1.0 Alliance Semiconductor P. 4 of 11

3.135 3.3 3.6

0.0 0.0 0.0

3.135 3.3 3.6

0.0 0.0 0.0

2.35 2.5 2.9

0.0 0.0 0.0

2.0 – VDD + 0.3

*

–0.5

2.0 – V

*

–0.5

–0.8

+ 0.3

DDQ

–0.8

0–70°C

V

V

V

V

V

®

TQFP thermal resistance

Description Conditions Symbol Typical Units

Thermal resistance
(junction to ambient)

Thermal resistance
(junction to top of case)

* This parameter is sampled.

* Test conditions follow standard test

methods and procedures for measuring

*

thermal impedance, per EIA/JESD51

θ

θ

DC electrical characteristics

–166 –150 –133 –100

Parameter Symbol Test conditions

Input leakage

*

current
Output leakage

current
Operating power

supply current

Standby power
supply current

Output voltage

* LBO

pin has an internal pull-up and input leakage = ±10 µa.

Note: ICC give with no output loading. ICC increases with faster cycle times and greater output loading.

|ILI|VDD = Max, VIN = GND to V

OE

≥ V

, VDD = Max,

|I

|

LO

CE0

I

CC

I

SB

I

SB1

I

SB2

V

OL

V

OH

= VIL, CE1 = VIH,

Deselected, f = f

Deselected, f = 0, ZZ ≤ 0.2V

all V

Deselected, f = f

IOL = 8 mA, V

IOH = –4 mA, V

IH

V

= GND to V

OUT

f = f

, I

Max

OUT

≤ 0.2V or ≥ V

IN

All V

Max

≤ VIL or ≥ V

IN

DD

CE2

= VIL,

= 0 mA

, ZZ ≤ V

Max

– 0.2V

DD

, ZZ ≥ VDD – 0.2V

IH

= 3.465V – 0.4 – 0.4 – 0.4 – 0.4

DDQ

= 3.135V 2.4 – 2.4 – 2.4 – 2.4 –

DDQ

–2–2–2–2µA

DD

–2–2–2–2µA

–475–450–425–325mA

–130–110–100– 90

IL

– 30 – 30 – 30 – 30

– 30 – 30 – 30 – 30

AS7C33256PFS16A
AS7C33256PFS18A

JA

JC

46 °C/W

2.8 °C/W

UnitMin Max Min Max Min Max Min Max

mA

V

DC electrical characteristics for 2.5V I/O operation

–166 –150 –133 –100

Parameter Symbol Test conditions

OE

≥ V

Output leakage
current

Output voltage

|I

|

LO

V

OL

V

OH

V

IOL = 2 mA, V

IOH = –2 mA, V

IH

= GND to V

OUT

, VDD = Max,

DD

= 2.65V – 0.7 – 0.7 – 0.7 – 0.7

DDQ

= 2.35V 1.7 – 1.7 – 1.7 – 1.7 –

DDQ

–11–11–11–11µA

Timing characteristics over operating range

–166 –150 –133 –100

Parameter Symbol

Clock frequency f
Cycle time (pipelined mode) t
Cycle time (flow-through mode) t
Clock access time (pipelined mode) t

3/14/01; V.1.0 Alliance Semiconductor P. 5 of 11

Max

CYC

CYCF

CD

– 166 – 150 – 133 – 100 MHz
6 – 6.6 – 7.5 – 10 – ns

10–10–12–12–ns

–3.5–3.8–4.0–5.0ns

Unit Notes*MinMaxMinMaxMinMaxMinMax

UnitMin Max Min Max Min Max Min Max

V

Parameter Symbol

Clock access time (flow-through
mode)

Output enable LOW to data valid t
Clock HIGH to output Low Z t
Data output invalid from clock HIGH t
Output enable LOW to output Low Z t
Output enable HIGH to output High Z t
Clock HIGH to output High Z t
Output enable HIGH to invalid output t
Clock HIGH pulse width t
Clock LOW pulse width t
Address setup to clock HIGH t
Data setup to clock HIGH t
Write setup to clock HIGH t
Chip select setup to clock HIGH t
Address hold from clock HIGH t
Data hold from clock HIGH t
Write hold from clock HIGH t
Chip select hold from clock HIGH t
ADV

setup to clock HIGH t

setup to clock HIGH t

ADSP
ADSC setup to clock HIGH t
ADV

hold from clock HIGH t

hold fromclock HIGH t

ADSP
ADSC hold from clock HIGH t

*“Notes” column refers to “notes” on page 10.

t

CDF

OE

LZC

OH

LZOE

HZOE

HZC

OHOE

CH

CL

AS

DS

WS

CSS

AH

DH

WH

CSH

ADVS

ADSPS

ADSCS

ADVH

ADSPH

ADSCH

AS7C33256PFS16A
AS7C33256PFS18A

®

–166 –150 –133 –100

Unit Notes*MinMaxMinMaxMinMaxMinMax

– 9 –10–10–12ns

– 3.5 – 3.8 – 4.0 – 5.0 ns

0–0–0–0–ns2,3,4

1.5 – 1.5 – 1.5 – 1.5 – ns 2
0–0–0–0–ns2,3,4
– 3.5 – 3.8 – 4.0 – 4.5 ns 2,3,4
– 3.5 – 3.8 – 4.0 – 5.0 ns 2,3,4
0–0–0–0–ns

2.4 – 2.5 – 2.5 – 3.5 – ns 5

2.4 – 2.5 – 2.5 – 3.5 – ns 5

1.5 – 1.5 – 1.5 – 2.0 – ns 6

1.5 – 1.5 – 1.5 – 2.0 – ns 6

1.5 – 1.5 – 1.5 – 2.0 – ns 6,7

1.5 – 1.5 – 1.5 – 2.0 – ns 6,8

0.5 – 0.5 – 0.5 – 0.5 – ns 6

0.5 – 0.5 – 0.5 – 0.5 – ns 6

0.5 – 0.5 – 0.5 – 0.5 – ns 6,7

0.5 – 0.5 – 0.5 – 0.5 – ns 6,8

1.5 – 1.5 – 1.5 – 2.0 – ns 6

1.5 – 1.5 – 1.5 – 2.0 – ns 6

1.5 – 1.5 – 1.5 – 2.0 – ns 6

0.5 – 0.5 – 0.5 – 0.5 – ns 6

0.5 – 0.5 – 0.5 – 0.5 – ns 6

0.5 – 0.5 – 0.5 – 0.5 – ns 6

Key to switching waveforms

Undefined/don’t careFalling inputRising input

3/14/01; V.1.0 Alliance Semiconductor P. 6 of 11

Timing waveform of read cycle

CLK

t

ADSPS

t

ADSPH

ADSP

ADSC

t

AS

t

AH

Address

GWE, BWE

CE0, CE2

t

CSS

t

CSH

A2A1 A3

t

WS

t

WH

t

ADSCS

t

ADSCH

AS7C33256PFS16A
AS7C33256PFS18A

®

t

t

CH

t

CYC
CL

LOAD NEW ADDRESS

CE1

t

ADVS

t

ADVH

ADV

OE

t

CD

ADV INSERTS WAIT STATES

Q(A2Ý01) Q(A3Ý01) Q(A3Ý10)

Q(A2Ý10)

D

OUT

(pipelined mode)

t

LZOE

D

OUT

t

HZOE

t

OH

Q(A1)

t

OE

Q(A1)

Q(A2)

Q(A2Ý01) Q(A3Ý01) Q(A3Ý10)

(flow-through mode)

Note: Ý = XOR when MODE = HIGH/No Connect; Ý = ADD when MODE = LOW.

is don’t care.

BW[a:b]

Q(A2Ý10)

Q(A2Ý11)

Q(A2Ý11) Q(A3)

Q(A3)

t

HZC

Q(A3Ý11)

t

HZC

3/14/01; V.1.0 Alliance Semiconductor P. 7 of 11

Timing waveform of write cycle

t

CH

CLK

t

ADSPS

t

ADSPH

ADSP

ADSC

t

CYC

t

CL

AS7C33256PFS16A
AS7C33256PFS18A

®

t

ADSCS

t

ADSCH

Address

BWE

BWa,b

CE0, CE2

CE1

ADV

A1

t

AS

t

AH

ADSC LOADS NEW ADDRESS

A2 A3

t

WS

t

WH

t

CSS

t

CSH

ADV SUSPENDS BURST

t

ADVS

t

ADVH

OE

t

DS

t

DH

Data In

Note: Ý = XOR when MODE = HIGH/No Connect; Ý = ADD when MODE = LOW.

D(A1)

D(A2Ý01) D(A2Ý10) D(A3)D(A2) D(A2Ý01) D(A3Ý01) D(A3Ý10)

D(A2Ý11)

3/14/01; V.1.0 Alliance Semiconductor P. 8 of 11

Timing waveform of read/write cycle

CLK

t

ADSPS

t

ADSPH

ADSP

Address

GWE

A1

AS7C33256PFS16A
AS7C33256PFS18A

®

t

CYC

t

CH

t

A2

t

CL

AS

t

AH

A3

t

WS

t

WH

CE0, CE2

CE1

ADV

OE

D

IN

D

OUT

(pipeline mode)

D

OUT

(flow-through mode)

t

CDF

t

LZC

t

CD

Q(A1)

Q(A1)

D(A2)

t

HZOE

t

ADVS

t

ADVH

t

DS

t

DH

t

LZOE

t

OE

Q(A3)

Q(A3Ý01)

Q(A3Ý01) Q(A3Ý10)

t

OH

Q(A3Ý10) Q(A3Ý11)

Q(A3Ý11)

Note: Ý = XOR when MODE = HIGH/No Connect; Ý = ADD when MODE = LOW.

3/14/01; V.1.0 Alliance Semiconductor P. 9 of 11

AS7C33256PFS16A
AS7C33256PFS18A

®

AC test conditions

• Output load: see Figure B, except for t

• Input pulse level: GND to 3V. See Figure A.

• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.

• Input and output timing reference levels: 1.5V.

+3.0V

GND

90%

10%

90%

10%

Figure A: Input waveform

Notes

1) For test conditions, see AC Test Conditions, Figures A, B, C.

2) This parameter measured with output load condition in Figure C.

3) This parameter is sampled, but not 100% tested.
is less than t

4) t

HZOE

5) tCH measured as HIGH above VIH and tCL measured as LOW below VIL.

6) This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must

meet the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled.

7) Write refers to

8) Chip select refers to

LZOE

; and t

is less than t

HZC

GWE, BWE, BW[a:d].

,

,

CE0

CE1

CE2

.

, t

, t

= 50

0

HZOE

, t

HZC

Ω

LZC

LZOE

Z

D

OUT

Figure B: Output load (A)

at any given temperature and voltage.

LZC

, see Figure C.

Ω

50

VL = 1.5V

30 pF*

for 3.3V I/O;
= V
for 2.5V I/O

DDQ

/2

Thevenin equivalent:

+3.3V for 3.3V I/O;
+2.5V for 2.5V I/O

D

OUT

317

5 pF*

Ω

351

GND

Figure C: Output load(B)

Ω

*including scope

and jig capacitance

Package Dimensions

100-pin quad flat pack (TQFP)

TQFP

Min Max

A1 0.05 0.15
A2 1.35 1.45

b0.220.38
c0.090.20
D 13.90 14.10
E 19.90 20.10

e 0.65 nominal
Hd 15.90 16.10
He 21.90 22.10

L0.450.75

L1 1.00 nominal

α 0° 7°

Dimensions in millimeters

c

L1

L

A1 A2

He

Hd

D

b

e

E

α

3/14/01; V.1.0 Alliance Semiconductor P. 10 of 11

AS7C33256PFS16A
AS7C33256PFS18A

®

Ordering information

–166 MHz –150 MHz –133 MHz –100 MHz

AS7C33256PFS16A-166TQC AS7C33256PFS16A-150TQC AS7C33256PFS16A-133TQC AS7C33256PFS16A-100TQC

AS7C33256PFS16A-166TQI AS7C33256PFS16A-150TQI AS7C33256PFS16A-133TQI AS7C33256PFS16A-100TQI

AS7C33256PFS18A-166TQC AS7C33256PFS18A-150TQC AS7C33256PFS18A-133TQC AS7C33256PFS18A-100TQC

AS7C33256PFS18A-166TQI AS7C33256PFS18A-150TQI AS7C33256PFS18A-133TQI AS7C33256PFS18A-100TQI

Part numbering guide

AS7C 33 256 PF S 16/18 A –XXX TQ C/I

12345678910

1.Alliance Semiconductor SRAM prefix

2.Operating voltage: 33=3.3V

3.Organization: 256=256K

4.Pipeline-Flowthrough (each device works in both modes)

5.Deselect: S=Single cycle deselect

6.Organization: 16=x16; 18=x18

7.Production version: A=first production version

8.Clock speed (MHz)

9.Package type: TQ=TQFP

10.Operating temperature: C=Commercial (

0° C to 70° C); I=Industrial (

°

C to 85° C)

-40

3/14/01; V.1.0 Alliance Semiconductor P. 11 of 11

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