Datasheet AS7C33256PFD18A-166TQC, AS7C33256PFD18A-166TQI, AS7C33256PFD18A-150TQI, AS7C33256PFD18A-150TQC, AS7C33256PFD18A-133TQI Datasheet (Alliance Semiconductor Corporation)

March 2001

Copyright © Alliance Semiconductor. All rights reserved.

®

AS7C33256PFD16A
AS7C33256PFD18A

3/22/01; v.1.0 Alliance Semiconductor P. 1 of 11

3.3V 256K ×

× ×

× 16/18 pipeline burst synchronous SRAM

Features

• Organization: 262,144 words × 16 or 18 bits

• Fast clock speeds to 166 MHz in LVTTL/LVCMOS

• Fast clock to data access: 3.5/3.8/4.0/5.0 ns

•Fast OE

access time: 3.5/3.8/4.0/5.0 ns

• Fully synchronous register-to-register operation

• “Flow-through” mode

• Dual-cycle deselect

- Single-cycle deselect also available (AS7C33256PFS16A/
AS7C33256PFS18A)

•Pentium®

*

compatible architecture and timing

• Asynchronous output enable control

• Economical 100-pin TQFP package

• Byte write enables

• Multiple chip enables for easy expansion

• 3.3V core power supply

• 2.5V or 3.3V I/O operation with separate V

DDQ

• 30 mW typical standby power in power down mode

•NTD™

*

pipeline architecture available

(AS7C33256NTD16A/AS7C33256NTD18A)

Selection guide

*

Pentium® is a registered trademark of Intel Corporation. NTD™ is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are

the property of their respective owners.

–166 –150 –133 –100 Units

Minimum cycle time 6 6.7 7.5 10 ns
Maximum pipelined clock frequency 166 150 133 100 MHz

Maximum pipelined clock access time 3.5 3.8 4 5 ns
Maximum operating current 475 450 425 325 mA

Maximum standby current 130 110 100 90 mA
Maximum CMOS standby current (DC) 30 30 30 30 mA

Logic block diagram

Burst logic

ADV
ADSC
ADSP

CLK

LBO

CLK

CLR

CS

18

16

18

A[17:0]

18

Address

D

Q

CS

CLK

register

256K × 16/18

Memory

array

16/18

16/18

DQb

CLK

DQ

Byte Write

registers

DQa

CLK

DQ

Byte Write

registers

Enable

CLK

DQ

register

Enable

CLK

DQ

delay

register

CE

Output
registers

Input

registers

Power
down

DATA [17:0]

2

CE0
CE1

CE2

BW

b

BW

a

OE

ZZ

OE

FT

CLK

CLK

DATA [15:0]

BWE

GWE

Pin arrangement

LBO

A5A4A3A2A1

A0

NC

NC

V

SS

V

DD

NC

NC

A10

A11

A12

A13

A14

A15

31323334353637383940414243444546474849

50

100

99989796959493929190898887868584838281

A6A7CE0

CE1NCNC

BWb

BWa

CE2

V

DD

VSSCLK

GWE

BWEOEADSC

ADSP

ADVA8A9

A16

NC
NC
NC

V

DDQ

V

SSQ

NC

NC
DQb
DQb
V

SSQ

V

DDQ

DQb
DQb

FT

V

DD

NC

V

SS

DQb
DQb

V

DDQ

V

SSQ

DQb
DQb

DQpb/NC

NC
V

SSQ

V

DDQ

NC

NC

NC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

A17
NC
NC
V

DDQ

V

SSQ

NC
DQpa/NC
DQa
DQa
V

SSQ

V

DDQ

DQa
DQa
VSS

ZZ
DQa
DQa
V

DDQ

V

SSQ

DQa
DQa
NC
NC
V

SSQ

V

DDQ

NC
NC
NC

NC
V

DD

TQFP 14 × 20mm

Note: pins 24, 74 are NC for ×16.

AS7C33256PFD16A
AS7C33256PFD18A

®

3/22/01

ALLIANCE SEMICONDUCTOR 2

Functional description

The AS7C33256PFD16A and ASAS7C33256PFD18A are high performance CMOS 4 Mbit synchronous Static Random Access Memory
(SRAM) devices organized as 262,144 words × 16 or 18 bits and incorporate a pipeline for highest frequency on any given technology.

Timing for this device is compatible with existing Pentium® synchronous cache specifications. This architecture is suited for ASIC, DSP
(TMS320C6X), and PowerPC

™

*

-based systems in computing, datacomm, instrumentation, and telecommunications systems.

Fast cycle times of 6/6.7/7.5/10 ns with clock access times (t

CD

) of 3.5/3.8/4.0/5.0 ns enable 166, 150, 133 and 100 MHz bus
frequencies. Three chip enable inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address
strobe (ADSC

), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses.

Read cycles are initiated with ADSP

(regardless of WE and ADSC) using the new external address clocked into the on-chip address register.

When ADSP

is sampled LOW, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation the data
accessed by the current address, registered in the address registers by the positive edge of CLK, are carried to the data-out registers and driven
on the output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted but is sampled on all
subsequent clock edges. Address is incremented internally for the next access of the burst when ADV

is sampled LOW and both address

strobes are HIGH. Burst operation is selectable with the

LBO

input. With

LBO

unconnected or driven HIGH, burst operations use a Pentium

®

count sequence. With

LBO

driven LOW the device uses a linear count sequence suitable for PowerPC™ and many other applications.

Write cycles are performed by disabling the output buffers with OE

and asserting a write command. A global write enable GWE writes all

16/18 bits regardless of the state of individual BW[a:b]

inputs. Alternately, when GWE is HIGH, one or more bytes may be written by

asserting BWE

and the appropriate individual byte BWn signal(s).

BWn

is ignored on the clock edge that samples ADSP LOW, but is sampled on all subsequent clock edges. Output buffers are disabled when

BWn

is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled LOW. Address is incremented

internally to the next burst address if BWn

and ADV are sampled LOW.

Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP follow.

• ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.

•

WE

signals are sampled on the clock edge that samples ADSC LOW (and ADSP HIGH).

• Master chip select CE0 blocks ADSP, but not ADSC.

The ASAS7C33256PFD16A and AS7C33256PFD18A operate from a 3.3V supply. I/Os use a separate power supply that can operate at 2.5V or

3.3V. These devices are available in a 100-pin 14×20 mm TQFP packaging.

*PowerPC™ is a tradenark International Business Machines Corporation.

Capacitance

Write enable truth table (per byte)

Key:
X = Don’t Care, L = Low, H = High, T=True, F=False
* valid read
n = a,b

WE, WEn

= internal write signal

Parameter Symbol Signals Test conditions Max Unit

Input capacitance C

IN

Address and control pins VIN = 0V 5 pF

I/O capacitance C

I/O

I/O pins VIN = V

OUT

= 0V 7 pF

GWE

BWE BWn

WEn

LXXT
HLLT
HHXF*
HLHF*

®

AS7C33256PFD16A
AS7C33256PFD18A

3/22/01

Alliance Semiconductor 3

Signal descriptions

Absolute maximum ratings

Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions may affect reliability.

Signal I/O Properties Description

CLK I CLOCK Clock. All inputs except OE

, FT, ZZ,

LBO

are synchronous to this clock.

A0–A17 I SYNC Address. Sampled when all chip enables are active and ADSC

or ADSP are asserted.

DQ[a,b] I/O SYNC Data. Driven as output when the chip is enabled and OE

is active.

CE0

ISYNC

Master chip enable. Sampled on clock edges when ADSP

or ADSC is active. When

CE0

is inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more

information.

CE1, CE2

ISYNC

Synchronous chip enables. Active HIGH and active LOW, respectively. Sampled on
clock edges when ADSC

is active or when CE0 and ADSP are active.

ADSP

ISYNC

Address strobe (processor). Asserted LOW to load a new address or to enter
standby mode.

ADSC

ISYNC

Address strobe (controller). Asserted LOW to load a new address or to enter
standby mode.

ADV

I SYNC Burst advance. Asserted LOW to continue burst read/write.

GWE

ISYNC

Global write enable. Asserted LOW to write all 16/18 bits. When HIGH, BWE

and

BW[a,b]

control write enable.

BWE

ISYNC

Byte write enable. Asserted LOW with GWE

= HIGH to enable effect of BW[a,b]

inputs.

BW[a,b]

ISYNC

Write enables. Used to control write of individual bytes when GWE = HIGH and
BWE = LOW. If any of BW[a,b] is active with GWE = HIGH and BWE = LOW the
cycle is a write cycle. If all BW[a,b]

are inactive, the cycle is a read cycle.

OE

IASYNC

Asynchronous output enable. I/O pins are driven when OE

is active and the chip is

in read mode.

LBO

I

STATIC default =

HIGH

Count mode. When driven HIGH, count sequence follows Intel XOR convention.
When driven LOW, count sequence follows linear convention. This signal is
internally pulled HIGH.

FT

ISTATIC

Flow-through mode.When LOW, enables single register flow-through mode.
Connect to V

DD

if unused or for pipelined operation.

ZZ I ASYNC

Sleep. Places device in low power mode; data is retained. Connect to GND if
unused.

Parameter Symbol Min Max Unit

Power supply voltage relative to GND V

DD

, V

DDQ

–0.5 +4.6 V

Input voltage relative to GND (input pins) V

IN

–0.5 VDD + 0.5 V

Input voltage relative to GND (I/O pins) V

IN

–0.5 V

DDQ

+ 0.5 V

Power dissipation P

D

–1.8W

DC output current I

OUT

–50mA

Storage temperature (plastic) T

stg

–65 +150 °C

Temperature under bias T

bias

–65 +135 °C

AS7C33256PFD16A
AS7C33256PFD18A

®

3/22/01

ALLIANCE SEMICONDUCTOR 4

Synchronous truth table

Key: X = Don’t Care, L = Low, H = High.

1

See “Write enable truth table” on page 2 for more information.

2

Q in flow through mode

3

For write operation following a READ,

OE

must be HIGH before the input data set up time and held HIGH throughout the input hold time.

Recommended operating conditions

CE0 CE1 CE2 ADSP ADSC ADV

WEn

1

OE Address accessed CLK Operation DQ

H X X X L X X X NA L to H Deselect Hi−Z

L L X L X X X X NA L to H Deselect Hi−Z
L L X H L X X X NA L to H Deselect Hi−Z
L X H L X X X X NA L to H Deselect Hi−Z
L X H H L X X X NA L to H Deselect Hi−Z
L H L L X X X L External L to H Begin read Hi−Z

2

L H L L X X X H External L to H Begin read Hi−Z
L H L H L X F L External L to H Begin read Hi−Z

2

L H L H L X F H External L to H Begin read Hi−Z

X X X H H L F L Next L to H Cont. read Q
X X X H H L F H Next L to H Cont. read Hi−Z
X X X H H H F L Current L to H Suspend read Q
X X X H H H F H Current L to H Suspend read Hi−Z

H X X X H L F L Next L to H Cont. read Q
H X X X H L F H Next L to H Cont. read Hi−Z
H X X X H H F L Current L to H Suspend read Q
H X X X H H F H Current L to H Suspend read Hi−Z

L H L H L X T X External L to H Begin write D

3

X X X H H L T X Next L to H Cont. write D

H X X X H L T X Next L to H Cont. write D

X X X H H H T X Current L to H Suspend write D

H X X X H H T X Current L to H Suspend write D

Parameter Symbol Min Nominal Max Unit

Supply voltage

V

DD

3.135 3.3 3.6
V

V

SS

0.0 0.0 0.0

3.3V I/O supply
voltage

V

DDQ

3.135 3.3 3.6
V

V

SSQ

0.0 0.0 0.0

2.5V I/O supply
voltage

V

DDQ

2.35 2.5 2.9
V

V

SSQ

0.0 0.0 0.0

Input voltages

†

Address and
control pins

V

IH

2.0 – VDD + 0.3
V

V

IL

–0.5

*

* V

IL

min = –2.0V for pulse width less than 0.2 × tRC.

† Input voltage ranges apply to 3.3V I/O operation. For 2.5V I/O operation, contact factory for input specifications.

–0.8

I/O pins

V

IH

2.0 – V

DDQ

+ 0.3

V

V

IL

–0.5

*

–0.8

Ambient operating temperature T

A

0–70°C

®

AS7C33256PFD16A
AS7C33256PFD18A

3/22/01

Alliance Semiconductor 5

TQFP thermal resistance

* This parameter is sampled.

DC electrical characteristics

DC electrical characteristics for 2.5V I/O operation

Description Conditions Symbol Typical Units

Thermal resistance
(junction to ambient)

* Test conditions follow standard test

methods and procedures for measuring

thermal impedance, per EIA/JESD51

θ

JA

40 °C/W

Thermal resistance
(junction to top of case)

*

θ

JC

8 °C/W

Parameter Symbol Test conditions

–166 –150 –133 –100

UnitMin Max Min Max Min Max Min Max

Input leakage
current

*

* LBO

pin has an internal pull-up and input leakage = ±10 µa.

Note: ICC give with no output loading. ICC increases with faster cycle times and greater output loading.

|ILI|VDD = Max, VIN = GND to V

DD

–2–2–2–2µA

Output leakage
current

|I

LO

|

OE

≥ V

IH

, VDD = Max,

V

OUT

= GND to V

DD

–2–2–2–2µA

Operating power
supply current

I

CC

CE0 = VIL, CE1 = VIH, CE2 = VIL,

f = f

Max

, I

OUT

= 0 mA

–475–450–425–325mA

Standby power
supply current

I

SB

Deselected, f = f

Max

, ZZ ≤ V

IL

–130–110–100– 90

mA

I

SB1

Deselected, f = 0, ZZ ≤ 0.2V

all V

IN

≤ 0.2V or ≥ V

DD

– 0.2V

– 30 – 30 – 30 – 30

I

SB2

Deselected, f = f

Max

, ZZ ≥ VDD – 0.2V

All V

IN

≤ VIL or ≥ V

IH

– 30 – 30 – 30 – 30

Output voltage

V

OL

IOL = 8 mA, V

DDQ

= 3.465V – 0.4 – 0.4 – 0.4 – 0.4

V

V

OH

IOH = –4 mA, V

DDQ

= 3.135V 2.4 – 2.4 – 2.4 – 2.4 –

Parameter Symbol Test conditions

–166 –150 –133 –100

UnitMin Max Min Max Min Max Min Max

Output leakage
current

|I

LO

|

OE

≥ V

IH

, VDD = Max,

V

OUT

= GND to V

DD

–11–11–11–11µA

Output voltage

V

OL

IOL = 2 mA, V

DDQ

= 2.65V – 0.7 – 0.7 – 0.7 – 0.7

V

V

OH

IOH = –2 mA, V

DDQ

= 2.35V 1.7 – 1.7 – 1.7 – 1.7 –

AS7C33256PFD16A
AS7C33256PFD18A

®

3/22/01

ALLIANCE SEMICONDUCTOR 6

Timing characteristics over operating range

*“Notes” column refers to “notes” on page 10.

Parameter Symbol

–166 –150 –133 –100

Unit Notes*MinMaxMinMaxMinMaxMinMax

Clock frequency f

Max

–166–150–133–100MHz

Cycle time (pipelined mode) t

CYC

6 –6.6–7.5–10– ns

Cycle time (flow-through mode) t

CYCF

10 – 10 – 12 – 12 – ns

Clock access time (pipelined mode) t

CD

– 3.5 – 3.8 – 4.0 – 5.0 ns

Clock access time (flow-through
mode)

t

CDF

– 9 –10–10–12ns

Output enable LOW to data valid t

OE

– 3.5 – 3.8 – 4.0 – 5.0 ns

Clock HIGH to output Low Z t

LZC

0–0–0–0–ns2,3,4

Data output invalid from clock HIGH t

OH

1.5 – 1.5 – 1.5 – 1.5 – ns 2

Output enable LOW to output Low Z t

LZOE

0–0–0–0–ns2,3,4

Output enable HIGH to output High Z t

HZOE

– 3.5 – 3.8 – 4.0 – 4.5 ns 2,3,4

Clock HIGH to output High Z t

HZC

– 3.5 – 3.8 – 4.0 – 5.0 ns 2,3,4

Output enable HIGH to invalid output t

OHOE

0–0–0–0–ns

Clock HIGH pulse width t

CH

2.4 – 2.5 – 2.5 – 3.5 – ns 5

Clock LOW pulse width t

CL

2.4 – 2.5 – 2.5 – 3.5 – ns 5

Address setup to clock HIGH t

AS

1.5 – 1.5 – 1.5 – 2.0 – ns 6

Data setup to clock HIGH t

DS

1.5 – 1.5 – 1.5 – 2.0 – ns 6

Write setup to clock HIGH t

WS

1.5 – 1.5 – 1.5 – 2.0 – ns 6,7

Chip select setup to clock HIGH t

CSS

1.5 – 1.5 – 1.5 – 2.0 – ns 6,8

Address hold from clock HIGH t

AH

0.5 – 0.5 – 0.5 – 0.5 – ns 6

Data hold from clock HIGH t

DH

0.5 – 0.5 – 0.5 – 0.5 – ns 6

Write hold from clock HIGH t

WH

0.5 – 0.5 – 0.5 – 0.5 – ns 6,7

Chip select hold from clock HIGH t

CSH

0.5 – 0.5 – 0.5 – 0.5 – ns 6,8

ADV setup to clock HIGH t

ADVS

1.5 – 1.5 – 1.5 – 2.0 – ns 6

ADSP

setup to clock HIGH t

ADSPS

1.5 – 1.5 – 1.5 – 2.0 – ns 6

ADSC

setup to clock HIGH t

ADSCS

1.5 – 1.5 – 1.5 – 2.0 – ns 6

ADV

hold from clock HIGH t

ADVH

0.5 – 0.5 – 0.5 – 0.5 – ns 6

ADSP

hold fromclock HIGH t

ADSPH

0.5 – 0.5 – 0.5 – 0.5 – ns 6

ADSC

hold from clock HIGH t

ADSCH

0.5 – 0.5 – 0.5 – 0.5 – ns 6

®

AS7C33256PFD16A
AS7C33256PFD18A

3/22/01

Alliance Semiconductor 7

Timing waveform of read cycle

Note: Ý = XOR when MODE = HIGH/No Connect; Ý = ADD when MODE = LOW.
BW[a:b]

is don’t care.

t

CYC

t

CH

t

CL

t

ADSPS

t

ADSPH

t

AS

t

AH

t

WS

t

ADVS

t

OH

CLK

ADSP

ADSC

Address

GWE, BWE

CE0, CE2

ADV

OE

D

OUT

t

CSS

t

CSH

t

CD

t

WH

t

ADVH

t

HZOE

t

ADSCS

t

ADSCH

LOAD NEW ADDRESS

ADV INSERTS WAIT STATES

Q(A2Ý10) Q(A2Ý11) Q(A3)Q(A2) Q(A2Ý01) Q(A3Ý01) Q(A3Ý10)

Q(A1)

A2A1 A3

CE1

(pipelined mode)

D

OUT

Q(A2Ý10) Q(A2Ý11) Q(A3)Q(A2Ý01) Q(A3Ý01) Q(A3Ý10) Q(A3Ý11)

Q(A1)

(flow-through mode)

t

HZC

t

OE

t

LZOE

Q(A3Ý11)

t

HZC

Key to switching waveform

Undefined/don’t careFalling inputRising input

AS7C33256PFD16A
AS7C33256PFD18A

®

3/22/01

ALLIANCE SEMICONDUCTOR 8

Timing waveform of write cycle

Note: Ý = XOR when MODE = HIGH/No Connect; Ý = ADD when MODE = LOW.

t

CYC

t

CL

t

ADSPS

t

ADSPH

t

ADSCS

t

ADSCH

t

AS

t

AH

t

WS

t

WH

t

CSS

t

ADVS

t

DS

t

DH

CLK

ADSP

ADSC

Address

BWE

CE0, CE2

ADV

OE

Data In

t

CSH

t

ADVH

D(A2Ý01) D(A2Ý10) D(A3)D(A2) D(A2Ý01) D(A3Ý01) D(A3Ý10)

D(A1)

D(A2Ý11)

ADV SUSPENDS BURST

ADSC LOADS NEW ADDRESS

A1

A2 A3

t

CH

CE1

BWa,b

®

AS7C33256PFD16A
AS7C33256PFD18A

3/22/01

Alliance Semiconductor 9

Timing waveform of read/write cycle

Note: Ý = XOR when MODE = HIGH/No Connect; Ý = ADD when MODE = LOW.

t

CH

t

CYC

t

CL

t

ADSPS

t

ADSPH

t

AS

t

AH

t

WS

t

WH

t

ADVS

t

DS

t

DH

t

OH

CLK

ADSP

Address

GWE

CE0, CE2

ADV

OE

D

IN

D

OUT

t

LZC

t

ADVH

t

LZOE

t

OE

t

CD

Q(A1)

Q(A3Ý01)

D(A2)

Q(A3)

Q(A3Ý10) Q(A3Ý11)

A1

A2

A3

CE1

t

HZOE

(pipeline mode)

D

OUT

Q(A1)

Q(A3Ý01) Q(A3Ý10)

(flow-through mode)

t

CDF

Q(A3Ý11)

AS7C33256PFD16A
AS7C33256PFD18A

®

3/22/01

ALLIANCE SEMICONDUCTOR 10

AC test conditions

351

Ω

5 pF*

317

Ω

D

OUT

GND

Figure C: Output load(B)

*including scope

and jig capacitance

Z

0

= 50

Ω

D

OUT

50

Ω

Figure B: Output load (A)

30 pF*

Figure A: Input waveform

10%

90%

GND

90%

10%

+3.0V

• Output load: see Figure B, except for t

LZC

, t

LZOE

, t

HZOE

, t

HZC

, see Figure C.

• Input pulse level: GND to 3V. See Figure A.

• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.

• Input and output timing reference levels: 1.5V.

VL = 1.5V

for 3.3V I/O;
= V

DDQ

/2

for 2.5V I/O

Thevenin equivalent:

+3.3V for 3.3V I/O;
+2.5V for 2.5V I/O

Package Dimensions

100-pin quad flat pack (TQFP)

Dimensions in millimeters

TQFP

Min Max
A1 0.05 0.15
A2 1.35 1.45

b 0.22 0.38
c 0.09 0.20
D 13.90 14.10
E 19.90 20.10

e 0.65 nominal
Hd 15.90 16.10
He 21.90 22.10

L 0.45 0.75

L1 1.00 nominal

α 0° 7°

A1 A2

L1

L

c

He

E

Hd

D

b

e

α

Notes

1) For test conditions, see AC Test Conditions, Figures A, B, C.

2) This parameter measured with output load condition in Figure C.

3) This parameter is sampled, but not 100% tested.

4) t

HZOE

is less than t

LZOE

; and t

HZC

is less than t

LZC

at any given temperature and voltage.

5) tCH measured as HIGH above VIH and tCL measured as LOW below VIL.

6) This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must
meet the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled.

7) Write refers to

GWE, BWE, BW[a:d].

8) Chip select refers to

CE0, CE1, CE2

.

© Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names
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®

AS7C33256PFD16A
AS7C33256PFD18A

3/22/01; v.1.0 Alliance Semiconductor P. 11 of 11

Ordering information

Part numbering guide

1.Alliance Semiconductor SRAM prefix

2.Operating voltage: 33=3.3V

3.Organization: 256=256K

4.Pipeline-Flowthrough (each device works in both modes)

5.Deselect:D=Dual cycle deselect

6.Organization: 16=x16; 18=x18

7.Production version: A=first production version

8.Clock speed (MHz)

9.Package type: TQ=TQFP

10.Operating temperature: C=Commercial (

0° C to 70° C); I=Industrial (

-40

°

C to 85° C)

–166 MHz –150 MHz –133 MHz –100 MHz

AS7C33256PFD16A-166TQC AS7C33256PFD16A-150TQC AS7C33256PFD16A-133TQC AS7C33256PFD16A-100TQC

AS7C33256PFD16A-166TQI AS7C33256PFD16A-150TQI AS7C33256PFD16A-133TQI AS7C33256PFD16A-100TQI

AS7C33256PFD18A-166TQC AS7C33256PFD18A-150TQC AS7C33256PFD18A-133TQC AS7C33256PFD18A-100TQC

AS7C33256PFD18A-166TQI AS7C33256PFD18A-150TQI AS7C33256PFD18A-133TQI AS7C33256PFD18A-100TQI

AS7C 33 256 PF S 16/18 A –XXX TQ C/I

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