Datasheet AS7C33256NTF32A, AS7C33256NTF36A Datasheet (Alliance Semiconductor)

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November 2004

AS7C33256NTF32A
AS7C33256NTF36A

®

3.3V 256K×32/36 Flowthrough Synchronous SRAM with NTD

Features

• Organization: 262,144 words × 32 or 36 bits

™

•NTD

architecture for efficient bus operation

• Fast clock to data access: 7.5/8.5/10 ns

•Fast OE

access time: 3.5/4.0 ns

• Fully synchronous operation

• Flow-through mode

• Asynchronous output enable control

• Available in 100-pin TQFP

• Byte write enables

• Clock enable for operation hold

• Multiple chip enables for easy expansion

Logic Block Diagram

R/W
BWa

BWb
BWc

BWd

LBO

18

D

ZZ

A[17:0]

CE0
CE1
CE2

ADV / LD

Address

register

Burst logic

Control

logic

CLK

CLK

TM

• 3.3 core power supply

• 2.5V or 3.3V I/O operation with separate V

DDQ

• 30 mW typical standby power

• Self-timed write cycles

• Interleaved or linear burst modes

• Snooze mode for standby operation

Q

18

D

Write delay

addr. registers

CLK

Q

18

CLK

Wri te Buf fe r

256K x 32/36

SRAM

Array

DQ[a,b,c,d]

CLK

CEN

32/36

D

Data

Input

Register

CLK

Q

32/36

OE

32/36

OE

32/36

Output

32/36

Buffer

32/36

DQ[a,b,c,d]

Selection Guide

-75 -85 -10 Units

Minimum cycle time 8.5 10 12 ns

Maximum clock access time 7.5 8.5 10 ns

Maximum operating current 300 280 240 mA

Maximum standby current 120 110 100 mA

Maximum CMOS standby current (DC) 30 30 30 mA

11/8/04, v. 1.1 Alliance Semiconductor P. 1 of 18

Copyright © Alliance Semiconductor. All rights reserved.

AS7C33256NTF32A
AS7C33256NTF36A

®

8 Mb Synchronous SRAM products list

Org Part Number Mode Speed

512KX18 AS7C33512PFS18A PL-SCD 166/133 MHz

256KX32

256KX36 AS7C33256PFS36A PL-SCD 166/133 MHz

512KX18 AS7C33512PFD18A PL-DCD 166/133 MHz

256KX32

256KX36 AS7C33

512KX18 AS7C33512FT18A FT 7.5/8.5/10 ns

256KX32

256KX36 AS7C33

512KX18 AS7C33512NTD18A NTD-PL 166/133 MHz

256KX32

256KX36 AS7C33

512KX18 AS7C33512NTF18A NTD-FT 7.5/8.5/10 ns

256KX32

256KX36 AS7C33

AS7C33256PFS32A PL-SCD 166/133 MHz

AS7C33

AS7C33

AS7C33

AS7C33

256

256

256

256

256

256

256

256

1,2

PFD32A PL-DCD 166/133 MHz

PFD36A PL-DCD 166/133 MHz

FT32A FT 7.5/8.5/10 ns

FT36A FT 7.5/8.5/10 ns

NTD32A NTD-PL 166/133 MHz

NTD36A NTD-PL 166/133 MHz

NTF32A NTD-FT 7.5/8.5/10 ns

NTF36A NTD-FT 7.5/8.5/10 ns

1 Core Power Supply: VDD = 3.3V + 0.165V
2 I/O Supply Voltage: VDDQ = 3.3V +

VDDQ = 2.5V +

0.165V for 3.3V I/O

0.125V for 2.5V I/O

PL-SCD : Pipelined Burst Synchronous SRAM - Single Cycle Deselect
PL-DCD : Pipelined Burst Synchronous SRAM - Double Cycle Deselect
FT : Flow-through Burst Synchronous SRAM

1

NTD

-PL : Pipelined Burst Synchronous SRAM with NTD

NTD-FT : Flow-through Burst Synchronous SRAM with NTD

TM

TM

1. NTD: No Turnaround Delay. NTDTM is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property
of their respective owners.

11/8/04, v. 1.1 Alliance Semiconductor P. 2 of 18

Pin arrangement for TQFP (top view)

AACE0

99989796959493929190898887868584838281

DQPc/NC

DQc0
DQc1

V

DDQ

V

SSQ

DQc2
DQc3
DQc4

DQc5

V

SSQ

V

DDQ

DQc6
DQc7

NC

V

DD

NC

V

SS

DQd0
DQd1

V

DDQ

V

SSQ

DQd2
DQd3
DQd4
DQd5

V

SSQ

V

DDQ

DQd6
DQd7

DQPd/NC

100

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

31323334353637383940414243444546474849

CE1

BWd

BWc

DD

BWb

V

BWa

CE2

TQFP 14x20mm

®

VSSCLK

R/W

CENOEADV/LD

NCAA

AS7C33256NTF32A
AS7C33256NTF36A

A

80

DQPb/NC

79

DQb7

78

DQb6

77

V
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

50

DDQ

V

SSQ

DQb5

DQb4

DQb3

DQb2

V

SSQ

V

DDQ

DQb1

DQb0

V

ss

NC

V

DD

ZZ

DQa7

DQa6

V

DDQ

V

SSQ

DQa5

DQa4

DQa3

DQa2

V

SSQ

V

DDQ

DQa1

DQa0

DQP/NC

AAA

LBO

Note: Pins 1, 30, 51 , and 80 are NC for ×32

11/8/04, v. 1.1 Alliance Semiconductor P. 3 of 18

A

A1

A0

NC

NC

SS

V

V

DD

NC

AAAAA

NC

A

A

AS7C33256NTF32A
AS7C33256NTF36A

®

Functional description

The AS7C33256NTF32A/36A family is a high performance CMOS 8 Mbit Synchronous Static Random Access Memory (Flowthrough
SRAM) organized as 262,144 words × 32 or 36 bits and incorporates a LATE Write.

This variation of the 8Mb sychronous SRAM uses the No Turnaround Delay (NTD™) architecture, featuring an enhanced write operation
that improves bandwidth over pipelined burst devices. In a normal flowthrough burst device, the write data, command, and address are all
applied to the device on the same clock edge. If a read command follows this write command, the system must wait for one 'dead' cycle for
valid data to become available. This dead cycle can significantly reduce overall bandwidth for applications requiring random access or read­modify-write operations.

™

devices use the memory bus more efficiently by introducing a write latency which matches one-cycle flow-through read latency.

NTD
Write data is applied one cycle after the write command and address, allowing the read pipeline to clear. With NTD
operations can be used in any order without producing dead bus cycle.

Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full 32/36 bit writes.
Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied to the device one clock
cycle later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for write operations; it can be tied low for
normal operations. Outputs go to a high impedance state when the device is de-selected by any of the three chip enable inputs.

Use the ADV (burst advance) input to perform burst read, write and deselect operations. When ADV is high, external addresses, chip select,

pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any device operations,

R/W
including burst, can be stalled using the CEN=1, the clock enable input.

The AS7C33256NTF32A and AS7C33256NTF36A operate with a 3.3V ± 5% power supply for the device core (VDD). DQ circuits use a
separate power supply (V

) that operates across 3.3V or 2.5V ranges. These devices are available in a 100-pin 14×20 mm TQFP package

DDQ

Capacitance

Parameter Symbol Test conditions Min Max Unit

Input capacitance C

I/O capacitance C

*

Guaranteed not tested

IN

I/O

*

*

Vin = 0V - 5 pF

Vin = V

= 0V - 7 pF

out

™

, write and read

TQFP thermal resistance

Description Conditions Symbol Typ ic al Units

Thermal resistance
(junction to ambient)

Thermal resistance
(junction to top of case)

1 This parameter is sampled

1

Test conditions follow standard test methods
and procedures for measuring thermal

1

impedance, per EIA/JESD51

1–layer θ

4–layer θ

JA

JA

θ

JC

11/8/04, v. 1.1 Alliance Semiconductor P. 4 of 18

40 °C/W

22 °C/W

8 °C/W

AS7C33256NTF32A
AS7C33256NTF36A

®

Signal descriptions

Signal I/O Properties Description

CLK I CLOCK Clock. All inputs except OE

CEN

I SYNC Clock enable. When de-asserted high, the clock input signal is masked.

A, A0, A1 I SYNC Address. Sampled when all chip enables are active and ADV/LD

DQ[a,b,c,d] I/O SYNC Data. Driven as output when the chip is enabled and OE

CE0
CE2

, CE1,

I SYNC

Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD
Are ignored when ADV/LD

Advance or Load. When sampled high, the internal burst address counter will increment in

ADV/LD

I SYNC

the order defined by the LBO input value. (refer to table on page 2) When low, a new
address is loaded.

R/W

BW[a,b,c,d]

OE

I SYNC

I SYNC

I ASYNC Asynchronous output enable. I/O pins are not driven when OE is inactive.

A high during LOAD initiates a READ operation. A low during LOAD initiates a WRITE
operation. Is ignored when ADV/LD

Byte write enables. Used to control write on individual bytes. Sampled along with WRITE
command and BURST WRITE.

Selects Burst mode. When tied to V

LBO

ISTATIC

order. When driven Low, device follows linear Burst order. This signal is internally pulled

High.

ZZ I ASYNC Snooze. Places device in low power mode; data is retained. Connect to GND if unused.

NC - - No connects. Note that pin 84 will be used for future address expansion to 16Mb density.

, LBO, and ZZ are synchronous to this clock.

is asserted.

is active.

is high.

is high.

or left floating, device follows Interleaved Burst

DD

is asserted.

Snooze Mode

SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
SNOOZE MODE is dictated by the length of time the ZZ is in a High state.

The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.

When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time t
become disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successful
complete. Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. similarly,
when exiting SNOOZE MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of
SNOOZE MODE.

is met. After entering SNOOZE MODE, all inputs except ZZ

ZZI

Burst Order

Interleaved Burst Order LBO=1 Linear Burst Order LBO=0

A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0

Starting Address0 00 11 01 1 Starting Address0 00 11 01 1

First increment 0 1 0 0 1 1 1 0 First increment 0 1 1 0 1 1 0 0

Second increment 1 0 1 1 0 0 0 1 Second increment 1 0 1 1 0 0 0 1

Third increment 1 1 1 0 0 1 0 0 Third increment 1 1 0 0 0 1 1 0

11/8/04, v. 1.1 Alliance Semiconductor P. 5 of 18

AS7C33256NTF32A
AS7C33256NTF36A

®

Synchronous truth table

CE0 CE1 CE2 ADV/LD R/W BWn OE CEN

[5,6,7,8,9,11

]

Address

source CLK Operation DQ Notes

H X X L X X X L NA L to H DESELECT Cycle High-Z

X X H L X X X L NA L to H DESELECT Cycle High-Z

X L X L X X X L NA L to H DESELECT Cycle High-Z

X X X H X X X L NA L to H CONTINUE DESELECT Cycle High-Z 1

L H L L H X L L External L to H READ Cycle (Begin Burst) Q

X X X H X X L L Next L to H READ Cycle (Continue Burst) Q 1,10

L H L L H X H L External L to H NOP/DUMMY READ (Begin Burst) High-Z 2

X X X H X X H L Next L to H DUMMY READ (Continue Burst) High-Z 1,2,10

L H L L L L X L External L to H WRITE CYCLE (Begin Burst) D 3

X X X H X L X L Next L to H WRITE CYCLE (Continue Burst) D 1,3,10

L H L L L H X L External L to H NOP/WRITE ABORT (Begin Burst) High-Z 2,3

X X X H X H X L Next L to H WRITE ABORT (Continue Burst) High-Z

X X X X X X X H Current L to H INHIBIT CLOCK - 4

Key: X = Don’t Care, H = HIGH, L = LOW. BWn = H means all byte write signals (BWa, BWb, BWc, and BWd) are HIGH. BWn = L means one or
more byte write signals are LOW.

Notes:

1 CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or WRITE) is chose in the initial
BEGIN BURST cycle. A CONINUE DESELECT cycle can only be entered if a DESELECT CYCLE is executed first.

2 DUMMY READ and WRITE ABORT cycles can be considered NOPs because the device performs no external operation. A WRITE ABORT means a
WRITE command is given, but no operation is performed.

may be wired LOW to minimize the number of control signal to the SRAM. The device will automatically turn off the output drivers during a WRITE

3 OE
cycle. OE

4 If an INHIBIT CLOCK command occurs during a READ operation, the DQ bus will remain active (Low-Z). If it occurs during a WRITE cycle, the bus
will remain in High-Z. No WRITE operations will be performed during the INHIBIT CLOCK cycle.

5
balls);

6 All inputs except

7 Wait states are inserted by setting

8 This device contains circuitry that will ensure that the outputs will be in High-Z during power-up.

9 The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth BURST CYCLE.
10 The address counter is incremented for all CONTINUE BURST cycles.
11 ZZ pin is always Low.

may be used when the bus turn-on and turn-off times do not meet an application’s requirements.

BWa enables WRITEs to byte “a” (DQa pins/balls); BWb enables WRITEs to byte “b” (DQb pins/balls); BWc enables WRITEs to byte “c” (DQc pins/

BWd enables WRITEs to byte “d” (DQd pins/balls).

OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.

CEN HIGH.

1,2,3,

10

11/8/04, v. 1.1 Alliance Semiconductor P. 6 of 18

State Diagram for NTD SRAM

AS7C33256NTF32A
AS7C33256NTF36A

®

Read

Write

Absolute maximum ratings

Burst

Read

Read

Write

Write

W

Read

D

s

e

l

R

e

a

d

R

ead

te

i

r

s

D

W

Burst

Write

l

e

e

t

i

r

1

Burst
Read

Dsel

Burst
Write

Burst

Dsel

Dsel

Burst

Dsel

Burst

Parameter Symbol Min Max Unit

Power supply voltage relative to GND V

Input voltage relative to GND (input pins) V

Input voltage relative to GND (I/O pins) V

Power dissipation P

DC output current I

Storage temperature (plastic) T

Temperature under bias (Junction) T

DD

, V

IN

IN

D

OUT

stg

bias

DDQ

–0.5 +4.6 V

–0.5 VDD + 0.5 V

–0.5 V

+ 0.5 V

DDQ

–1.8W

–50mA

–65 +150

–65 +150

o

C

o

C

1 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions may affect reliability.

Recommended operating conditions at 3.3V I/O

Parameter Symbol Min Nominal Max Unit

Supply voltage for inputs V

Supply voltage for I/O V

Ground supply Vss 0 0 0 V

DD

DDQ

3.135 3.3 3.465 V

3.135 3.3 3.465 V

Recommended operating conditions at 2.5V I/O

Parameter Symbol Min Nominal Max Unit

Supply voltage for inputs V

Supply voltage for I/O V

Ground supply Vss 0 0 0 V

11/8/04, v. 1.1 Alliance Semiconductor P. 7 of 18

DD

DDQ

3.135 3.3 3.465 V

2.375 2.5 2.625 V

®

DC electrical characteristics for 3.3V I/O operation

Parameter Sym Conditions Min Max Unit

Input leakage current

1

|ILI|VDD = Max, 0V < VIN < V

Output leakage current |ILO|OE ≥ VIH, VDD = Max, 0V < V

Input high (logic 1) voltage V

Input low (logic 0) voltage V

Output high voltage V

Output low voltage V

1 LBO, and ZZ pins have an internal pull-up or pull-down, and input leakage = ±10 µA.

IH

IL

OH

OL

Address and control pins 2

I/O pins 2

Address and control pins -0.3

I/O pins -0.5

IOH = –4 mA, V

IOL = 8 mA, V

= 3.135V 2.4 – V

DDQ

= 3.465V – 0.4 V

DDQ

DC electrical characteristics for 2.5V I/O operation

Parameter Sym Conditions Min Max Unit

Input leakage current |ILI|VDD = Max, 0V < VIN < V

Output leakage current |ILO|OE ≥ VIH, VDD = Max, 0V < V

Input high (logic 1) voltage V

Input low (logic 0) voltage V

Output high voltage V

Output low voltage V

*

V

max < VDD +1.5V for pulse width less than 0.2 X t

IH

**

V

min = -1.5 for pulse width less than 0.2 X t

IL

IH

IL

OH

OL

Address and control pins 1.7

I/O pins 1.7

Address and control pins -0.3

I/O pins -0.3

IOH = –4 mA, V

IOL = 8 mA, V

CYC

CYC

DDQ

DDQ

DD

= 2.375V 1.7 – V

= 2.625V – 0.7 V

DD

OUT

OUT

< V

< V

DDQ

DDQ

AS7C33256NTF32A
AS7C33256NTF36A

-2 2 µA

-2 2 µA

*

VDD+0.3

*

V

+0.3

**

**

DDQ

0.8

0.8

-2 2 µA

-2 2 µA

*

VDD+0.3 V

*

V

+0.3 V

**

**

DDQ

0.7 V

0.7 V

V

V

IDD operating conditions and maximum limits

Parameter Sym Conditions -75 -85 -10 Unit

Operating power supply current

Standby power supply current

1 ICC given with no output loading. ICC increases with faster cycle times and greater output loading.

1

I

CC

I

SB

I

SB1

I

SB2

CE0 < VIL, CE1 > VIH, CE2 < VIL, f = f

= 0 mA, ZZ < V

I

OUT

All VIN ≤ 0.2V or >

f = f

Max

VDD – 0.2V,

, ZZ < V

IL

Deselected,

IL

Deselected, f = 0, ZZ < 0.2V,

all V

≤ 0.2V or ≥ VDD – 0.2V

IN

Deselected, f = f

all V

, ZZ ≥ VDD – 0.2V,

Max

≤ VIL or ≥ V

IN

IH

11/8/04, v. 1.1 Alliance Semiconductor P. 8 of 18

Max

,

300

120

30

30

280 240

110 100

30 30

30 30

mA

mA

Timing characteristics over operating range

Parameter Sym

Cycle time t

Clock access time t

Output enable low to data valid t

Clock high to output low Z t

Data Output invalid from clock high t

Output enable low to output low Z t

Output enable high to output high Z t

Clock high to output high Z t

Output enable high to invalid output t

Clock high pulse width t

Clock low pulse width t

Address and Control setup to clock high t

Data setup to clock high t

Write setup to clock high t

Chip select setup to clock high t

Address hold from clock high t

Data hold from clock high t

Write hold from clock high t

Chip select hold from clock high t

Clock enable setup to clock high t

Clock enable hold from clock high t

ADV

setup to clock high t

ADV

hold from clock high t

1 See “AC test conditions” on page 15.

CYC

CD

OE

LZC

OH

LZOE

HZOE

HZC

OHOE

CH

CL

AS

DS

WS

CSS

AH

DH

WH

CSH

CENS

CENH

ADVS

ADVH

AS7C33256NTF32A
AS7C33256NTF36A

®

-75 –85 –10

Min Max Min Max Min Max

8.5-10–12– ns

-7.5–8.5– 10 ns

- 3.5 – 4.0 – 4.0 ns

2.5 - 2.5 – 2.5 – ns 2,3,4

2.5 - 2.5 – 2.5 – ns 2

0.0 - 0 – 0 – ns 2,3,4

- 3.5 – 4.0 – 4.0 ns 2,3,4

- 4.0 – 5.0 – 5.0 ns 2,3,4

0.0-0–0–ns

2.8 - 3.0 – 3.0 – ns 5

2.8 - 3.0 – 3.0 – ns 5

2.0 - 2.0 – 2.0 – ns 6

2.0 - 2.0 – 2.0 – ns 6

2.0 - 2.0 – 2.0 – ns 6, 7

2.0 - 2.0 – 2.0 – ns 6, 8

0.5 - 0.5 – 0.5 – ns 6

0.5 - 0.5 – 0.5 – ns 6

0.5 - 0.5 – 0.5 – ns 6, 7

0.5 - 0.5 – 0.5 – ns 6, 8

2.0 - 2.0 – 2.0 – ns 6

0.5 - 0.5 – 0.5 – ns 6

2.0 - 2.0 – 2.0 – ns 6

0.5 - 0.5 – 0.5 – ns 6

Unit Notes

1

Snooze Mode Electrical Characteristics

Description Conditions Symbol Min Max Units

Current during Snooze Mode ZZ > V

IH

ZZ active to input ignored t

ZZ inactive to input sampled t

ZZ active to SNOOZE current t

ZZ inactive to exit SNOOZE current t

11/8/04, v. 1.1 Alliance Semiconductor P. 9 of 18

I

SB2

PDS

PUS

ZZI

RZZI

30 mA

2cycle

2cycle

2cycle

0

Key to switching waveforms

AS7C33256NTF32A
AS7C33256NTF36A

®

Timing waveform of read cycle

CLK

t

t

CENH

CENS

CEN

t

Address

R/W

t

t

AS

AH

A1 A2

tWSt

WH

t

CSH

CSS

Falling inputRising input

t

t

CH

CL

don’t care

Undefined

t

CYC

A3

CE0,CE2

CE1

ADV/LD

OE

Dout

Command

t

ADVS

t

ADVH

t

LZOE

t

OE

READ

Q(A1)

Q(A1)

t

DSEL

HZOE

READ

Q(A2)

Q(A2)

BURST

READ

Q(A2Ý01)

Q(A2Y‘01)

BURST

READ

Q(A2Ý10)

Q(A2Y‘10)

BURST

Q(A2Ý11)

READ

Q(A2Y‘11)

STALL READ

Q(A3)

Q(A3)

Q(A3Y‘01)

BURST

READ

Q(A3Ý01)

11/8/04, v. 1.1 Alliance Semiconductor P. 10 of 18

Timing waveform of write cycle

CLK

t

t

CENH

CENS

CEN

AS7C33256NTF32A
AS7C33256NTF36A

®

t

t

CH

CL

t

CYC

Address

R/W

BWn

CE0,CE2

CE1

ADV/LD

t

AS

t

AH

A1 A2

t

t

CSS

CSH

t

t

ADVS

ADVH

A3

OE

Din

Dout

Command

Q(n-1)

t

HZOE

WRITE

D(A1)

D(A1)

DSEL

WRITE

D(A2)

D(A2)

BURST

WRITE

D(A2Ý01)

D(A2Y‘01)

BURST

WRITE

D(A2Ý10)

t

DS

D(A2Y‘10) D(A2Y‘11)

BURST

STALL WRITE

WRITE

D(A2Ý11)

t

DH

D(A3)

D(A3)

D(A3Y‘01)

BURST

WRITE

D(A3Ý01)

11/8/04, v. 1.1 Alliance Semiconductor P. 11 of 18

Timing waveform of read/write cycle

AS7C33256NTF32A
AS7C33256NTF36A

®

CLK

CEN

ADDRESS

R/W

BWn

CE0, CE2

CE1

t

CENS

t

t

AS

t

WS

t

WS

CSS

t

CENH

t

AH

t

WH

t

WH

t

CSH

t

t

CH

CL

A2A1

A3 A5A4

t

CYC

A6

A7

t

ADVS

t

ADVH

ADV/LD

OE

t

CD

D/Q

Command

WRITE

D(A1)

tDSt

D(A1)

DH

WRITE

D(A2)

D(A2)

BURST

WRITE

t

LZC

D(A2Ý01)

Q(A3) Q(A4)

READ
Q(A3)

D(A2Ý01)

Note: Ý = XOR when LBO = high/no connect. Ý = ADD when LBO = low.

t

OH

READ
Q(A4)

t

HZOE

t

OE

Q(A4Ý01

t

BURST

READ

Q(A4Ý01)

LZOE

t

HZC

)

WRITE

D(A5)

D(A5) Q(A6)

READ

WRITE

Q(A6)

D(A7)

DSEL

D(A7)

11/8/04, v. 1.1 Alliance Semiconductor P. 12 of 18

NOP, stall and deselect cycles

CLK

CEN

CE1

CE0, CE2

ADV/LD

AS7C33256NTF32A
AS7C33256NTF36A

®

R/W

BWn

Address

D/Q

Command

Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. OE is low.

A1

READ
Q(A1)

Q(A1)

BURST

Q(A1Ý01

Q(A1Ý01)

STALL DSEL

)

Q(A1Ý10)

BURST

Q(A1Ý10

)

BURST

DSEL

A2

WRITE

D(A2)

D(A2)

BURST

D(A2Ý01

NOP

BURST
D(A2

)

Ý10)

A3

WRITE

NOP

D(A3)

11/8/04, v. 1.1 Alliance Semiconductor P. 13 of 18

Timing waveform of snooze mode

CLK

ZZ setup cycle

ZZ

t

ZZI

I

supply

I

SB2

®

t

RZZI

t

PUS

ZZ recovery cycle

AS7C33256NTF32A
AS7C33256NTF36A

All inputs

(except ZZ)

Dout

Deselect or Read Only

Deselect or Read Only

Normal
operation
Cycle

High-Z

11/8/04, v. 1.1 Alliance Semiconductor P. 14 of 18

AS7C33256NTF32A

s

AS7C33256NTF36A

®

AC test conditions

• Output Load: see Figure B,
except for

t

LZC

, t

LZOE

, t

HZOE

, t

see Figure C.

HZC

• Input pulse level: GND to 3V. See Figure A.

• Input rise and fall time (Measured at 0.3V and 2.7V): 2 ns. See Figure A.

• Input and output timing reference levels: 1.5V.

+3.0V

90%

10%

GND

Figure A: Input waveform

90%

10%

Z0=50Ω

D

out

Figure B: Output load (A)

50Ω

30 pF*

VL=1.5V

D

OUT

353Ω/1538

Figure C: Output load(B)

Notes

1 For test conditions, see AC Test Conditions, Figures A, B, C.
2 This parameter measured with output load condition in Figure C
3 This parameter is sampled and not 100% tested.
4t
5
6I
7 Transitions are measured ±500 mV from steady state voltage. Output loading specified with C
8t
9 This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs mu

is less than t

HZOE

t

is a‘no load’ parameter to indicate exactly when SRAM outputs have stopped driving.

HZCN

given with no output loading. ICC increases with faster cycle times and greater output loading.

CC

measured as high above VIH, and tCL measured as low below VIL

CH

meet the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled.

LZOE

; and t

is less than t

HZC

at any given temperature and voltage.

LZC

= 5 pF as in Figure C.

L

Thevenin equivalent:

+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O

319Ω/1667

Ω

5 pF*

GND

Ω

*including scope

and jig capacitance

11/8/04, v. 1.1 Alliance Semiconductor P. 15 of 18

Package Dimensions

AS7C33256NTF32A
AS7C33256NTF36A

®

100-pin quad flat pack (TQFP)

TQFP

Min Max

A1 0.05 0.15

A2 1.35 1.45

b 0.22 0.38

c 0.09 0.20

D 13.80 14.20

E 19.80 20.20

e 0.65 nominal

Hd 15.80 16.20

He 21.80 22.20

L 0.45 0.75

L1 1.00 nominal

α 0° 7°

Dimensions in millimeters

c

L1

L

Hd

D

b

e

α

A1

A2

He

E

11/8/04, v. 1.1 Alliance Semiconductor P. 16 of 18

AS7C33256NTF32A
AS7C33256NTF36A

®

Ordering information

Package Width -75 -85 -10

TQFP x32 AS7C33256NTF32A-75TQC AS7C33256NTF32A-85TQC AS7C33256NTF32A-10TQC

TQFP x32 AS7C33256NTF32A-75TQI AS7C33256NTF32A-85TQI AS7C33256NTF32A-10TQI

TQFP x36 AS7C33256NTF36A-75TQC AS7C33256NTF36A-85TQC AS7C33256NTF36A-10TQC

TQFP x36 AS7C33256NTF36A-75TQI AS7C33256NTF36A-85TQI AS7C33256NTF36A-10TQI

Note: Add suffix ‘N’ to he above part numbers for Lead Free Parts (Ex. AS7C33256NTF32A-85TQCN)

Part numbering guide

AS7C 33 256 NTF 32/36 A –XX TQ C/I X

1

1.Alliance Semiconductor SRAM prefix

2.Operating voltage: 33 = 3.3V

3.Organization:

= No Turn-around Delay, Flowthrough mode

4.NTF

5.Organization: 32 = x32; 36 = x36

6.Production version: A = first production version

7.Clock access time [-75 = 7.5 ns; -85 = 8.5 ns; -10 = 10 ns]

8.Package type: TQ = TQFP.

23

256 = 256

K

45678

910

9.Operating temperature: C = commercial (

10. N = Lead free part

0° C to 70° C); I = industrial (

-40

°

C to 85° C)

11/8/04, v. 1.1 Alliance Semiconductor P. 17 of 18

AS7C33256NTF32A
AS7C33256NTF36A

®

Alliance Semiconductor Corporation

2575, Augustine Drive,

Santa Clara, CA 95054

Tel: 408 - 855 - 4900

Fax: 408 - 855 - 4999

www.alsc.com

© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and
Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the
trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products
at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data
contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to
change or correct this data at any time, without notice. If the product described herein is under development, significant
changes to these specifications are possible. The information in this product data sheet is intended to be general
descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or
warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application
or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of
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infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale
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and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights,
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does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure
may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life­supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against
all claims arising from such use.

®

Copyright © Alliance Semiconductor

All Rights Reserved

Part Number:AS7C33256NTF32A

AS7C33256NTF36A

Document Version: v. 1.1