Datasheet AS7C33128PFS36A-166TQI, AS7C33128PFS36A-166TQC, AS7C33128PFS36A, AS7C33128PFS36A-150TQC, AS7C33128PFS36A-133TQI Datasheet (Alliance Semiconductor Corporation)

January 2001
Preliminary Information

Copyright © Alliance Semiconductor. All rights reserved.

®

7C33128PFS32A
7C33128PFS36A

3.3V 128K X 32/36 pipeline burst synchronous SRAM

2/1/01; V.0.9 Alliance Semiconductor P. 1 of 11

Features

• Organization: 131,072 words × 32 or 36 bits

• Fast clock speeds to 166 MHz in LVTTL/LVCMOS

• Fast clock to data access: 3.5/3.8/4.0/5.0 ns

•Fast OE

access time: 3.5/3.8/4.0/5.0 ns

• Fully synchronous register-to-register operation

• Single register “Flow-through” mode

• Single-cycle deselect

- Dual-cycle deselect also available (AS7C33128PFD32A/
AS7C33128PFD36A)

•Pentium®

*

compatible architecture and timing

• Asynchronous output enable control

• Economical 100-pin TQFP package

• Byte write enables

• Multiple chip enables for easy expansion

• 3.3 core power supply

• 2.5V or 3.3V I/O operation with separate V

DDQ

• 30 mW typical standby power in power down mode

•NTD™

*

pipeline architecture available

(AS7C33128NTD32A/ AS7C33128NTD36A)

Logic block diagram

Q0

Q1

128K × 32/36

Memory

array

Burst logic

CLK

CLR

CE

Address

DQ
CE
CLK

DQ

d

CLK

DQ

Byte write

registers

regist er

DQ

c

CLK

DQ

Byte write

registers

DQ

b

CLK

DQ

Byte write

registers

DQ

a

CLK

DQ

Byte write

regist ers

Enable

CLK

DQ

register

Enable

CLK

DQ

delay

register

CE

Output

registers

Input

registers

Power
down

DATA [35: 0]

4

36/32

171517

17

GWE
BWE

BW

d

ADV
ADSC
ADSP

CLK

CE0
CE1

CE2

BW

c

BW

b

BW

a

OE

A[16:0]

ZZ

LBO

OE

FT

CLK CLK

36/32

DATA [31: 0]

Pin arrangement

DQPc/NC

DQ

c

DQ

c

V

DDQ

V

SSQ

DQ

c

DQ

c

DQ

c

DQ

c

V

SSQ

V

DDQ

DQ

c

DQ

c

FT

V

DD

NC
V

SS

DQ

d

DQ

d

V

DDQ

V

SSQ

DQ

d

DQ

d

DQ

d

DQ

d

V

SSQ

V

DDQ

DQ

d

DQ

d

DQPd/NC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

DQPb/NC
DQ

b

DQ

b

V

DDQ

V

SSQ

DQ

b

DQ

b

DQ

b

DQ

b

V

SSQ

V

DDQ

DQ

b

DQ

b

V

SS

ZZ
DQ

a

DQ

a

V

DDQ

V

SSQ

DQ

a

DQ

a

DQ

a

DQ

a

V

SSQ

V

DDQ

DQ

a

DQ

a

DQPa/NC

LBO

A5A4A3A2A1

A0

NC

NC

V

SS

V

DD

NC

NC

A10

A11

A12

A13

A14

A15

31323334353637383940414243444546474849

50

100

99989796959493929190898887868584838281

A6A7CE0

CE1

BWdBWcBWbBWaCE2

V

DD

VSSCLK

GWE

BWEOEADSC

ADSP

ADVA8A9

NC
VDD

A16

Note: Pins 1,30,51,80 are NC for ×32

TQFP 14 × 20 mm

Selection guide

*

Pentium® is a registered trademark of Intel Corporation. NTD™ is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document

are the property of their respective owners.

AS7C33128PFS32A

–166

AS7C33128PFS32A

–150

AS7C33128PFS32A

–133

AS7C33128PFS32A

–100 Units

Minimum cycle time 6 6.7 7.5 10 ns
Maximum clock frequency 166 150 133 100 MHz
Maximum pipelined clock access time 3.5 3.8 4 5 ns
Maximum operating current 475 450 425 325 mA
Maximum standby current 130 110 100 90 mA
Maximum CMOS standby current (DC) 30 30 30 30 mA

7C33128PFS32A
7C33128PFS36A

®

2/1/01 Alliance Semiconductor P. 2 of 11

Functional description

The AS7C33128PFS32A and AS7C33128PFS36A are high-performance CMOS 4-Mbit synchronous Static Random Access Memory (SRAM)
devices organized as 131,072 words × 32 or 36 bits, and incorporate a two-stage register-register pipeline for highest frequency on any given
technology.

Timing for these devices is compatible with existing Pentium

®

synchronous cache specifications. This architecture is suited for ASIC, DSP

(TMS320C6X), and PowerPC

™

*

-based systems in computing, datacomm, instrumentation, and telecommunications systems.

Fast cycle times of 6/6.7/7.5/10 ns with clock access times (t

CD

) of 3.5/3.8/4.0/5.0 ns enable 166, 150, 133 and 100 MHz bus frequencies.

Three chip enable (CE

) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe

(ADSC

), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses.

Read cycles are initiated with ADSP

(regardless of WE and ADSC) using the new external address clocked into the on-chip address register

when ADSP

is sampled Low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation the data accessed
by the current address, registered in the address registers by the positive edge of CLK, are carried to the data-out registers and driven on the
output pins on the next positive edge of CLK. ADV

is ignored on the clock edge that samples ADSP asserted, but is sampled on all subsequent

clock edges. Address is incremented internally for the next access of the burst when ADV

is sampled Low, and both address strobes are High.

Burst operation is selectable with the

LBO

input. With

LBO

unconnected or driven High, burst operations use a Pentium® count sequence. With

LBO

driven LOW, the device uses a linear count sequence suitable for PowerPC™ and many other applications.

Write cycles are performed by disabling the output buffers with OE

and asserting a write command. A global write enable GWE writes all 32/

36 bits regardless of the state of individual BW[a:d]

inputs. Alternately, when GWE is High, one or more bytes may be written by asserting

BWE

and the appropriate individual byte BWn signal(s).

BWn

is ignored on the clock edge that samples ADSP Low, but is sampled on all subsequent clock edges. Output buffers are disabled when BWn
is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled Low. Address is incremented internally to
the next burst address if BWn

and ADV are sampled Low.

Read or write cycles may also be initiated with ADSC

instead of ADSP. The differences between cycles initiated with ADSC and ADSP follow.

•ADSP

must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.

•WE

signals are sampled on the clock edge that samples ADSC LOW (and ADSP High).

•Master chip enable CE0

blocks ADSP, but not ADSC.

AS7C33128PFS32A and AS7C33128PFS36A family operates from a core 3.3V power supply. I/Os use a separate power supply that can operate
at 2.5V or 3.3V. These devices are available in a 100-pin 14 × 20 mm TQFP package.

*PowerPC™ is a tradenark International Business Machines Corporation.

Capacitance

Write enable truth table (per byte)

Key:

X = Don’t Care, L = Low, H = High, T = True, F = False; *= Valid read; n = a, b, c, d; WE,

WEn

= internal write signal.

Parameter Symbol Signals Test conditions Max Unit

Input capacitance C

IN

Address and control pins VIN = 0V 5 pF

I/O capacitance C

I/O

I/O pins VIN = V

OUT

= 0V 7 pF

GWE

BWE BWn WEn

LXX T
HLL T
HHX F*
HLH F

*

7C33128PFS32A
7C33128PFS36A

®

2/1/01 Alliance Semiconductor P. 3 of 11

Signal descriptions

Absolute maximum ratings

Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions may affect reliability.

Signal

I/
O Properties Description

CLK I CLOCK Clock. All inputs except OE

, FT, ZZ, LBO are synchronous to this clock.

A0–A16 I SYNC Address. Sampled when all chip enables are active and ADSC

or ADSP are asserted.

DQ[a,b,c,d] I/O SYNC Data. Driven as output when the chip is enabled and OE

is active.

CE0 ISYNC

Master chip enable. Sampled on clock edges when ADSP

or ADSC is active. When CE0 is

inactive, ADSP

is blocked. Refer to the Synchronous Truth Table for more information.

CE1, CE2

ISYNC

Synchronous chip enables. Active HIGH and active Low, respectively. Sampled on clock
edges when ADSC

is active or when CE0 and ADSP are active.

ADSP

ISYNC

Address strobe processor. Asserted LOW to load a new bus address or to enter standby
mode.

ADSC

I SYNC Address strobe controller. Asserted LOW to load a new address or to enter standby mode.

ADV

I SYNC Advance. Asserted LOW to continue burst read/write.

GWE

ISYNC

Global write enable. Asserted LOW to write all 32/36 bits. When High, BWE

and BW[a:d]

control write enable.

BWE

I SYNC Byte write enable. Asserted LOW with GWE = HIGH to enable effect of BW[a:d] inputs.

BW[a,b,c,d] ISYNC

Write enables. Used to control write of individual bytes when GWE

= HIGH and BWE =

Low. If any of BW[a:d]

is active with GWE = HIGH and BWE = LOW the cycle is a write

cycle. If all BW[a:d]

are inactive the cycle is a read cycle.

OE

IASYNC

Asynchronous output enable. I/O pins are driven when OE

is active and the chip is in read

mode.

LBO

I

STATIC
default =
HIGH

Count mode. When driven High, count sequence follows Intel XOR convention. When
driven Low, count sequence follows linear convention. This signal is internally pulled High.

18

FT ISTATIC

Flow-through mode.When low, enables single register flow-through mode. Connect to V

DD

if unused or for pipelined operation.

ZZ I ASYNC Sleep. Places device in low power mode; data is retained. Connect to GND if unused.

Parameter Symbol Min Max Unit

Power supply voltage relative to GND V

DD

, V

DDQ

–0.5 +4.6 V

Input voltage relative to GND (input pins) V

IN

–0.5 VDD + 0.5 V

Input voltage relative to GND (I/O pins) V

IN

–0.5 V

DDQ

+ 0.5 V

Power dissipation P

D

–1.8W

DC output current I

OUT

–50mA

Storage temperature (plastic) T

stg

–65 +150

o

C

Temperature under bias T

bias

–65 +135

o

C

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7C33128PFS36A

®

2/1/01 Alliance Semiconductor P. 4 of 11

Synchronous truth table

Key: X = Don’t Care, L = Low, H = High.

1

See “Write enable truth table”on page 2 for more information.

2

Q in flow through mode.

3

For write operation following a READ,

OE

must be HIGH before the input data set up time and held HIGH throughout the input hold time.

Recommended operating conditions

CE0 CE1 CE2 ADSP ADSC ADV

WEn

1

OE

Address accessed CLK Operation DQ

HXXXLXXX NA L to H Deselect Hi−Z

LLXLXXXX NA L to H Deselect Hi−Z
LLXHLXXX NA L to H Deselect Hi−Z
LXHLXXXX NA L to H Deselect Hi−Z
LXHHLXXX NA L to H Deselect Hi−Z
L H L L XXXL External L to H Begin read Hi−Z

2

LHLLXXXH External L to H Begin read Hi−Z
LHLHLXFL External L to H Begin read Hi−Z

2

LHLHLXFH External L to H Begin read Hi−Z

XXXHHLFL Next L to H Cont. read Q
XXXHHLFH Next L to H Cont. read Hi−Z
XXXHHHFL Current L to H Suspend read Q
XXXHHHFH Current L to H Suspend read Hi−Z
HXXXHLFL Next L to H Cont. read Q
HXXXHLFH Next L to H Cont. read Hi−Z
HXXXHHFL Current L to H Suspend read Q
HXXXHHFH Current L to H Suspend read Hi−Z

LHLHLXTX External L to H Begin write D

3

XXXHHLTX Next L to H Cont. write D
HXXXHLTX Next L to H Cont. write D
XXXHHHTX Current L to H Suspend write D
HXXXHHTX Current L to H Suspend write D

Parameter Symbol Min Nominal Max Unit

Supply voltage

V

DD

3.135 3.3 3.6
V

V

SS

0.0 0.0 0.0

3.3V I/O supply
voltage

V

DDQ

3.135 3.3 3.6
V

V

SSQ

0.0 0.0 0.0

2.5V I/O supply
voltage

V

DDQ

2.35 2.5 2.9
V

V

SSQ

0.0 0.0 0.0

Input voltages

†

Address and
control pins

V

IH

2.0 – VDD + 0.3
V

V

IL

–0.5

*

* V

IL

min = –2.0V for pulse width less than 0.2 × tRC.

† Input voltage ranges apply to 3.3V I/O operation. For 2.5V I/O operation, contact factory for input specifications.

–0.8

I/O pins

V

IH

2.0 – V

DDQ

+ 0.3

V

V

IL

–0.5

*

–0.8

Ambient operating temperature T

A

0–70°C

7C33128PFS32A
7C33128PFS36A

®

2/1/01 Alliance Semiconductor P. 5 of 11

TQFP thermal resistance

* This parameter is sampled.

DC electrical characteristics

DC electrical characteristics for 2.5V I/O operation

Description Conditions Symbol Typical Units

Thermal resistance
(junction to ambient)

* Test conditions follow standard test methods and

procedures for measuring thermal impedance, per EIA/

JESD51

θ

JA

46 °C/W

Thermal resistance
(junction to top of case)

*

θ

JC

2.8 °C/W

Parameter Symbol Test conditions

–166 –150 –133 –100

UnitMin Max Min Max Min Max Min Max

Input leakage
current

*

* LBO

pin has an internal pull-up and input leakage = ±10 µa.

Note: ICC given with no output loading. ICC increases with faster cycles times and greater output loading.

|ILI|VDD = Max, VIN = GND to V

DD

–2–2–2–2µA

Output leakage
current

|I

LO

|

OE

≥ V

IH

, VDD = Max,

V

OUT

= GND to V

DD

–2–2–2–2µA

Operating power
supply current

I

CC

CE0 = VIL, CE1 = VIH, CE2 = VIL,

f = f

Max

, I

OUT

= 0 mA

– 475 – 450 – 425 – 325 mA

Standby power
supply current

I

SB

Deselected, f = f

Max

, ZZ ≤ V

IL

–130–110–100– 90

mA

I

SB1

Deselected, f = 0, ZZ ≤ 0.2V

all V

IN

≤ 0.2V or ≥ V

DD

– 0.2V

–30–30–30–30

I

SB2

Deselected, f = f

Max

, ZZ ≥ VDD – 0.2V

All V

IN

≤ VIL or ≥ V

IH

–30–30–30–30

Output voltage

V

OL

IOL = 8 mA, V

DDQ

= 3.465V –0.4–0.4–0.4–0.4

V

V

OH

IOH = –4 mA, V

DDQ

= 3.135V 2.4 – 2.4 – 2.4 – 2.4 –

Parameter Symbol Test conditions

–166 –150 –133 –100

UnitMinMaxMinMaxMinMaxMinMax

Output leakage
current

|I

LO

|

OE

≥ V

IH

, VDD = Max,

V

OUT

= GND to V

DD

–11–11–11–11µA

Output voltage

V

OL

IOL = 2 mA, V

DDQ

= 2.65V –0.7–0.7–0.7–0.7

V

V

OH

IOH = –2 mA, V

DDQ

= 2.35V 1.7 – 1.7 – 1.7 – 1.7 –

7C33128PFS32A
7C33128PFS36A

®

2/1/01 Alliance Semiconductor P. 6 of 11

Timing characteristics over operating range

*See “Notes” on page 10.

Key to switching waveforms

Parameter

Symbo

l

–166 –150 –133 –100

Unit

Notes

*Min Max Min Max Min Max Min Max

Clock frequency f

Max

– 166 – 150 – 133 – 100 MHz

Cycle time (pipelined mode) t

CYC

6 – 6.6 – 7.5 – 10 – ns

Cycle time (flow-through mode) t

CYCF

10–10–12–12– ns

Clock access time (pipelined mode) t

CD

– 3.5 – 3.8 – 4.0 – 5.0 ns

Clock access time (flow-through
mode)

t

CDF

– 9 –10–10–12ns

Output enable LOW to data valid t

OE

– 3.5 – 3.8 – 4.0 – 5.0 ns

Clock HIGH to output Low Z t

LZC

0–0–0–0–ns2,3,4

Data output invalid from clock HIGH t

OH

1.5 – 1.5 – 1.5 – 1.5 – ns 2

Output enable LOW to output Low Z t

LZOE

0–0–0–0–ns2,3,4

Output enable HIGH to output High Z t

HZOE

– 3.5 – 3.8 – 4.0 – 4.5 ns 2,3,4

Clock HIGH to output High Z t

HZC

– 3.5 – 3.8 – 4.0 – 5.0 ns 2,3,4

Output enable HIGH to invalid output t

OHOE

0–0–0–0–ns

Clock HIGH pulse width t

CH

2.4 – 2.5 – 2.5 – 3.5 – ns 5

Clock LOW pulse width t

CL

2.4 – 2.5 – 2.5 – 3.5 – ns 5

Address setup to clock HIGH t

AS

1.5 – 1.5 – 1.5 – 2.0 – ns 6

Data setup to clock HIGH t

DS

1.5 – 1.5 – 1.5 – 2.0 – ns 6

Write setup to clock HIGH t

WS

1.5 – 1.5 – 1.5 – 2.0 – ns 6,7

Chip select setup to clock HIGH t

CSS

1.5 – 1.5 – 1.5 – 2.0 – ns 6,8

Address hold from clock HIGH t

AH

0.5 – 0.5 – 0.5 – 0.5 – ns 6

Data hold from clock HIGH t

DH

0.5 – 0.5 – 0.5 – 0.5 – ns 6

Write hold from clock HIGH t

WH

0.5 – 0.5 – 0.5 – 0.5 – ns 6,7

Chip select hold from clock HIGH t

CSH

0.5 – 0.5 – 0.5 – 0.5 – ns 6,8

ADV setup to clock HIGH t

ADVS

1.5 – 1.5 – 1.5 – 2.0 – ns 6

ADSP

setup to clock HIGH t

ADSPS

1.5 – 1.5 – 1.5 – 2.0 – ns 6

ADSC

setup to clock HIGH t

ADSCS

1.5 – 1.5 – 1.5 – 2.0 – ns 6

ADV

hold from clock HIGH t

ADVH

0.5 – 0.5 – 0.5 – 0.5 – ns 6

ADSP

hold fromclock HIGH t

ADSPH

0.5 – 0.5 – 0.5 – 0.5 – ns 6

ADSC

hold from clock HIGH t

ADSCH

0.5 – 0.5 – 0.5 – 0.5 – ns 6

Undefined/don’t careFalling inputRising input

7C33128PFS32A
7C33128PFS36A

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2/1/01 Alliance Semiconductor P. 7 of 11

Timing waveform of read cycle

Note: Ý = XOR when MODE = HIGH/No Connect; Ý = ADD when MODE = LOW.
BW[a:d]

is don’t care.

t

CYC

t

CH

t

CL

t

ADSPS

t

ADSPH

t

AS

t

AH

t

WS

t

ADVS

t

OH

CLK

ADSP

ADSC

Address

GWE, BWE

CE0, CE2

ADV

OE

D

OUT

t

CSS

t

CSH

t

HZC

t

CD

t

WH

t

ADVH

t

HZOE

t

ADSCS

t

ADSCH

LOAD NEW ADDRESS

ADV INSERTS WAIT STATES

Q(A2Ý10)

Q(A2Ý11) Q(A3)

Q(A2)

Q(A2Ý01) Q(A3Ý01) Q(A3Ý10)

Q(A1)

A2A1 A3

CE1

(pipelined mode)

D

OUT

Q(A2Ý10)

Q(A2Ý11)

Q(A3)

Q(A2Ý01) Q(A3Ý01) Q(A3Ý10)

Q(A3Ý11)

Q(A1)

(flow-through mode)

t

HZC

t

OE

t

LZOE

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2/1/01 Alliance Semiconductor P. 8 of 11

Timing waveform of write cycle

Note: Ý = XOR when MODE = HIGH/No Connect; Ý = ADD when MODE = LOW.

t

CYC

t

CL

t

ADSPS

t

ADSPH

t

ADSCS

t

ADSCH

t

AS

t

AH

t

WS

t

WH

t

CSS

t

ADVS

t

DS

t

DH

CLK

ADSP

ADSC

Address

BWE

CE0, CE2

ADV

OE

Data In

t

CSH

t

ADVH

D(A2Ý01) D(A2Ý10) D(A3)D(A2) D(A2Ý01) D(A3Ý01) D(A3Ý10)

D(A1)

D(A2Ý11)

ADV SUSPENDS BURST

ADSC LOADS NEW ADDRESS

A1

A2 A3

t

CH

CE1

BW[a:d]

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Timing waveform of read/write cycle

Note: Ý = XOR when MODE = HIGH/No Connect; Ý = ADD when MODE = LOW.

t

CH

t

CYC

t

CL

t

ADSPS

t

ADSPH

t

AS

t

AH

t

WS

t

WH

t

ADVS

t

DS

t

DH

t

OH

CLK

ADSP

Address

GWE

CE0, CE2

ADV

OE

D

IN

D

OUT

t

LZC

t

ADVH

t

LZOE

t

OE

t

CD

Q(A1)

Q(A3Ý01)

D(A2)

Q(A3)

Q(A3Ý10) Q(A3Ý11)

A1

A2

A3

CE1

t

HZOE

(pipeline mode)

D

OUT

Q(A1)

Q(A3Ý01) Q(A3Ý10)

(flow-through mode)

t

CDF

Q(A3Ý11)

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2/1/01 Alliance Semiconductor P. 10 of 11

AC test conditions

Notes
1 For test conditions, see AC Test Conditions, Figures A, B, C.
2 This parameter measured with output load condition in Figure C.
3 This parameter is sampled, but not 100% tested.
4t

HZOE

is less than t

LZOE

; and t

HZC

is less than t

LZC

at any given temperature and voltage.
5 tCH measured as HIGH above VIH and tCL measured as LOW below VIL.
6 This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must

meet the setup and hold times for all rising edges of CLK when chip is enabled.

7 Write refers to

GWE, BWE, BW[a:d].

8 Chip select refers to

CE0, CE1, CE2

.

351

Ω

5 pF*

317

Ω

D

OUT

GND

Figure C: Output load(B)

*including scope

and jig capacitance

Z

0

= 50

Ω

D

OUT

50

Ω

Figure B: Output load (A)

30 pF*

Figure A: Input waveform

10%

90%

GND

90%

10%

+3.0V

• Output load: see Figure B, except for t

LZC

, t

LZOE

, t

HZOE

, t

HZC

, see Figure C.

• Input pulse level: GND to 3V. See Figure A.

• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.

• Input and output timing reference levels: 1.5V.

VL = 1.5V

for 3.3V I/O;
= V

DDQ

/2

for 2.5V I/O

Thevenin equivalent:

+3.3V for 3.3V I/O;
+2.5V for 2.5V I/O

Package Dimensions

100-pin quad flat pack (TQFP)

Dimensions in millimeters

TQFP

Min Max

A1 0.05 0.15
A2 1.35 1.45

b 0.22 0.38

c 0.09 0.20

D 13.90 14.10

E 19.90 20.10
e 0.65 nominal

Hd 15.90 16.10

He 21.90 22.10

L 0.45 0.75

L1 1.00 nominal

α 0° 7°

He

E

Hd

D

b

e

A1 A2

L1

L

c

α

®

AS7C33128PFS32A
AS7C33128PFS36A

© Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or register ed tr ademarks of Allia nce . All o th er b ran d an d
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responsibility for any errors that may app ear in th is doc um e nt. T h e d ata c ontain ed h ere in re pr esent s Allian ce ’s best data a nd /or e stim ate s at the ti me of issuan ce. Al lianc e reser ves the righ t to
change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. T h e in form a tion in this
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2/1/01; V.0.9 Alliance Semiconductor P. 11 of 11

Ordering information

Part numbering guide

1.Alliance Semiconductor SRAM prefix

2.Operating voltage: 33=3.3V

3.Organization: 128=128K

4.Pipeline-Flowthrough (each device works in both modes)

5.Deselect: S=Single cycle deselect

6.Organization: 32=x32; 36=x36

7.Production version: A=first production version

8.Clock speed (MHz)

9.Package type: TQ=TQFP

10.Operating temperature: C=Commercial (

0° C to 70° C); I=Industrial (

-40

°

C to 85° C)

–166 MHz –150 MHz –133 MHz –100 MHz

AS7C33128PFS32A-166TQC AS7C33128PFS32A-150TQC AS7C33128PFS32A-133TQC AS7C33128PFS32A-100TQC

AS7C33128PFS32A-166TQI AS7C33128PFS32A-150TQI AS7C33128PFS32A-133TQI AS7C33128PFS32A-100TQI

AS7C33128PFS36A-166TQC AS7C33128PFS36A-150TQC AS7C33128PFS36A-133TQC AS7C33128PFS36A-100TQC

AS7C33128PFS36A-166TQI AS7C33128PFS36A-150TQI AS7C33128PFS36A-133TQI AS7C33128PFS36A-100TQI

AS7C 33 128 PF S 32/36 A –XXX TQ C/I

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