Datasheet AS7C33128PFS18B Datasheet (Alliance Semiconductor)

December 2004

AS7C33128PFS18B

®

3.3V 128K × 18 pipeline burst synchronous SRAM

Features

• Organization: 131,072 words × 18 bits

• Fast clock speeds to 200 MHz

• Fast clock to data access: 3.0/3.5/4.0 ns

•Fast OE

access time: 3.0/3.5/4.0 ns

• Fully synchronous register-to-register operation

• Single-cycle deselect

• Asynchronous output enable control

• Available in 100-pin TQFP package

• Individual byte write and global write

Logic block diagram

CLK

ADV
ADSC
ADSP

A[16:0]

GWE

BW

b

BWE

BW

a

CE0
CE1

CE2

Power

ZZ

down

OE

17

LBO

CLK
CS

Burst logic

CLR

D

CS

CLK

Q

Address
register

DQ

DQb

Byte Write

registers

CLK

DQ

DQa

Byte Write

registers

CLK

DQ

Enable

register

CE
CLK

DQ

Enable

delay

register

CLK

• Multiple chip enables for easy expansion

• 3.3V core power supply

• 2.5V or 3.3V I/O operation with separate V

• Linear or interleaved burst control

• Snooze mode for reduced power-standby

• Common data inputs and data outputs

128K × 18

Memory

18

2

Output

registers

CLK

array

18

Input

registers

CLK

18

DQ [a,b]

17

15

17

OE

DDQ

Selection guide

–200 –166 –133 Units

Minimum cycle time 5 6 7.5 ns
Maximum clock frequency 200 166 133 MHz
Maximum clock access time 3.0 3.5 4 ns
Maximum operating current 375 350 325 mA
Maximum standby current 130 100 90 mA
Maximum CMOS standby current (DC) 30 30 30 mA

12/10/04; v.1.4 Alliance Semiconductor P. 1 of 19

Copyright © Alliance Semiconductor. All rights reserved.

AS7C33128PFS18B

®

2 Mb Synchronous SRAM products list

Org Part Number Mode Speed

128KX18 AS7C33128PFS18B PL-SCD 200/166/133 MHz

64KX32
64KX36 AS7C3364PFS36B PL-SCD 200/166/133 MHz

128KX18 AS7C33128PFD18B PL-DCD 200/166/133 MHz

64KX32
64KX36 AS7C3364PFD36B PL-DCD 200/166/133 MHz

128KX18 AS7C33128FT18B FT 6.5/7.5/8.0/10 ns

64KX32
64KX36 AS7C3364FT36B FT 6.5/7.5/8.0/10 ns

AS7C3364PFS32B PL-SCD 200/166/133 MHz

AS7C3364PFD32B PL-DCD 200/166/133 MHz

AS7C3364FT32B FT 6.5/7.5/8.0/10 ns

1,2

1 Core Power Supply: VDD = 3.3V + 0.165V
2 I/O Supply Voltage: VDDQ = 3.3V +

VDDQ = 2.5V +

0.165V for 3.3V I/O

0.125V for 2.5V I/O

PL-SCD : Pipelined Burst Synchronous SRAM - Single Cycle Deselect
PL-DCD : Pipelined Burst Synchronous SRAM - Double Cycle Deselect
FT : Flow-through Burst Synchronous SRAM

12/10/04; v.1.4 Alliance Semiconductor P. 2 of 19

Pin arrangement

NC
NC
NC

V

DDQ

V

SSQ

NC

NC
DQb0
DQb1

V

SSQ

V

DDQ

DQb2
DQb3

NC

V

DD

NC

V
DQb4
DQb5
V

DDQ

V

SSQ

DQb6
DQb7
DQpb

NC

V

SSQ

V

DDQ

NC
NC
NC

SS

®

DD

SS

V

CE2

V

CLK

GWE

BWEOEADSC

1

AACE0

100

CE1NCNC

99989796959493929190898887868584838281

BWb

BWa

2
3
4
5
6
7
8
9
10
11
12
13
14
15

TQFP 14 × 20mm

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

31323334353637383940414243444546474849

ADSP

ADVAA

AS7C33128PFS18B

A

80

NC

79

NC

78

V

77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

50

DDQ

V

SSQ

NC
DQpa
DQa7
DQa6
V

SSQ

V

DDQ

DQa5
DQa4
VSS
NC
V

DD

ZZ
DQa3
DQa2
V

DDQ

V

SSQ

DQa1
DQa0
NC
NC
V

SSQ

V

DDQ

NC
NC
NC

AAA

LBO

12/10/04; v.1.4 Alliance Semiconductor P. 3 of 19

A

A1

A0

NC

NC

V

SS

V

DD

NC

NC

AAAAA

A

NC

AS7C33128PFS18B

®

Functional description

The AS7C33128PFS18B is a high performance CMOS 2 Mbit synchronous Static Random Access Memory (SRAM) devices
organized as 131,072 words × 18 bits and incorporate a pipeline for highest frequency on any given technology.

Timing for this device is compatible with existing Pentium

1

ASIC, DSP, and PowerPC

™

-based systems in computing, datacom, instrumentation, and telecommunications systems.

®

synchronous cache specifications. This architecture is suited for

Fast cycle times of 5.0/6.0/7.5 ns with clock access times (t

) of 3.0/3.5/4.0 ns enable 200, 166 and 133 MHz bus

CD

frequencies. Three chip enable inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the
controller address strobe (ADSC

), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent

internally generated burst addresses.
Read cycles are initiated with ADSP

address register. When ADSP

(regardless of WE and ADSC) using the new external address clocked into the on-chip

is sampled LOW, the chip enables are sampled active, and the output buffer is enabled with OE.
In a read operation the data accessed by the current address, registered in the address registers by the positive edge of CLK, are
carried to the data-out registers and driven on the output pins on the next positive edge of CLK. ADV
edge that samples ADSP
access of the burst when ADV
input. With

LBO

unconnected or driven HIGH, burst operations use a Pentium® count sequence. With

device uses a linear count sequence suitable for PowerPC
Write cycles are performed by disabling the output buffers with OE

GWE

writes all 18 bits regardless of the state of individual BW[a:b] inputs. Alternately, when GWE is HIGH, one or more

bytes may be written by asserting BWE
BWn

is ignored on the clock edge that samples ADSP LOW, but is sampled on all subsequent clock edges. Output buffers are
disabled when BWn
LOW. Address is incremented internally to the next burst address if BWn

Read or write cycles may also be initiated with ADSC

asserted but is sampled on all subsequent clock edges. Address is incremented internally for the next

is sampled LOW and both address strobes are HIGH. Burst mode is selectable with the

™

and many other applications.

and asserting a write command. A global write enable

and the appropriate individual byte BWn signal(s).

is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled

and ADV are sampled LOW.

instead of ADSP. The differences between cycles initiated with ADSC

is ignored on the clock

LBO

LBO

driven LOW the

and ADSP are as follows:

• ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.

WE

signals are sampled on the clock edge that samples ADSC LOW (and ADSP HIGH).

•

• Master chip select CE0

blocks ADSP, but not ADSC.

The AS7C33128PFS18B operates from a 3.3V supply. I/Os use a separate power supply that can operate at 2.5V or 3.3V.
These devices are available in a 100-pin 14×20 mm TQFP package.

TQFP capacitance

Parameter Symbol Test conditions Min Max Unit

Input capacitance C

I/O capacitance C

* Guaranteed not tested

IN

I/O

*

*

VIN = 0V - 5 pF

V

= 0V - 7 pF

OUT

TQFP thermal resistance

Description Conditions Symbol Typ ic al Units

Thermal resistance
(junction to ambient)

Thermal resistance
(junction to top of case)

1 This parameter is sampled

1. PowerPC™ is a trademark International Business Machines Corporation

12/10/04; v.1.4 Alliance Semiconductor P. 4 of 19

1

1

Test conditions follow standard test methods and

procedures for measuring thermal impedance,

per EIA/JESD51

1–layer θ

4–layer θ

JA

JA

θ

JC

40 °C/W

22 °C/W

8 °C/W

AS7C33128PFS18B

®

Signal descriptions

Signal I/O Properties Description

CLK I CLOCK Clock. All inputs except OE, ZZ,
A,A0,A1 I SYNC Address. Sampled when all chip enables are active and ADSC or ADSP are asserted.
DQ[a,b] I/O SYNC Data. Driven as output when the chip is enabled and OE

CE0

CE1,

CE2

ADSP
ADSC I SYNC Address strobe (controller). Asserted LOW to load a new address or to enter standby mode.
ADV

GWE

BWE

BW[a,b]

OE

LBO

ZZ I ASYNC Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
NC - - No connect

I SYNC

I SYNC

I SYNC Address strobe (processor). Asserted LOW to load a new address or to enter standby mode.

I SYNC Burst advance. Asserted LOW to continue burst read/write.

I SYNC

I SYNC Byte write enable. Asserted LOW with GWE = HIGH to enable effect of BW[a,b] inputs.

I SYNC

I ASYNC

ISTATIC

Master chip enable. Sampled on clock edges when ADSP
inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more information.

Synchronous chip enables. Active HIGH and active LOW, respectively. Sampled on clock
edges when ADSC

Global write enable. Asserted LOW to write all 18 bits. When HIGH, BWE
control write enable.

Write enables. Used to control write of individual bytes when GWE = HIGH and BWE
LOW. If any of BW[a,b]
cycle. If all BW[a,b] are inactive, the cycle is a read cycle.

Asynchronous output enable. I/O pins are driven when OE
mode.

Selects Burst mode. When tied to VDD or left floating, device follows interleaved Burst
order. When driven Low, device follows linear Burst order. This signal is internally pulled

High.

is active or when CE0 and ADSP are active.

is active with GWE = HIGH and BWE = LOW the cycle is a write

LBO

are synchronous to this clock.

is active.

or ADSC is active. When CE0 is

and BW[a,b]

is active and the chip is in read

=

Snooze Mode

SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to I
SNOOZE MODE is dictated by the length of time the ZZ is in a High state.

The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.

When the ZZ pin becomes a logic High, I
is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.
Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting
SNOOZE MODE during t
MODE.

, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE

PUS

is guaranteed after the time t

SB2

is met. After entering SNOOZE MODE, all inputs except ZZ

ZZI

. The duration of

SB2

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®

Write enable truth table (per byte)

Function GWE BWE BWa BWb

Write All Bytes

LXXX

HLLL
Write Byte a H L L H
Write Byte b H L H L

Read

Key: X = don’t care, L = low, H = high, n = a, b;

HHXX

HLHH

BWE, BWn

= internal write signal.

Asynchronous Truth Table

Operation ZZ OE I/O Status

Snooze mode H X High-Z

Read

Write L X Din, High-Z
Deselected L X High-Z

Notes:

1. X means “Don’t Care”

2. ZZ pin is pulled down internally

3. For write cycles that follows read cycles, the output buffers must be disabled with OE

4. Snooze mode means power down state of which stand-by current does not depend on cycle times

5. Deselected means power down state of which stand-by current depends on cycle times

L L Dout
L H High-Z

, otherwise data bus contention will occur.

AS7C33128PFS18B

Burst sequence table

Interleaved burst address (LBO = 1) Linear burst address (LBO = 0)

A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0

1st Address

nd

2

Address

rd

3

Address

th

4

Address

0 00 11 01 1
0 10 01 11 0
1 01 10 00 1
1 11 00 10 0

1st Address

nd

2

Address

rd

3

Address

th

4

Address

0 00 11 01 1
0 11 01 10 0
1 01 10 00 1
1 11 00 11 0

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AS7C33128PFS18B

®

Synchronous truth table

1

CE0

CE1 CE2 ADSP ADSC ADV

[4]

WRITE

[2]

OE Address accessed CLK Operation DQ

HXXXLX X X NA L to H DeselectHi−Z

L L X L X X X X NA L to H Deselect Hi−Z
L L X H L X X X NA L to H Deselect Hi−Z
L X H L X X X X NA L to H Deselect Hi−Z
L X H H L X X X NA L to H Deselect Hi−Z
L H L L X X X L External L to H Begin read Q
L H L L X X X H External L to H Begin read Hi−Z
L H L H L X H L External L to H Begin read Q

L H L H L X H H External L to H Begin read Hi−Z
XXXHHL H L Next L to HContinue readQ
XXXHHL H H Next L to HContinue readHi−Z
XXXHHH H L Current L to HSuspend readQ
XXXHHH H H Current L to HSuspend readHi−Z
HXXXHL H L Next L to HContinue readQ
HXXXHL H H Next L to HContinue readHi−Z
HXXXHH H L Current L to HSuspend readQ
HXXXHH H H Current L to HSuspend readHi−Z

L H L H L X L X External L to H Begin write D
XXXHHL L X Next L to HContinue writeD
HXXXHL L X Next L to HContinue writeD
XXXHHH L X Current L to HSuspend writeD
HXXXHH L X Current L to HSuspend writeD

1 X = don’t care, L = low, H = high
2 For WRITE, L means any one or more byte write enable signals (BWa or BWb) and BWE are LOW or GWE is LOW. WRITE = HIGH for all BWx, BWE,
GWE

HIGH. See "Write enable truth table (per byte)," on page 7 for more information.

3 For write operation following a READ,

4. ZZ pin is always Low.

OE

must be high before the input data set up time and held high throughout the input hold time.

3

12/10/04; v.1.4 Alliance Semiconductor P. 7 of 19

AS7C33128PFS18B

®

Absolute maximum ratings

Parameter Symbol Min Max Unit

Power supply voltage relative to GND V

Input voltage relative to GND (input pins) V

Input voltage relative to GND (I/O pins) V

Power dissipation P

Short circuit output current I

Storage temperature T

Temperature under bias T

Stresses greater than those listed under “Absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only, and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions may affect reliability.

Recommended operating conditions at 3.3V I/O

Parameter Symbol Min Nominal Max Unit

Supply voltage for inputs V

Supply voltage for I/O V

Ground supply Vss 0 0 0 V

DD

DDQ

DD

, V

IN

IN

d

OUT

stg

bias

DDQ

–0.5 +4.6 V

–0.5 VDD + 0.5 V

–0.5 V

DDQ

–1.8W

–20 mA

–65 +150

–65 +135

3.135 3.3 3.465 V

3.135 3.3 3.465 V

+ 0.5 V

o

o

C

C

Recommended operating conditions at 2.5V I/O

Parameter Symbol Min Nominal Max Unit

Supply voltage for inputs V

Supply voltage for I/O V

DD

DDQ

Ground supply Vss 0 0 0 V

3.135 3.3 3.465 V

2.375 2.5 2.625 V

12/10/04; v.1.4 Alliance Semiconductor P. 8 of 19

DC electrical characteristics for 3.3V I/O operation

Parameter Sym Conditions Min Max Unit

†

Input leakage current

Output leakage current |I

|ILI|V

|OE ≥ VIH, VDD = Max, 0V < V

LO

= Max, 0V < VIN < V

DD

Address and control pins 2* VDD+0.3

Input high (logic 1) voltage V

IH

I/O pins 2* V

Address and control pins -0.3** 0.8

Input low (logic 0) voltage V

Output high voltage V

Output low voltage V

IL

OH

OL

I/O pins -0.5** 0.8

IOH = –4 mA, V

IOL = 8 mA, V

DC electrical characteristics for 2.5V I/O operation

Parameter Sym Conditions Min Max Unit

†

Input leakage current

Output leakage current |I

Input high (logic 1) voltage V

Input low (logic 0) voltage V

Output high voltage V

Output low voltage V

† LBO and ZZ pins and have an internal pull-up or pull-down, and input leakage = ±10 µA.

*

V

max < VDD +1.5V for pulse width less than 0.2 X t

IH

**

V

min = -1.5 for pulse width less than 0.2 X t

IL

|ILI|V

|OE ≥ VIH, VDD = Max, 0V < V

LO

= Max, 0V < VIN < V

DD

Address and control pins 1.7* VDD+0.3 V

IH

Address and control pins -0.3** 0.7 V

IL

OH

OL

CYC

CYC

IOH = –4 mA, V

IOL = 8 mA, V

AS7C33128PFS18B

®

DD

< V

OUT

= 3.135V 2.4 – V

DDQ

= 3.465V – 0.4 V

DDQ

OUT

DDQ

DD

< V

I/O pins 1.7* V

I/O pins -0.3** 0.7 V

= 2.375V 1.7 – V

DDQ

= 2.625V – 0.7 V

DDQ

-2 2 µA

-2 2 µA

DDQ

-2 2 µA

DDQ

-2 2 µA

+0.3

V

V

+0.3 V

DDQ

IDD operating conditions and maximum limits

Parameter Sym Conditions -200 -166 -133 Unit

Operating power supply current

Standby power supply current

1

I

I

1 ICC given with no output loading. ICC increases with faster cycle times and greater output loading.

CE0 < VIL, CE1 > VIH, CE2 < VIL, f = f

I

I

SB1

SB2

CC

All VIN ≤ 0.2V or >

SB

all V

Deselected, f = f

= 0 mA, ZZ < V

I

OUT

VDD – 0.2V,

, ZZ < V

f = f

Max

Deselected, f = 0, ZZ < 0.2V,

≤ 0.2V or ≥ VDD – 0.2V

IN

Max

all VIN ≤ VIL or ≥ V

IL

Deselected,

IL

, ZZ ≥ VDD – 0.2V,

IH

12/10/04; v.1.4 Alliance Semiconductor P. 9 of 19

Max

,

375 350 325 mA

130 100 90

30 30 30

30 30 30

mA

Timing characteristics over operating range

Parameter Sym

Clock frequency f
Cycle time t
Clock access time t
Output enable LOW to data valid t
Clock HIGH to output Low Z t
Data output invalid from clock HIGH t
Output enable LOW to output Low Z t
Output enable HIGH to output High Z t
Clock HIGH to output High Z t
Output enable HIGH to invalid output t
Clock HIGH pulse width t
Clock LOW pulse width t
Address setup to clock HIGH t
Data setup to clock HIGH t
Write setup to clock HIGH t
Chip select setup to clock HIGH t
Address hold from clock HIGH t
Data hold from clock HIGH t
Write hold from clock HIGH t
Chip select hold from clock HIGH t
ADV

setup to clock HIGH t

ADSP

setup to clock HIGH t

ADSC

setup to clock HIGH t

ADV

hold from clock HIGH t

ADSP

hold from clock HIGH t

ADSC

hold from clock HIGH t

1 See “Notes” on page 16.

Max

CYC

CD

OE

LZC

OH

LZOE

HZOE

HZC

OHOE

CH

CL

AS

DS

WS

CSS

AH

DH

WH

CSH

ADVS

ADSPS

ADSCS

ADVH

ADSPH

ADSCH

AS7C33128PFS18B

®

–200 –166 –133

Min Max Min Max Min Max

– 200

5–

–3.0

–3.0

0–

1.5 –

0–

–3.0

–3.0

0–

2.0 –

2.3 –

1.4 –

1.4 –

1.4 –

1.4 –

0.4 –

0.4 –

0.4 –

0.4 –

1.4 –

1.4 –

1.4 –

0.4 –

0.4 –

0.4 –

– 166 – 133 MHz
6 – 7.5 – ns
–3.5–4.0ns
–3.5–4.0ns
0 – 0 – ns 2,3,4

1.5–1.5– ns 2
0 – 0 – ns 2,3,4
– 3.5 – 4.0 ns 2,3,4
– 3.5 – 4.0 ns 2,3,4
0–0–ns

2.4–2.5– ns 5

2.4–2.5– ns 5

1.5–1.5– ns 6

1.5–1.5– ns 6

1.5–1.5– ns 6,7

1.5–1.5– ns 6,8

0.5–0.5– ns 6

0.5–0.5– ns 6

0.5–0.5– ns 6,7

0.5–0.5– ns 6,8

1.5–1.5– ns 6

1.5–1.5– ns 6

1.5–1.5– ns 6

0.5–0.5– ns 6

0.5–0.5– ns 6

0.5–0.5– ns 6

Unit Notes

1

Snooze Mode Electrical Characteristics

Description Conditions Symbol Min Max Units

Current during Snooze Mode ZZ > V

IH

ZZ active to input ignored t
ZZ inactive to input sampled t
ZZ active to SNOOZE current t
ZZ inactive to exit SNOOZE current t

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I

SB2

PDS

PUS

ZZI

RZZI

30 mA
2cycle
2cycle

2cycle

0

Key to switching waveforms

AS7C33128PFS18B

®

Timing waveform of read cycle

CLK

t

ADSP

ADSC

Address

, BWE

GWE

CE0, CE2

ADSPS

t

t

CSS

AS

t

ADSPH

t

AH

t

WS

t

CSH

t

ADSCS

A2A1 A3

t

WH

t

ADSCH

t

CYC

t

CH

t

CL

LOAD NEW ADDRESS

don’t careFalling inputRising input

Undefined

CE1

t

ADVS

t

ADVH

ADV

ADV inserts wait states

OE

t

Dout

Read
Q(A1)

t

LZOE

OE

Suspend

Read

Q(A1)

Q(A1)

Read

Q(A2)

t

HZOE

Burst
Read

Q(A

t

2Ý01

OH

Q(A2)

)

Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. BW[a:d] is don’t care.

t

CD

2Ý10

)

Q(A

Q(A2Ý10)

Burst
Read

2Ý11

)

Q(A2Ý01) Q(A3Ý01) Q(A3Ý10)

Burst

Suspend

Read

Q(A

2Ý10

Read

)

Q(A

t

HZC

Q(A2Ý11)

Read

Q(A3) DSEL

Q(A

Burst
Read

3Ý01

Q(A3)

)

Q(A

Burst
Read

3Ý10

Burst

Read

3Ý11

)

Q(A

)

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Timing waveform of write cycle

t

CH

CLK

t

CYC

t

CL

AS7C33128PFS18B

®

ADSP

ADSC

Address

BWE

BW[a:b]

CE0, CE2

CE1

ADV

t

ADSPS

t

t

CSS

AS

A1

t

ADSPH

t

AH

t

CSH

A2

ADV SUSPENDS BURST

t

ADSC LOADS NEW ADDRESS

A3

ADSCS

t

WS

t

ADVS

t

ADSCH

t

WH

t

ADVH

OE

Read

Q(A1)

D(A1)

Sus­pend
Write

D(A1)

Read

Q(A2)

Suspend

Write
D(A2)

Din

Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low.

D(A

ADV
Burst
Write

2Ý01

D(A2Ý01)

Suspend

D(A

)

t

DS

D(A2Ý10) D(A3)D(A2) D(A2Ý01) D(A3Ý01) D(A3Ý10)

Write

2Ý01

D(A2Ý11)

ADV
Burst
Write

)

2Ý10

D(A

ADV
Burst
Write

)

D(A

2Ý11

Write

D(A3)

)

D(A

t

Burst
Write

3Ý01

DH

ADV
Burst
Write

)

3Ý10

D(A

12/10/04; v.1.4 Alliance Semiconductor P. 12 of 19

)

®

Timing waveform of read/write cycle (ADSP Controlled; ADSC High)

t

CYC

t

CL

CLK

t

CH

AS7C33128PFS18B

ADSP

Address

GWE

CE0, CE2

CE1

ADV

OE

t

ADSPS

A1

t

ADSPH

A2

t

AH

t

t

ADVS

WS

A3

t

WH

t

ADVH

t

t

DH

DS

t

AS

Din

Dout

t

CD

t

LZC

Q(A1)

DSEL Suspend

Read

Q(A1)

Read

Q(A1)

Read

Q(A2)

D(A2)

t

HZOE

Suspend

Write

D(A2)

t

LZOE

Read

Q(A3)

Q(A

t

OE

ADV

Burst

Read

3Ý01

Q(A3)

)

Q(A

ADV
Burst
Read

3Ý10

t

OH

Q(A3Ý01)

)

Q(A

Q(A3Ý10) Q(A3Ý11)

ADV
Burst
Read

3Ý11

)

Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low.

12/10/04; v.1.4 Alliance Semiconductor P. 13 of 19

®

Timing waveform of read/write cycle (ADSC controlled, ADSP = HIGH)

t

CYC

CLK

t

CH

t

CL

AS7C33128PFS18B

ADSC

DDRESS

GWE

CE0,CE2

CE1

ADV

OE

Dout

t

ADSCS

t

CSS

A1

t

ADSCH

t

CSH

A2

t

LZOE

A3

t

OE

Q(A1)

A4

Q(A2)

Q(A3)

t

HZOE

Q(A4)

A5

t

WS

A6

t

WH

A7

t

AS

A8

t

AH

t

LZOE

A9

Q(A8)

Q(A9)

t

OH

Din

READ
Q(A1)

READ

Q(A2)

READ
Q(A3)

READ
Q(A4)

D(A5)

t

DS

WRITE

D(A5)

D(A6)

t

DH

WRITE

D(A6)

D(A7)

WRITE

D(A7)

READ

Q(A8)

READ
Q(A9)

12/10/04; v.1.4 Alliance Semiconductor P. 14 of 19

Timing waveform of power down cycle

)

CLK

AS7C33128PFS18B

®

t

CYC

t

CH

t

CL

ADSP

ADSC

ADDRESS

GWE

CE0,CE2

CE1

ADV

OE

t

ADSPS

t

CSS

A1

t

ADSPS

t

CSH

A2

t

WS

t

WH

t

OE

t

READ
Q(A1)

LZOE

S

USPEND

READ
Q(A1)

Q(A1)

t

PDS

ZZ Setup Cycle

t

ZZI

t

HZC

t

HZOE

t

PUS

ZZ Recovery Cycle Normal Operation Mode

t

RZZI

I

SB2

Sleep
State

READ
Q(A2)

D(A2)

D(A2(Ý01))

SUSPEND

WRITE

D(A2)

D(A2

Din

Dout

I

supply

ZZ

12/10/04; v.1.4 Alliance Semiconductor P. 15 of 19

C

ON-

TINUE

WRITE

Ý01

AS7C33128PFS18B

®

AC test conditions

• Output load: see Figure B, except for t

• Input pulse level: GND to 3V. See Figure A.

• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.

• Input and output timing reference levels: 1.5V.

+3.0V

GND

10%

90%

90%

10%

D

Figure A: Input waveform

Notes
1 For test conditions, see AC Test Conditions, Figures A, B, C.
2 This parameter measured with output load condition in Figure C.
3 This parameter is sampled, but not 100% tested.
4t
5 tCH measured as HIGH above VIH and tCL measured as LOW below VIL.
6 This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs

7 Write refers to
8 Chip select refers to

is less than t

HZOE

must meet the setup and hold times for all rising edges of CLK when chip is enabled.

; and t

LZOE

GWE, BWE, BW[a,b].

CE0, CE1, CE2

HZC

is less than t

, t

LZOE

, t

LZC

Z0 = 50

OUT

Figure B: Output load (A)

at any given temperature and voltage.

LZC

HZOE

Ω

, t

, see Figure C.

HZC

50

Ω

30 pF*

VL = 1.5V

for 3.3V I/O;
= V

DDQ

for 2.5V I/O

Thevenin equivalent:

+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O

319

D

OUT

353

/2

Ω / 1538Ω

Ω / 1667Ω

5 pF*
GND

*including scope

and jig capacitance

Figure C: Output load (B)

12/10/04; v.1.4 Alliance Semiconductor P. 16 of 19

Package Dimensions

100-pin quad flat pack (TQFP)

AS7C33128PFS18B

®

Hd

D

L1

L

TQFP

Min Max

A1 0.05 0.15
A2 1.35 1.45

b 0.22 0.38
c 0.09 0.20

D 13.90 14.10

E 19.90 20.10

e 0.65 nominal
Hd 15.85 16.15
He 21.80 22.20

L 0.45 0.75
L1 1.00 nominal

α 0° 7°

Dimensions in millimeters

A1 A2

He

b

α

e

E

12/10/04; v.1.4 Alliance Semiconductor P. 17 of 19

AS7C33128PFS18B

®

Ordering information

Package Width –200 –166 –133

TQFP x18 AS7C33128PFS18B-200TQC AS7C33128PFS18B-166TQC AS7C33128PFS18B-133TQC
TQFP x18 AS7C33128PFS18B-200TQI AS7C33128PFS18B-166TQI AS7C33128PFS18B-133TQI

Note
Add suffix ‘N’ to the above part numbers for lead free parts (Ex AS7C33128PFS18B-166TQCN)

Part numbering guide

AS7C 33 128 PF S 18 B –XXX TQ C/I X

1234567891011

1. Alliance Semiconductor SRAM Prefix

2. Operating voltage: 33 = 3.3V

3. Organization: 128 = 128K

4. Pipeline mode

5. Deselect: S = Single cycle deselect

6. Organization: 18 = x18

7. Production version: B = product revision

8. Clock speed (MHz)

9. Package type: TQ = TQFP

10. Operating temperature: C = Commercial (

11. N=Lead Free Part

0° C to 70° C); I = Industrial (

-40

° C to 85° C)

12/10/04; v.1.4 Alliance Semiconductor P. 18 of 19

AS7C33128PFS18B

®

®

Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel: 408 - 855 - 4900

Copyright © Alliance Semiconductor
All Rights Reserved
Part Number: AS7C33128PFS18B
Document Version: v.1.4

Fax: 408 - 855 - 4999
www.alsc.com

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The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at
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