Datasheet AS7C33128PFD36A-100TQI, AS7C33128PFD36A, AS7C33128PFD32A-166TQI, AS7C33128PFD32A-150TQI, AS7C33128PFD32A-150TQC Datasheet (Alliance Semiconductor Corporation)

March 2001

AS7C33128PFD32A
AS7C33128PFD36A

®

3.3V 128K ×

× 32/36 pipeline burst synchronous SRAM

× ×

Features

• Organization: 131,072 words × 32 or 36 bits

• Fast clock speeds to 166 MHz in LVTTL/LVCMOS

• Fast clock to data access: 3.5/3.8/4.0/5.0 ns

•Fast OE

access time: 3.5/3.8/4.0/5.0 ns

• Fully synchronous register-to-register operation

• Single register “Flow-through” mode

• Dual-cycle deselect

- Single-cycle deselect also available (AS7C33128PFS32A/
AS7C33128PFS36A)

•Pentium®

*

compatible architecture and timing

Logic block diagram

LBO

CLK

ADV
ADSC
ADSP

A[16:0]

GWE

BWE

BW

BW

BW

BW

CE0

CE1

CE2

OE

d

c

b

a

Power

ZZ

down

CLK

CE
CLR

17

DQ
CE
CLK

DQ

CLK

DQ

CLK

DQ

CLK

DQ

CLK

DQ

CE
CLK

DQ

CLK

Address
register

DQ

d

Byte write

registers

DQ

c

Byte write

registers

DQ

b

Byte write

registers

DQ

a

Byte write

regist ers

Enable

register

Enable

delay

register

Q0

Burst logic

Q1

128K × 32/36

Memory

171517

array

36/32

4

OE

Output

regist ers

CLK CLK

DATA [35: 0]

FT

DATA [31: 0]

36/32

registers

Input

• Asynchronous output enable control

• Economical 100-pin TQFP package

• Byte write enables

• Multiple chip enables for easy expansion

• 3.3 core power supply

• 2.5V or 3.3V I/O operation with separate V

DDQ

• 30 mW typical standby power in power down mode

•NTD™

*

pipeline architecture available

(AS7C33128KNTD32A/ AS7C33128NTD36A)

Pin arrangement

DD

V

VSSCLK

GWE

BWEOEADSC

ADSP

ADVA8A9

DQPb/NC

80

DQ

79

b

DQ

78

b

V

77

DDQ

V

76

SSQ

DQ

75

b

DQ

74

b

DQ

73

b

DQ

72

b

V

71

SSQ

V

70

DDQ

DQ

69

b

DQ

68

b

V

67

SS

NC

66

VDD

65

ZZ

64

DQ

63

a

DQ

62

a

V

61

DDQ

V

60

SSQ

DQ

59

a

DQ

58

a

DQ

57

a

DQ

56

a

V

55

SSQ

V

54

DDQ

DQ

53

a

DQ

52

a

DQPa/NC

51

50

SS

DD

A0

V

NC

NC

NC

NC

V

A10

A11

A12

A13

A14

A15

A16

DQPc/NC

DQ
DQ

V

DDQ

V

DQ
DQ
DQ
DQ

V

V

DDQ

DQ
DQ

V

DQ
DQ

V

DDQ

V
DQ
DQ
DQ
DQ
V

V

DDQ

DQ
DQ

DQPd/NC

A6A7CE0

CE1

BWdBWcBWbBWaCE2

99989796959493929190898887868584838281

100

1
2

c

3

c

4
5

SSQ

6

c

7

c

8

c

9

c

10

SSQ

11
12

c

13

c

FT

14
15

DD

NC

16

V

17

SS

18

d

19

d

20
21

SSQ

22

d

23

d

24

d

25

d

26

SSQ

27
28

d

29

d

30

TQFP 14 × 20 mm

31323334353637383940414243444546474849

A5A4A3A2A1

LBO

Note: Pins 1,30,51,80 are NC for ×32

Selection guide

–166 –150 –133 –100 Units

Minimum cycle time 6 6.7 7.5 10 ns
Maximum clock frequency 166 150 133 100 MHz
Maximum pipelined clock access time 3.5 3.8 4 5 ns
Maximum operating current 475 450 425 325 mA
Maximum standby current 130 110 100 90 mA
Maximum CMOS standby current (DC) 30 30 30 30 mA

*

Pentium® is a registered trademark of Intel Corporation. NTD™ is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are

the property of their respective owners.

3/22/01; v.1.0 Alliance Semiconductor P. 1 of 11

Copyright © Alliance Semiconductor. All rights reserved.

AS7C33128PFD32A
AS7C33128PFD36A

®

Functional description

The AS7C33128PFD32A and AS7C33128PFD36A are high-performance CMOS 4-Mbit synchronous Static Random Access Memory (SRAM)
devices organized as 131,072 words × 32 or 36 bits, and incorporate a two-stage register-register pipeline for highest frequency on any
given technology.

®

Timing for these devices is compatible with existing Pentium
(TMS320C6X), and PowerPC

Fast cycle times of 6/6.7/7.5/10 ns with clock access times (t
frequencies. Three chip enable (CE
address strobe (ADSC
addresses.

Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register
when ADSP
accessed by the current address, registered in the address registers by the positive edge of CLK, are carried to the data-out registers and driven
on the output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on all
subsequent clock edges. Address is incremented internally for the next access of the burst when ADV
strobes are High. Burst operation is selectable with the
count sequence. With

Write cycles are performed by disabling the output buffers with OE
32/36 bits regardless of the state of individual BW[a:d]
asserting BWE

BWn
BWn
internally to the next burst address if BWn

Read or write cycles may also be initiated with ADSC

•ADSP

•WE

•Master chip enable CE0

AS7C33128PFD32A and AS7C33128PFD36A family operates from a core 3.3V power supply. I/Os use a separate power supply that can
operate at 2.5V or 3.3V. These devices are available in a 100-pin 14 × 20 mm TQFP package.

is sampled Low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation the data

is ignored on the clock edge that samples ADSP Low, but is sampled on all subsequent clock edges. Output buffers are disabled when
is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled Low. Address is incremented

must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.

signals are sampled on the clock edge that samples ADSC LOW (and ADSP High).

), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst

and the appropriate individual byte BWn signal(s).

*

™

-based systems in computing, datacomm, instrumentation, and telecommunications systems.

) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller

LBO

driven LOW, the device uses a linear count sequence suitable for PowerPC™ and many other applications.

and ADV are sampled Low.

instead of ADSP. The differences between cycles initiated with ADSC and ADSP follow.

blocks ADSP, but not ADSC.

synchronous cache specifications. This architecture is suited for ASIC, DSP

) of 3.5/3.8/4.0/5.0 ns enable 166, 150, 133 and 100 MHz bus

CD

is sampled Low, and both address

LBO

input. With

inputs. Alternately, when GWE is High, one or more bytes may be written by

LBO

unconnected or driven High, burst operations use a Pentium

and asserting a write command. A global write enable GWE writes all

®

*PowerPC™ is a tradenark International Business Machines Corporation.

Capacitance

Parameter Symbol Signals Test conditions Max Unit

Input capacitance C
I/O capacitance C

IN

I/O

Address and control pins VIN = 0V 5 pF

I/O pins VIN = V

= 0V 7 pF

OUT

Write enable truth table (per byte)

GWE

LXX T
HLL T
HHX F*
HLH F

Key:

X = Don’t Care, L = Low, H = High, T = True, F = False; *= Valid read; n = a, b, c, d; WE,

3/22/01; v.1.0 Alliance Semiconductor P. 2 of 11

BWE BWn WEn

*

= internal write signal.

WEn

AS7C33128PFD32A
AS7C33128PFD36A

®

Signal descriptions

Signal I/O Properties Description

CLK I CLOCK Clock. All inputs except OE
A0–A16 I SYNC Address. Sampled when all chip enables are active and ADSC
DQ[a,b,c,d] I/O SYNC Data. Driven as output when the chip is enabled and OE

CE0 ISYNC

CE1, CE2

ADSP

ADSC

ISYNC

ISYNC

I SYNC Address strobe controller. Asserted LOW to load a new address or to enter standby mode.

Master chip enable. Sampled on clock edges when ADSP
inactive, ADSP

is blocked. Refer to the Synchronous Truth Table for more information.

Synchronous chip enables. Active HIGH and active Low, respectively. Sampled on clock
edges when ADSC

is active or when CE0 and ADSP are active.

Address strobe processor. Asserted LOW to load a new bus address or to enter standby
mode.

ADV I SYNC Advance. Asserted LOW to continue burst read/write.

GWE

BWE

ISYNC

I SYNC Byte write enable. Asserted LOW with GWE = HIGH to enable effect of BW[a:d] inputs.

Global write enable. Asserted LOW to write all 32/36 bits. When High, BWE
control write enable.

Write enables. Used to control write of individual bytes when GWE

BW[a,b,c,d] ISYNC

Low. If any of BW[a:d]
cycle. If all BW[a:d]

OE

IASYNC

STATIC

I

LBO

default =
HIGH

FT ISTATIC

Asynchronous output enable. I/O pins are driven when OE
mode.

Count mode. When driven High, count sequence follows Intel XOR convention. When
driven Low, count sequence follows linear convention. This signal is internally pulled High.

Flow-through mode.When low, enables single register flow-through mode. Connect to V
if unused or for pipelined operation.

ZZ I ASYNC Sleep. Places device in low power mode; data is retained. Connect to GND if unused.

, FT, ZZ, LBO are synchronous to this clock.

or ADSP are asserted.
is active.
or ADSC is active. When CE0 is

and BW[a:d]

= HIGH and BWE =

is active with GWE = HIGH and BWE = LOW the cycle is a write

are inactive the cycle is a read cycle.

is active and the chip is in read

18

DD

Absolute maximum ratings

Parameter Symbol Min Max Unit

Power supply voltage relative to GND V
Input voltage relative to GND (input pins) V
Input voltage relative to GND (I/O pins) V
Power dissipation P
DC output current I
Storage temperature (plastic) T
Temperature under bias T

Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute max­imum rating conditions may affect reliability.

3/22/01; v.1.0 Alliance Semiconductor P. 3 of 11

DD

IN

IN

D

OUT

stg

bias

, V

DDQ

–0.5 +4.6 V
–0.5 VDD + 0.5 V
–0.5 V

+ 0.5 V

DDQ

–1.8W
–50mA
–65 +150
–65 +135

o

C

o

C

AS7C33128PFD32A
AS7C33128PFD36A

®

Synchronous truth table

CE0 CE1 CE2 ADSP ADSC ADV

H X X X L X X X NA L to H Deselect Hi−Z

L L X L X X X X NA L to H Deselect Hi−Z
L L X H L X X X NA L to H Deselect Hi−Z
L X H L X X X X NA L to H Deselect Hi−Z
L X H H L X X X NA L to H Deselect Hi−Z
L H L L X X X L External L to H Begin read Hi−Z
L H L L X X X H External L to H Begin read Hi−Z
LHLHLXFL External L to HBegin readHi−Z
LHLHLXFH External L to HBegin readHi−Z

X X X H H L F L Next L to H Cont. read Q

X X X H H L F H Next L to H Cont. read Hi−Z

X X X H H H F L Current L to H Suspend read Q

X X X H H H F H Current L to H Suspend read Hi−Z

H X X X H L F L Next L to H Cont. read Q

H X X X H L F H Next L to H Cont. read Hi−Z

H X X X H H F L Current L to H Suspend read Q

H X X X H H F H Current L to H Suspend read Hi−Z

LHLHLXTX External L to HBegin writeD
X X X H H L T X Next L to H Cont. write D
H X X X H L T X Next L to H Cont. write D
X X X H H H T X Current L to H Suspend write D
H X X X H H T X Current L to H Suspend write D

Key: X = Don’t Care, L = Low, H = High.

1

See “Write enable truth table”on page 2 for more information.

2

Q in flow through mode.

3

For write operation following a READ,

must be HIGH before the input data set up time and held HIGH throughout the input hold time.

OE

Recommended operating conditions

Parameter Symbol Min Nominal Max Unit

Supply voltage

3.3V I/O supply
voltage

2.5V I/O supply
voltage

Address and

Input voltages

†

Ambient operating temperature T

min = –2.0V for pulse width less than 0.2 × tRC.

* V

IL

† Input voltage ranges apply to 3.3V I/O operation. For 2.5V I/O operation, contact factory for input specifications.

control pins

I/O pins

WEn

1

OE Address accessed CLK Operation DQ

V

V

V

V

V

V

DDQ

DDQ

V

V

V

V

DD

SS

SSQ

SSQ

IH

IL

IH

IL

A

3.135 3.3 3.6

0.0 0.0 0.0

3.135 3.3 3.6

0.0 0.0 0.0

2.35 2.5 2.9

0.0 0.0 0.0

2.0 – VDD + 0.3

*

–0.5

2.0 – V

*

–0.5

–0.8

+ 0.3

DDQ

–0.8

0–70°C

2

2

3

V

V

V

V

V

3/22/01; v.1.0 Alliance Semiconductor P. 4 of 11

®

TQFP thermal resistance

Description Conditions Symbol Typical Units

Thermal resistance
(junction to ambient)

Thermal resistance
(junction to top of case)

* This parameter is sampled.

* Test conditions follow standard test

methods and procedures for measuring

*

thermal impedance, per EIA/JESD51

θ

JA

θ

JC

DC electrical characteristics

–166 –150 –133 –100

Parameter Symbol Test conditions

Input leakage

*

current
Output leakage

current
Operating power

supply current

Standby power
supply current

Output voltage

* LBO

pin has an internal pull-up and input leakage = ±10 µa.

Note: ICC given with no output loading. ICC increases with faster cycles times and greater output loading.

|ILI|VDD = Max, VIN = GND to V

≥ V

|I

|

LO

I

CC

I

SB

I

SB1

I

SB2

V

OL

V

OH

OE

V

CE0 = VIL, CE1 = VIH, CE2 = VIL,

f = f

Deselected, f = f

Deselected, f = 0, ZZ ≤ 0.2V

all V

IN

Deselected, f = f

All V

IOL = 8 mA, V

IOH = –4 mA, V

, VDD = Max,

IH

= GND to V

OUT

, I

OUT

= 0 mA

Max

Max

≤ 0.2V or ≥ V

, ZZ ≥ VDD – 0.2V

Max

≤ VIL or ≥ V

IN

DDQ

DDQ

DD

, ZZ ≤ V

– 0.2V

DD

IH

= 3.465V –0.4–0.4–0.4–0.4

= 3.135V 2.4 – 2.4 – 2.4 – 2.4 –

–2–2–2–2µA

DD

–2–2–2–2µA

– 475 – 450 – 425 – 325 mA

–130–110–100– 90

IL

–30–30–30–30

–30–30–30–30

AS7C33128PFD32A
AS7C33128PFD36A

40 °C/W

8 °C/W

UnitMin Max Min Max Min Max Min Max

mA

V

DC electrical characteristics for 2.5V I/O operation

–166 –150 –133 –100

Parameter Symbol Test conditions

≥ V

Output leakage
current

Output voltage

3/22/01; v.1.0 Alliance Semiconductor P. 5 of 11

|

|I

LO

V

OL

V

OH

OE

V

IOL = 2 mA, V

IOH = –2 mA, V

, VDD = Max,

IH

= GND to V

OUT

DD

–11–11–11–11µA

= 2.65V –0.7–0.7–0.7–0.7

DDQ

= 2.35V 1.7 – 1.7 – 1.7 – 1.7 –

DDQ

UnitMin Max Min Max Min Max Min Max

V

Timing characteristics over operating range

Parameter Symbol

Clock frequency f
Cycle time (pipelined mode) t
Cycle time (flow-through mode) t
Clock access time (pipelined mode) t
Clock access time (flow-through

mode)
Output enable LOW to data valid t
Clock HIGH to output Low Z t
Data output invalid from clock HIGH t
Output enable LOW to output Low Z t
Output enable HIGH to output High Z t
Clock HIGH to output High Z t
Output enable HIGH to invalid output t
Clock HIGH pulse width t
Clock LOW pulse width t
Address setup to clock HIGH t
Data setup to clock HIGH t
Write setup to clock HIGH t
Chip select setup to clock HIGH t
Address hold from clock HIGH t
Data hold from clock HIGH t
Write hold from clock HIGH t
Chip select hold from clock HIGH t
ADV setup to clock HIGH t
ADSP

setup to clock HIGH t

setup to clock HIGH t

ADSC
ADV

hold from clock HIGH t

ADSP

hold fromclock HIGH t

hold from clock HIGH t

ADSC

*See “Notes” on page 10.

Max

CYC

CYCF

CD

t

CDF

OE

LZC

OH

LZOE

HZOE

HZC

OHOE

CH

CL

AS

DS

WS

CSS

AH

DH

WH

CSH

ADVS

ADSPS

ADSCS

ADVH

ADSPH

ADSCH

AS7C33128PFD32A
AS7C33128PFD36A

®

–166 –150 –133 –100

Unit Notes*MinMaxMinMaxMinMaxMinMax

– 166 – 150 – 133 – 100 MHz
6 – 6.6 – 7.5 – 10 – ns

10–10–12–12– ns

– 3.5 – 3.8 – 4.0 – 5.0 ns

– 9 –10–10–12ns

– 3.5 – 3.8 – 4.0 – 5.0 ns
0–0–0–0–ns2,3,4

1.5 – 1.5 – 1.5 – 1.5 – ns 2
0–0–0–0–ns2,3,4
– 3.5 – 3.8 – 4.0 – 4.5 ns 2,3,4
– 3.5 – 3.8 – 4.0 – 5.0 ns 2,3,4
0–0–0–0–ns

2.4 – 2.5 – 2.5 – 3.5 – ns 5

2.4 – 2.5 – 2.5 – 3.5 – ns 5

1.5 – 1.5 – 1.5 – 2.0 – ns 6

1.5 – 1.5 – 1.5 – 2.0 – ns 6

1.5 – 1.5 – 1.5 – 2.0 – ns 6,7

1.5 – 1.5 – 1.5 – 2.0 – ns 6,8

0.5 – 0.5 – 0.5 – 0.5 – ns 6

0.5 – 0.5 – 0.5 – 0.5 – ns 6

0.5 – 0.5 – 0.5 – 0.5 – ns 6,7

0.5 – 0.5 – 0.5 – 0.5 – ns 6,8

1.5 – 1.5 – 1.5 – 2.0 – ns 6

1.5 – 1.5 – 1.5 – 2.0 – ns 6

1.5 – 1.5 – 1.5 – 2.0 – ns 6

0.5 – 0.5 – 0.5 – 0.5 – ns 6

0.5 – 0.5 – 0.5 – 0.5 – ns 6

0.5 – 0.5 – 0.5 – 0.5 – ns 6

3/22/01; v.1.0 Alliance Semiconductor P. 6 of 11

Timing waveform of read cycle

CLK

t

ADSPS

t

ADSPH

ADSP

ADSC

t

AS

t

AH

Address

GWE, BWE

CE0, CE2

t

CSS

t

CSH

A2A1 A3

t

WS

t

WH

t

ADSCS

t

ADSCH

AS7C33128PFD32A
AS7C33128PFD36A

®

t

t

CH

t

CYC
CL

LOAD NEW ADDRESS

CE1

t

ADVS

t

ADVH

ADV

OE

t

CD

ADV INSERTS WAIT STATES

Q(A2Ý10) Q(A2Ý11) Q(A3)Q(A2Ý01) Q(A3Ý01) Q(A3Ý10) Q(A3Ý11)

D

OUT

(pipelined mode)

t

LZOE

D

OUT

t

HZOE

t

OH

Q(A1)

t

OE

Q(A1)

(flow-through mode)

Note: Ý = XOR when MODE = HIGH/No Connect; Ý = ADD when MODE = LOW.
BW[a:d]

is don’t care.

Key to switching waveform

t

HZC

Q(A2Ý10) Q(A2Ý11) Q(A3)Q(A2) Q(A2Ý01)

Q(A3Ý01)

Q(A3Ý10)

t

Q(A3Ý11)

HZC

Undefined/don’t careFalling inputRising input

3/22/01; v.1.0 Alliance Semiconductor P. 7 of 11

Timing waveform of write cycle

t

CH

CLK

t

ADSPS

t

ADSPH

ADSP

ADSC

t
t

CYC

CL

AS7C33128PFD32A
AS7C33128PFD36A

®

t

ADSCS

t

ADSCH

Address

BWE

BW[a:d]

CE0, CE2

CE1

ADV

A1

t

AS

t

AH

ADSC LOADS NEW ADDRESS

A2 A3

t

WS

t

WH

t

CSS

t

CSH

ADV SUSPENDS BURST

t

ADVS

t

ADVH

OE

t

DS

t

DH

Data In

Note: Ý = XOR when MODE = HIGH/No Connect; Ý = ADD when MODE = LOW.

D(A1)

D(A2Ý01) D(A2Ý10) D(A3)D(A2) D(A2Ý01) D(A3Ý01) D(A3Ý10)

D(A2Ý11)

3/22/01; v.1.0 Alliance Semiconductor P. 8 of 11

Timing waveform of read/write cycle

CLK

t

ADSPS

t

ADSPH

ADSP

Address

GWE

A1

AS7C33128PFD32A
AS7C33128PFD36A

®

t

CYC

t

CH

t

A2

t

CL

AS

t

AH

A3

t

WS

t

WH

CE0, CE2

CE1

ADV

OE

D

IN

D

OUT

(pipeline mode)

D

OUT

(flow-through mode)

t

CDF

t

ADVS

t

ADVH

t

DS

t

DH

D(A2)

t

LZC

t

CD

Q(A1) Q(A3Ý01)

Q(A1) Q(A3Ý01) Q(A3Ý10)

t

HZOE

t

LZOE

t

OE

Q(A3) Q(A3Ý10) Q(A3Ý11)

t

OH

Q(A3Ý11)

Note: Ý = XOR when MODE = HIGH/No Connect; Ý = ADD when MODE = LOW.

3/22/01; v.1.0 Alliance Semiconductor P. 9 of 11

AS7C33128PFD32A
AS7C33128PFD36A

®

AC test conditions

• Output load: see Figure B, except for t

• Input pulse level: GND to 3V. See Figure A.

• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.

• Input and output timing reference levels: 1.5V.

+3.0V

GND

90%

10%

90%

10%

Figure A: Input waveform

Notes
1 For test conditions, see AC Test Conditions, Figures A, B, C.
2 This parameter measured with output load condition in Figure C.
3 This parameter is sampled, but not 100% tested.
4t
5 tCH measured as HIGH above VIH and tCL measured as LOW below VIL.
6 This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must

7 Write refers to
8 Chip select refers to

is less than t

HZOE

meet the setup and hold times for all rising edges of CLK when chip is enabled.

LZOE

; and t

is less than t

HZC

GWE, BWE, BW[a:d].

CE0, CE1, CE2

.

, t

, t

= 50

0

HZOE

, t

Ω

LZC

LZOE

Z

D

OUT

Figure B: Output load (A)

at any given temperature and voltage.

LZC

, see Figure C.

HZC

Ω

50

30 pF*

VL = 1.5V

for 3.3V I/O;
= V

DDQ

for 2.5V I/O

/2

Thevenin equivalent:

+3.3V for 3.3V I/O;
+2.5V for 2.5V I/O

D

OUT

317

5 pF*

Ω

351

GND

Figure C: Output load(B)

Ω

*including scope

and jig capacitance

Package Dimensions

100-pin quad flat pack (TQFP)

TQFP

Min Max
A1 0.05 0.15
A2 1.35 1.45

b 0.22 0.38
c 0.09 0.20

D 13.90 14.10

E 19.90 20.10

e 0.65 nominal
Hd 15.90 16.10
He 21.90 22.10

L 0.45 0.75

L1 1.00 nominal

α 0° 7°

Dimensions in millimeters

c

L1

L

A1 A2

He

Hd

D

b

e

E

α

3/22/01; v.1.0 Alliance Semiconductor P. 10 of 11

AS7C33128PFD32A
AS7C33128PFD36A

®

Ordering information

–166 MHz –150 MHz –133 MHz –100 MHz

AS7C33128PFD32A-166TQC AS7C33128PFD32A-150TQC AS7C33128PFD32A-133TQC AS7C33128PFD32A-100TQC

AS7C33128PFD32A-166TQI AS7C33128PFD32A-150TQI AS7C33128PFD32A-133TQI AS7C33128PFD32A-100TQI

AS7C33128PFD36A-166TQC AS7C33128PFD36A-150TQC AS7C33128PFD36A-133TQC AS7C33128PFD36A-100TQC

AS7C33128PFD36A-166TQI AS7C33128PFD36A-150TQI AS7C33128PFD36A-133TQI AS7C33128PFD36A-100TQI

Part numbering guide

AS7C 33 128 PF D 32/36 A –XXX TQ C/I

1

23

1.Alliance Semiconductor SRAM prefix

2.Operating voltage: 33=3.3V

3.Organization: 128=128K

4.Pipeline-Flowthrough (each device works in both modes)

5.Deselect: D=Dual cycle deselect

6.Organization: 32=x32; 36=x36

7.Production version: A=first production version

8.Clock speed (MHz)

9.Package type: TQ=TQFP

10.Operating temperature: C=Commercial (

4

5

0° C to 70° C); I=Industrial (

6789

°

C to 85° C)

-40

10

3/22/01; v.1.0 Alliance Semiconductor P. 11 of 11

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