Datasheet AS7C33128FT18B Datasheet (Alliance Semiconductor)

December 2004

3.3V 128K × 18 Flow Through Synchronous SRAM

Features

• Organization: 131,072 words × 18 bits

• Fast clock to data access: 6.5/7.5/8.0/10.0 ns

•Fast OE

• Fully synchronous flow through operation

• Asynchronous output enable control

• Economical 100-pin TQFP package

• Individual byte write and Global write

• Multiple chip enables for easy expansion

Logic block diagram

access time: 3.5/4.0 ns

CLK

ADV
ADSC
ADSP

A[16:0]

17

D

CS

CLK

CLK
CS
CLR

Burst logic

Address
register

AS7C33128FT18B

®

• 3.3V core power supply

• 2.5V or 3.3V I/O operation with separate V

• Linear or interleaved burst control

• Snooze mode for reduced power standby

• Common data inputs and data outputs

LBO

128K × 18

Memory

2

2

Q

17

15

17

array

DDQ

GWE

BW

BWE

BW

CE0
CE1

CE2

DQ

18

b

a

Power

ZZ

down

OE

DQb

Byte Write

registers

CLK

DQ

DQa

Byte Write

registers

CLK

DQ

Enable

register

CE
CLK

DQ

Enable

delay

register

CLK

OE

Output
Buffers

2

18

Input

registers

CLK

18

DQ [a,b]

Selection guide

–65 -75 -80 -10 Units

Minimum cycle time 7.5 8.5 10 12 ns
Maximum clock access time 6.5 7.5 8.0 10.0 ns
Maximum operating current 250 225 200 175 mA
Maximum standby current 120 100 90 90 mA
Maximum CMOS standby current (DC) 30 30 30 30 mA

12/10/04; v.1.3 Alliance Semiconductor P. 1 of 19

Copyright © Alliance Semiconductor. All rights reserved.

AS7C33128FT18B

®

2 Mb Synchronous SRAM products list

Org Part Number Mode Speed

128KX18 AS7C33128PFS18B PL-SCD 200/166/133 MHz

64KX32
64KX36 AS7C3364PFS36B PL-SCD 200/166/133 MHz

128KX18 AS7C33128PFD18B PL-DCD 200/166/133 MHz

64KX32
64KX36 AS7C3364PFD36B PL-DCD 200/166/133 MHz

128KX18 AS7C33128FT18B FT 6.5/7.5/8.0/10 ns

64KX32
64KX36 AS7C3364FT36B FT 6.5/7.5/8.0/10 ns

AS7C3364PFS32B PL-SCD 200/166/133 MHz

AS7C3364PFD32B PL-DCD 200/166/133 MHz

AS7C3364FT32B FT 6.5/7.5/8.0/10 ns

1,2

1 Core Power Supply: VDD = 3.3V + 0.165V
2 I/O Supply Voltage: VDDQ = 3.3V +

VDDQ = 2.5V +

0.165V for 3.3V I/O

0.125V for 2.5V I/O

PL-SCD : Pipelined Burst Synchronous SRAM - Single Cycle Deselect
PL-DCD : Pipelined Burst Synchronous SRAM - Double Cycle Deselect
FT : Flow-through Burst Synchronous SRAM

12/10/04; v.1.3 Alliance Semiconductor P. 2 of 19

Pin arrangement

V

DDQ

V

DQb0
DQb1

V

V

DDQ

DQb2
DQb3

V

DQb4
DQb5
V

DDQ

V
DQb6
DQb7
DQpb

V
V

DDQ

NC
NC
NC

SSQ

NC
NC

SSQ

NC

DD

NC

V

SSQ

NC

SSQ

NC
NC
NC

SS

®

DD

SS

AACE0

100

CE1NCNC

BWb

99989796959493929190898887868584838281

V

BWa

CE2

V

CLK

GWE

BWEOEADSC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

TQFP 14 × 20mm

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

31323334353637383940414243444546474849

ADSP

ADVAA

AS7C33128FT18B

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

50

A
NC
NC
V

DDQ

V

SSQ

NC
DQpa
DQa7
DQa6
V

SSQ

V

DDQ

DQa5
DQa4
VSS
NC
V

DD

ZZ
DQa3
DQa2
V

DDQ

V

SSQ

DQa1
DQa0
NC
NC
V

SSQ

V

DDQ

NC
NC
NC

AAA

LBO

12/10/04; v.1.3 Alliance Semiconductor P. 3 of 19

A

A1

A0

NC

NC

V

SS

V

DD

AAAAA

NC

NC

A

NC

AS7C33128FT18B

®

Functional description

The AS7C33128FT18B is a high-performance CMOS 2-Mbit synchronous Static Random Access Memory (SRAM) device organized as
131,072 words × 18 bits.

Fast cycle times of 7.5/8.5/10/12 ns with clock access times (tCD) of 6.5/7.5/8.0/10 ns. Three chip enable (CE) inputs permit easy memory
expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC
The burst advance pin (ADV) allows subsequent internally generated burst addresses.

Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address
register when ADSP is sampled low , the chip enables are sa mpled active, and the ou tput buffe r is enabled with OE. In a read operation, the
data accessed by the current address registered in the address registers by the positive edge of CLK are carried to the data-out buffer. ADV
is ignored on the clock edge that samples ADSP asserted, but is sampled on all subsequent clock edges. Address is incremented internally
for the next access of the burst when ADV is sampled low and both address strobes are high. Burst mode is selectable with the

LBO

With

unconnected or driven high, burst operations use an interleaved count sequence. With

count sequence.
Write cycles ar e perform ed by d isabling the output buffers with OE and asserting a write command. A global write enable GWE writes all

18 bits regardless of the state of individual BW[a,b] inputs. Alternately, when GWE is high, one or more bytes may be written by asserting
BWE and the appropriate individual byte BWn signals.

BWn is ignored on the clock edge that samples ADSP low, but it is sampled on all subsequent clock edges. Output buffers are disabled
when BWn is sampled LOW regardless of OE. Data is clocked into the data input register when BWn is sampled low. Address is
incremented internally to the next burst address if BWn

Read or write cycles may also be initiated with ADSC

and ADV are sampled low.

instead of ADSP. The differences between cycles initiated with ADSC and ADSP

are as follows:

• ADSP

must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.

), or the processor address strobe (ADSP).

LBO

input.

LBO

driven low, the device uses a linear

•WE signals are sampled on the clock edge that samples ADSC low (and ADSP high).

• Master chip enable CE0 blocks ADSP, but not ADSC.

The AS7C33128FT18B family operates from a core 3.3V power supply. I/Os use a separate power supply that can operate at 2.5V or 3.3V.
These devices are available in a 100-pin TQFP package.

TQFP capacitance

Parameter Symbol Test conditions Min Max Unit

Input capacitance C
I/O capacitance C

*Guaranteed not tested

IN

I/O

*

*

VIN = 0V - 5 pF

V

= 0V - 7 pF

OUT

TQFP thermal resistance

Description Conditions Symbol Typical Units

Thermal resistance
(junction to ambient)

Thermal resistance
(junction to top of case)

1 This parameter is sampled

1–layer θ

1

1

Test conditio ns follow standard test methods and

procedures for measuring thermal impedance,

per EIA/JESD51

4–layer θ

JA

JA

θ

JC

40 °C/W
22 °C/W

8 °C/W

12/10/04; v.1.3 Alliance Semiconductor P. 4 of 19

Signal descriptions

AS7C33128FT18B

®

Pin I/O Properties

Description

CLK I CLOCK Clock. All inputs except OE, ZZ, and LBO are synchronous to this clock.
A,A0,A1 I SYNC Address. Sampled when all chip enables are active and when ADSC or ADSP are asserted.
DQ[a,b] I/O SYNC Data. Driven as output when the chi p is enabled and when OE

CE0 I SYNC

CE1, CE2

ADSP
ADSC
ADV

GWE

I SYNC

I SYNC Address strobe processor. Asserted low to load a new address or to enter standby mode.
I SYNC Address strobe controller. Asserted low to load a new address or to enter standby mode.
I SYNC Advance. Asserted low to continue burst read/write.

I SYNC

Master chip enable. Sampled on clock edges when ADSP
ADSP is blocked. Refer to the “Synchronous truth table” for more information.

Synchronous chip enables, active high, and active low, respectively . Sampled on clock edges when

is active or when CE0 and ADSP are active.

ADSC

Global write enable. Asserted low to write all 18 bits. When high, BWE
enable.

is active.

or ADSC is active. When CE0 is inactive,

and BW[a,b] control write

BWE I SYNC Byte write enable. Asserted low with GWE high to enable effect of BW[a,b] inputs.

Write enables. Used to control write of individual bytes when GWE is high and BWE is low. If any of

BW[a,b]

I SYNC

BW[a,b] is active with GWE high and BWE low , the cy cle is a write cyc le. If all BW[a ,b] are in active ,
the cycle is a read cycle.

OE

LBO ISTATIC

I ASYNC Asynchronous output enable. I/O pins are driven when OE is active and chip is in read mode.

Selects Burst mode. When tied to V

or left floating, device follows interleaved Burst order. When

DD

driven Low, device follows linear Burst order. This signal is internally pulled High.
ZZ I ASYNC Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
NC - - No connect

Snooze Mode

SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to I
SNOOZE MODE is dictated by the length of time the ZZ is in a High state.

The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.

When the ZZ pin becomes a logic High, I

is guaranteed after the time t

SB2

is met. After entering SNOOZE MODE, all inputs except ZZ

ZZI

is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully com­plete. Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when
exiting SNOOZE MODE during t

, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE

PUS

MODE.

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. The duration of

SB2

®

Write enable truth table (per byte)

Function GWE BWE BWa BWb

Write All Bytes

Write Byte a
Write Byte b

Read

Key: X = don’t care, L = low, H = high, n = a, b;

LXXX
HLLL
HLLH
HLHL
HHXX
HLHH

BWE, BWn

= internal write signal.

Asynchronous Truth Table

Operation ZZ OE I/O Status

Snooze mode H X High-Z

Read

Write L X Din, High-Z
Deselected L X High-Z

Notes:

1. X means “Don’t Care”

2. ZZ pin is pulled down internally

3. For write cycles that follows read cycles, the output buffers must be disabled with OE

4. Snooze mode means power down state of which stand-by current does not depend on cycle times

5. Deselected means power down state of which stand-by current depends on cycle times

LLDout
L H High-Z

, otherwise data bus contention will occur.

AS7C33128FT18B

Burst sequence table

Interleaved burst address (LBO = 1) Linear burst address (LBO = 0)

A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0

1st Address

nd

2

Address

rd

3

Address

th

4

Address

0 00 11 01 1
0 10 01 11 0
1 01 10 00 1
1 11 00 10 0

1st Address

nd

2

Address

rd

3

Address

th

4

Address

0 00 11 01 1
0 11 01 10 0
1 01 10 00 1
1 11 00 11 0

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AS7C33128FT18B

®

Synchronous truth table

1

CE0

CE1 CE2 ADSP ADSC ADV

[4]

WRITE

[2]

OE Address accessed CLK Operation DQ

HXXXLX X X NA L to H DeselectHi−Z
L L X L X X X X NA L to H Deselect Hi−Z
L L X H L X X X NA L to H Deselect Hi−Z
L X H L X X X X NA L to H Deselect Hi−Z
L X H H L X X X NA L to H D eselect Hi−Z
L H L L X X X L External L to H Begin read Q
L H L L X X X H External L to H Begin read Hi−Z
L H L H L X H L External L to H Begin read Q
L H L H L X H H External L to H Begin read Hi−Z
XXXHHL H L Next L to HContinue readQ
XXXHHL H H Next L to HContinue readHi−Z
XXXHHH H L Current L to HSuspend readQ
XXXHHH H H Current L to HSuspend readHi−Z
HXXXHL H L Next L to HContinue readQ
HXXXHL H H Next L to HContinue readHi−Z
HXXXHH H L Current L to HSuspend readQ
HXXXHH H H Current L to HSuspend readHi−Z
L H L H L X L X External L to H Begin write D
XXXHHL L X Next L to HContinue writeD
HXXXHL L X Next L to HContinue writeD
XXXHHH L X Current L to HSuspend writeD
HXXXHH L X Current L to HSuspend writeD

1 X = don’t care, L = low, H = high
2 For WRITE, L means any one or more byte write enable signals (BWa or BWb) and BWE are LOW or GWE is LOW. WRITE = HIGH for all BWx, BWE, GWE HIGH. See

"Write enable truth table (per byte)," on page 6 for more information.

3 For write operation following a READ,
4 ZZ pin is always Low.

OE must be high before the input data set up time and held high throughout the input hold time

3

12/10/04; v.1.3 Alliance Semiconductor P. 7 of 19

AS7C33128FT18B

®

.

Absolute maximum ratings

1

Parameter Symbol Min Max Unit

Power supply voltage relative to GND V
Input voltage relative to GND (input pins) V
Input voltage relative to GND (I/O pins) V
Power dissipation P
DC output current I
Storage temperature (plastic) T
Temperature under bias T

1 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other

conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect reliability.

DD

, V

IN
IN

D

OUT

stg

bias

DDQ

–0.5 +4.6 V
–0.5 VDD + 0.5 V
–0.5 V

+ 0.5 V

DDQ

–1.8W

–50mA
–65 +150 °C
–65 +135 °C

Recommended operating conditions at 3.3V I/O

Parameter Symbol Min Nominal Max Unit

Supply voltage for inputs V
Supply voltage for I/O V

DD

DDQ

3.135 3.3 3.465 V

3.135 3.3 3.465 V

Ground supply Vss 0 0 0 V

Recommended operating conditions at 2.5V I/O

Parameter Symbol Min Nominal Max Unit

Supply voltage for inputs V
Supply voltage for I/O V

DD

DDQ

Ground supply Vss 0 0 0 V

3.135 3.3 3.465 V

2.375 2.5 2.625 V

12/10/04; v.1.3 Alliance Semiconductor P. 8 of 19

DC electrical characteristics for 3.3V I/O operation

Parameter Sym Conditions Min Max Unit

†

Input leakage current
Output leakage current |I

|ILI|V

|OE ≥ VIH, VDD = Max, 0V < V

LO

= Max, 0V < VIN < V

DD

Address and control pins 2* VDD+0.3

Input high (logic 1) voltage V

IH

Address and control pins -0.3** 0.8

Input low (logic 0) voltage V

Output high voltage V
Output low voltage V

IL

OH

OL

IOH = –4 mA, V

IOL = 8 mA, V

DC electrical characteristics for 2.5V I/O operation

Parameter Sym Conditions Min Max Unit

†

Input leakage current
Output leakage current |I

Input high (logic 1) voltage V

Input low (logic 0) voltage V

Output high voltage V
Output low voltage V

† LBO and ZZ pins have an internal pull-up or pull-down, and input leakage = ±10 µA.

*

V

max < VDD +1.5V for pulse width less than 0.2 X t

IH

**

V

min = -1.5 for pulse width less than 0.2 X t

IL

|ILI|V

|OE ≥ VIH, VDD = Max, 0V < V

LO

DD

Address and control pins 1.7* VDD+0.3 V

IH

Address and control pins -0.3** 0.7 V

IL

OH

OL

CYC

CYC

IOH = –4 mA, V

IOL = 8 mA, V

AS7C33128FT18B

®

DD

< V

OUT

DDQ

I/O pins 2* V

I/O pins -0.5** 0.8

= 3.135V 2.4 – V

DDQ

= 3.465V – 0.4 V

DDQ

= Max, 0V < VIN < V

OUT

DD

< V

I/O pins 1.7* V

I/O pins -0.3** 0.7 V

= 2.375V 1.7 – V

DDQ

= 2.625V – 0.7 V

DDQ

-2 2 µA

-2 2 µA

DDQ

-2 2 µA

DDQ

-2 2 µA

+0.3

DDQ

V

V

+0.3 V

IDD operating conditions and maximum limits

Parameter Sym Conditions -65 -75 -80 -10 Unit

1

Operating power supply current

I

I

Standby power supply current

I

I

1 ICC given with no output loading. ICC increases with faster cycle times and greater output loading.

CE0 < VIL, CE1 > VIH, CE2 < VIL, f = f

CC

SB

SB1

SB2

All VIN ≤ 0.2V or >

all V

Deselected, f = f

= 0 mA, ZZ < V

I

OUT

VDD – 0.2V,
, ZZ < V

f = f

Max

Deselected, f = 0, ZZ < 0.2V,

≤ 0.2V or ≥ VDD – 0.2V

IN

Max

all V

≤ VIL or ≥ V

IN

IL

Deselected,

IL

, ZZ ≥ VDD – 0.2V,

IH

12/10/04; v.1.3 Alliance Semiconductor P. 9 of 19

Max

,

250 225 200 175 mA

120 100 90 90

30 30 30 30

30 30 30 30

mA

Timing characteristics over operating range

AS7C33128FT18B

®

Parameter Sym

Cycle time t
Clock access time t
Output enable LOW to data valid t
Clock HIGH to output Low Z t
Data output invalid from clock HIGH t
Output enable LOW to output Low Z t
Output enable HIGH to output High Z t
Clock HIGH to output High Z t
Output enable HIGH to invalid output t
Clock HIGH pulse width t
Clock LOW pulse width t
Address setup to clock HIGH t
Data setup to clock HIGH t
Write setup to clock HIGH t
Chip select setup to clock HIGH t
Address hold from clock HIGH t
Data hold from clock HIGH t
Write hold from clock HIGH t
Chip select hold from clock HIGH t
ADV

setup to clock HIGH t

ADSP

setup to clock HIGH t

ADSC

setup to clock HIGH t

ADV

hold from clock HIGH t

ADSP

hold from clock HIGH t

ADSC

hold from clock HIGH t

1 See “Notes” on page 16.

CYC

CD
OE

LZC

OH
LZOE
HZOE

HZC

OHOE

CH

CL

AS

DS

WS

CSS

AH

DH

WH

CSH

ADVS
ADSPS
ADSCS

ADVH
ADSPH

ADSCH

–65 -75 -80 –10

Min Max Min Max Min Max Min Max

Notes

Unit

7.5 – 8.5 – 10 – 12 – ns
– 6.5 – 7.5 – 8.0 – 10 ns
– 3.5 – 3.5 – 4.0 – 4.0 ns

2.5 – 2.5 – 2.5 – 2.5 – ns 2,3,4

2.5 – 2.5 – 2.5 – 2.5 – ns 2
0 – 0 – 0 – 0 – ns 2,3,4
– 3.0 – 3.5 – 4.0 – 5.0 ns 2,3,4
– 3.0 – 3.5 – 4.0 – 5.0 ns 2,3,4
0–0–0– 0 – ns

2.5 – 3.0 – 4.0 – 4.0 – ns 5

2.5 – 3.0 – 4.0 – 4.0 – ns 5

1.5 – 2.0 – 2.0 – 2.0 – ns 6

1.5 – 2.0 – 2.0 – 2.0 – ns 6

1.5 – 2.0 – 2.0 – 2.0 – ns 6,7

1.5 – 2.0 – 2.0 – 2.0 – ns 6,8

0.5 – 0.5 – 0.5 – 0.5 – ns 6

0.5 – 0.5 – 0.5 – 0.5 – ns 6

0.5 – 0.5 – 0.5 – 0.5 – ns 6,7

0.5 – 0.5 – 0.5 – 0.5 – ns 6,8

1.5 – 2.0 – 2.0 – 2.0 – ns 6

1.5 – 2.0 – 2.0 – 2.0 – ns 6

1.5 – 2.0 – 2.0 – 2.0 – ns 6

0.5 – 0.5 – 0.5 – 0.5 – ns 6

0.5 – 0.5 – 0.5 – 0.5 – ns 6

0.5 – 0.5 – 0.5 – 0.5 – ns 6

1

Snooze Mode Electrical Characteristics

Description Conditions Symbol Min Max Units

Current during Snooze Mode ZZ > V

IH

ZZ active to input ignored t
ZZ inactive to input sampled t
ZZ active to SNOOZE current t
ZZ inactive to exit SNOOZE current t

12/10/04; v.1.3 Alliance Semiconductor P. 10 of 19

I

SB2
PDS
PUS

ZZI

RZZI

30 mA
2cycle
2cycle

2cycle

0

Key to switching waveforms

AS7C33128FT18B

®

Timing waveform of read cycle

CLK

Address

GWE

CE0, CE2

ADSP

ADSC

, BWE

t

ADSPS

t

t

CSS

AS

t

ADSPH

t

AH

t

WS

t

CSH

t

ADSCS

t

WH

don’t careFalling inputRising input

t

CYC

t

CH

t

ADSCH

LOAD NEW ADDRESS

A2A1 A3

t

CL

Undefined

CE1

t

ADVS

t

ADVH

ADV

ADV inserts wait states

OE

t

OE

t

LZOE

Dout

Read
Q(A1)

Q(A1)

Suspend

Read
Q(A1)

Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. BW[a:d] is don’t care.

t

HZOE

Read

Q(A2)

t

OH

t

CD

Burst
Read

2Ý10

Q(A2Ý10)

Suspend

Read

)

Q(A

2Ý10

Q(A2Ý01) Q(A3Ý01)

Burst
Read

2Ý01

Q(A

)

Q(A

Q(A2Ý11)

Burst
Read

2Ý11

)

Q(A

Q(A3)

Q(A3Ý10)

Q(A3Ý11)

t

Read

Q(A3) DSEL

)

Q(A

Burst
Read

3Ý01

Burst
Read

)

Q(A

3Ý10

Burst
Read

3Ý11

)

Q(A

)

HZC

12/10/04; v.1.3 Alliance Semiconductor P. 11 of 19

Timing waveform of write cycle

t

CH

CLK

t

ADSPS

t

ADSPH

ADSP

ADSC

t

AS

t

AH

Address

BWE

BW[a:b]

A1

A2

t

CYC

t

CL

®

ADSC LOADS NEW ADDRESS

A3

AS7C33128FT18B

t

ADSCS

t

ADSCH

t

WS

t

WH

CE0, CE2

CE1

ADV

OE

Din

t

Read

Q(A1)

CSS

t

CSH

D(A1)

Suspend

Write

D(A1)

ADV SUSPENDS BURST

D(A2Ý01)

Read

Q(A2)

Suspend

Write
D(A2)

D(A

ADV
Burst
Write

2Ý01

D(A2Ý10) D(A3)D(A2) D(A2Ý01) D(A3Ý01) D(A3Ý10)

Suspend

Write

2Ý01

D(A

)

D(A2Ý11)

ADV

Burst

)

Write

2Ý10

D(A

ADV
Burst
Write

)

D(A

2Ý11

Write
D(A3)

)

D(A

t

ADVS

t

DS

Burst
Write

3Ý01

t

ADVH

t

DH

ADV
Burst
Write

)

3Ý10

D(A

)

Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low.

12/10/04; v.1.3 Alliance Semiconductor P. 12 of 19

®

Timing waveform of read/write cycle (ADSP Controlled; ADSC High)

t

CYC

t

CL

t

AS

t

AH

A3

t

WS

t

WH

CLK

ADSP

Address

BWE

BW[a:b]

CE0, CE2

A1

t

ADSPS

t

ADSPH

t

CH

A2

AS7C33128FT18B

CE1

ADV

OE

t

Din

t

CD

t

Suspend

Read
Q(A1)

HZOE

Read

Q(A2)

t

Dout

LZC

Read

Q(A1)

Q(A1)

Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low.

DS

t

D(A2)

t

ADVS

DH

t

LZOE

Suspend

Write

D(A2)

t

ADVH

t

OE

Read

Q(A3)

Q(A3)

Q(A

ADV
Burst
Read

3Ý01

t

OH

Q(A3Ý01)

)

Q(A

Q(A3Ý10) Q(A3Ý11)

ADV
Burst
Read

3Ý10

ADV
Burst
Read

)

Q(A

3Ý11

)

Suspend

Read

3Ý11

Q(A

)

12/10/04; v.1.3 Alliance Semiconductor P. 13 of 19

®

Timing waveform of read/write cycle(ADSC controlled, ADSP = HIGH)

t

CYC

CLK

t

CH

t

CL

AS7C33128FT18B

ADSC

ADDRESS

BWE

BW[a:b]

CE0,CE2

CE1

OE

Dout

t

ADSCS

t

CSS

A1

t

LZOE

t

ADSCH

t

CSH

t

OE

Q(A1)

A2

Q(A2)

A3

A4

Q(A3)

t

HZOE

Q(A4)

A5

A6

t

WS

A7

t

t

WH

AS

A8

t

AH

A9

t

CD

A10

Q(A9)

Q(A10)

t

OH

Din

READ

Q(A1)

READ
Q(A2)

READ
Q(A3)

READ
Q(A4)

D(A5)

t

DS

WRITE

D(A5)

D(A6)

t

DH

WRITE

D(A6)

D(A7)

WRITE

D(A7)

D(A8)

WRITE

D(A8)

READ

Q(A9)

READ

Q(A10)

Note: ADV is don’t care here.

12/10/04; v.1.3 Alliance Semiconductor P. 14 of 19

Timing waveform of power down cycle

CLK

AS7C33128FT18B

®

t

CYC

t

CH

t

CL

ADSP

ADSC

DDRESS

BWE

BW[a:b]

CE0,CE2

CE1

ADV

OE

t

ADSPS

t

CSS

A1

t

ADSPS

t

CSH

A2

t

WS

t

WH

t

OE

t

LZOE

READ
Q(A1)

Q(A1)

t

PDS

ZZ Setup Cycle

t

ZZI

READ

Q(A1Ý01)

t

HZC

t

HZOE

t

PUS

ZZ Recovery Cycle Normal Operation Mode

t

RZZI

I

SB2

Sleep
State

READ
Q(A2)

Q(A2)

Q(A2(Ý01))

READ

Q(A2Ý01)

Dout

I

supply

Din

ZZ

12/10/04; v.1.3 Alliance Semiconductor P. 15 of 19

AS7C33128FT18B

c

®

AC test conditions

• Output load: see Figure B, except for t

• Input pulse level: GND to 3V. See Figure A.

• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.

• Input and output timing reference levels: 1.5V.

+3.0V

GND

10%

90%

90%

10%

D

Figure A: Input waveform

Notes
1 For test conditions, see AC Test Conditions, Figures A, B, C.
2 This parameter measured with output load condition in Figure C.
3 This parameter is sampled, but not 100% tested.
4t
5 tCH measured as HIGH above VIH and tCL measured as LOW below VIL.
6 This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs

7 Write refers to
8 Chip select refers to

is less than t

HZOE

must meet the setup and hold times for all rising edges of CLK when chip is enabled.

; and t

LZOE

GWE, BWE, BW[a,b].

CE0, CE1, CE2

HZC

is less than t

, t

LZOE

, t

LZC

Z0 = 50

OUT

Figure B: Output load (A)

at any given temperature and voltage.

LZC

HZOE

Ω

, t

, see Figure C.

HZC

50

Ω

30 pF*

VL = 1.5V

for 3.3V I/O;
= V

DDQ

for 2.5V I/O

Thevenin equivalent:

+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O

319

D

OUT

353

/2

Ω / 1538Ω

Ω / 1667Ω

5 pF*
GND

*including scope

and jig capacitan

Figure C: Output load (B)

12/10/04; v.1.3 Alliance Semiconductor P. 16 of 19

Package Dimensions

100-pin quad flat pack (TQFP)

AS7C33128FT18B

®

Hd

D

L1

L

TQFP

Min Max

A1 0.05 0.15
A2 1.35 1.45

b 0.22 0.38

c 0.09 0.20
D 13.90 14.10
E 19.90 20.10

e 0.65 nominal

Hd 15.85 16.15
He 21.80 22.20

L 0.45 0.75

L1 1.00 nominal

α 0° 7°

Dimensions in millimeters

A1 A2

He

b

α

e

E

12/10/04; v.1.3 Alliance Semiconductor P. 17 of 19

AS7C33128FT18B

®

Ordering information

Package Width –65 -75 –80 –10

TQFP x18

TQFP x18

AS7C33128FT18B-

65TQC

AS7C33128FT18B-

65TQI

Note: Ass suffix ‘N’ to the above part number for Lead Free Parts (Ex. AS7C33128FT18B-65TQCN)

Part numbering guide

AS7C 33 128 FT 18 B –XX TQ C/I X

12345678910

1. Alliance Semiconductor SRAM Prefix

2. Operating voltage: 33=3.3V

3. Organization: 128=128K

4. Flowthrough.

5. Organization: 18=x18

6. Production version: B= product revision

7.

Clock access time: [-65 = 6.5 ns; -75 = 7.5 ns; -80 = 8.0 ns; -10 = 10.0]

8. Package type: TQ=TQFP

9. Operating temperature: C=Commercial (

10. X = Lead free part

AS7C33128FT18B-

75TQC

AS7C33128FT18B-

75TQI

0° C to 70° C); I=Industrial (

AS7C33128FT18B-

AS7C33128FT18B-

80TQC

80TQI

-40

° C to 85° C)

AS7C33128FT18B-

10TQC

AS7C33128FT18B-

10TQI

12/10/04; v.1.3 Alliance Semiconductor P. 18 of 19

AS7C33128FT18B

®

®

Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel: 408 - 855 - 4900

Copyright © Alliance Semiconductor
All Rights Reserved
Part Number: AS7C33128FT18B
Document Version: v.1.3

Fax: 408 - 855 - 4999
www.alsc.com

© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered
trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make
changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document.
The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at
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