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查询AS7C32096A-10TC供应商
February 2005
Preliminary Information
AS7C32096A
®
3.3V 256K × 8 CMOS SRAM
Features
• Industrial and commercial temperature
• Organization: 262,144 words × 8 bits
• Center power and ground pins
• High speed
- 10/12/15/20 ns address access time
- 4/5/6/7 ns output enable access time
• Low power consumption: ACTIVE
- 650 mW / max @ 10 ns
• Low power consumption: STANDBY
- 28.8 mW / max CMOS
Logic block diagram
V
CC
GND
Input buffer
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Row decoder
262,144 × 8
Array
(2,097,152)
Column decoder
A10
A11
A12
A13
A14
A15
Sense amp
Control
Circuit
A16
A17
WE
OE
CE
I/O1
I/O8
• Equal access and cycle times
• Easy memory expansion with
• TTL-compatible, three-state I/O
• JEDEC standard packages
- 44-pin TSOP 2
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Pin arrangements
44-pin TSOP 2
NC
NC
A0
A1
A2
A3
A4
CE
I/O1
I/O2
V
CC
GND
I/O3
I/O4
WE
A5
A6
A7
A8
A9
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
CE, OE
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
inputs
NC
NC
NC
A17
A16
A15
A14
OE
I/O8
I/O7
GND
V
I/O6
I/O5
A13
A12
A11
A10
NC
NC
NC
NC
CC
Selection guide
–10 –12 –15 –20 Unit
Maximum address access time 10 12 15 20 ns
Maximum output enable access time 4 5 6 7 ns
Maximum operating current
Maximum CMOS standby current 8 8 8 8 mA
2/24/05, v. 1.0 Alliance Semiconductor P. 1 of 9
Industrial 180 160 140 110 mA
Commercial 170 150 130 100 mA
Copyright © Alliance Semiconductor. All rights reserved.
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AS7C32096A
®
Functional description
The AS7C32096A is a high-performance CMOS 2,097,152-bit Static Random Access Memory (SRAM) device organized as
262,144 words × 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are
desired.
Equal address access and cycle times (t
ideal for high-performance applications. The chip enable input CE
systems.
When CE
is high the device enters standby mode. The device is guaranteed not to exceed 28.8mW power consumption in
CMOS standby mode.
A write cycle is accomplished by asserting write enable (WE
on the rising edge of WE
(write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins
only after outputs have been disabled with output enable (OE
A read cycle is accomplished by asserting output enable (OE
drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write
enable is active, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible, and operation is from a single 3.3V supply voltage. This device is available as
per industry standard 44-pin TSOP 2 package.
, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 4/5/6/7 ns are
AA
permits easy memory expansion with multiple-bank memory
) and chip enable (CE). Data on the input pins I/O1–I/O8 is written
) or write enable (WE).
) and chip enable (CE), with write enable (WE) high. The chip
Absolute maximum ratings
Parameter Symbol Min Max Unit
Voltage on V
Voltage on any pin relative to GND V
Power dissipation P
Storage temperature (plastic) T
Temperature with V
DC current into output (low) I
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
relative to GND V
CC
applied T
CC
t1
t2
D
stg
bias
OUT
–0.5 +5.0 V
–0.5 VCC +0.5 V
–1.0W
–65 +150 °C
–55 +125 °C
–20mA
Truth table
CE WE OE Data Mode
H X X High Z Standby (I
L H H High Z Output disable (I
LHL D
LLX D
Key: X = Don’t care, L = Low, H = High
OUT
IN
Read (ICC)
Write (ICC)
SB
, I
SB1
CC
)
)
2/24/05, v. 1.0 Alliance Semiconductor P. 2 of 9
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®
Recommended operating condition
Parameter Symbol Min Nominal Max Unit
Supply voltage V
Input voltage
Ambient operating
temperature
*
V
min = –1.0V for pulse width less than 5ns.
IL
**
max = VCC + 2.0V for pulse width less than 5ns.
V
IH
commercial T
industrial T
(10/12/15/20) 3.0 3.3 3.6 V
CC
**
V
IH
*
V
IL
A
A
DC operating characteristics (over the operating range)1
Parameter Symbol Test conditions
Input leakage
current
Output leakage
current
Operating power
supply current
Standby power
supply current
Output voltage
|I
|I
I
I
V
V
LO
CC
I
SB
SB1
LI
OL
OH
|
|
V
= Max, VIN = GND to V
CC
= Max, CE = V
V
CC
V
= GND to V
OUT
VCC = Max, CE ≤ V
f = f
Max
, I
OUT
= 0mA
VCC = Max, CE ≥ V
IL
IH,
CC
IH
CC
Industrial
Commercial
f = f
Max
VCC = Max,
CE
≥ V
V
≤ 0.2V or VIN ≥ VCC – 0.2V,
IN
CC
– 0.2V,
f = 0
IOL = 8 mA, VCC = Min
IOH = –4 mA, VCC = Min
AS7C32096A
2.0 – VCC + 0.5 V
–0.5 – 0.8 V
0– 70°C
–40 – 85 °C
–10 –12 –15 –20
UnitMin Max Min Max Min Max Min Max
–1–1–1–1µA
–1–1–1–1µA
–180–160–140–110mA
- 170 - 150 - 130 - 100 mA
–60–60–60–60mA
–8–8–8–8mA
–0.4–0.4–0.4–0.4V
2.4–2.4–2.4–2.4– V
Capacitance (f = 1MHz, Ta = 25° C, VCC = NOMINAL)
4
Parameter Symbol Signals Test conditions Max Unit
Input capacitance C
I/O capacitance C
2/24/05, v. 1.0 Alliance Semiconductor P. 3 of 9
IN
I/O
A, CE, WE, OE
I/O
VIN = 0V 5 pF
= V
V
IN
= 0V 7 pF
OUT
Page 4
AS7C32096A
®
Read cycle (over the operating range)
Parameter Symbol
Read cycle time
Address access time
Chip enable (CE
Output enable (OE
) access time
) access time
Output hold from address change
CE
Low to output in low Z
CE
High to output in high Z
OE
Low to output in low Z
OE
High to output in high Z
Power up time
Power down time
t
RC
t
AA
t
ACE
t
OE
t
OH
t
CLZ
t
CHZ
t
OLZ
t
OHZ
t
PU
t
PD
Key to switching waveforms
2,8
–10 –12 –15 –20
Unit NotesMin Max Min Max Min Max Min Max
10–12–15–20–ns
–10–12–15–20ns2
–10–12–15–20ns2
–4–5–6–7ns
3–3–3–3–ns4
3–3–3–3–ns3,4
–5–6–7–9ns3,4
0–0–0–0–ns3,4
–5–6–7–9ns3,4
0–0–0–0–ns3,4
–10–12–15–20ns3,4
Undefined/don’t careFalling inputRising input
Read waveform 1 (address controlled)
Address
t
AA
D
OUT
Read waveform 2 (CE
CE
OE
D
OUT
Supply
current
, OE controlled)
t
OE
t
OLZ
t
ACE
t
CLZ
t
PU
50% 50%
t
RC1
2,5,6,8
t
RC
2,5,7,8
Data valid
Data valid
t
OH
t
OHZ
t
CHZ
t
PD
I
CC
I
SB
2/24/05, v. 1.0 Alliance Semiconductor P. 4 of 9
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Write cycle (over the operating range)9
Parameter Symbol
Write cycle time
Chip enable (CE
) to write end
Address setup to write end
Address setup time
Write pulse width (OE
Write pulse width (OE
= high)
= low
Address hold from end of write
Write recovery time
Data valid to write end
Data hold time
Write enable to output in high Z
Output active from write end
t
t
t
t
t
WP1
t
WP2
t
t
t
t
t
t
WC
CW
AW
AS
AH
WR
DW
DH
WZ
OW
10–12–15–20–ns
7–8–10–12–ns
7–8–10–12–ns
0–0–0–0–ns
7–8–10–12–ns
10–12–15–20–ns
0–0–0–0–ns
0–0–0–0–ns
5–6–7–9–ns
0–0–0–0–ns3,4
05060709ns3,4
3–3–3–3–ns3,4
AS7C32096A
®
–10 –12 –15 –20
Unit NotesMin Max Min Max Min Max Min Max
Write waveform 1 (WE controlled)9
Address
WE
t
AS
D
IN
D
OUT
t
WZ
t
WC
t
AW
t
WP
t
DW
Data valid
t
OW
t
t
t
WR
AH
DH
2/24/05, v. 1.0 Alliance Semiconductor P. 5 of 9
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Write waveform 2 (CE controlled)9
t
AW
Address
t
AS
t
CW
CE
WE
t
WZ
D
IN
D
OUT
AC test conditions
- Output load: see Figure B.
- In put pulse level: GND to 3.0V. See Figures A and B.
- In put rise and fall times: 2 ns. See Figure A.
- In put and output timing reference levels: 1.5V.
AS7C32096A
®
t
WC
t
WP
t
DW
Data valid
t
WR
t
AH
t
DH
+3.3V
D
OUT
320
10
C
GND
Ω
+3.0V
GND
90%
10%
2 ns
Figure A: Input pulse
90%
10%
D
OUT
350
Ω
Figure B: 3.3V Output load
Notes
1During V
2 For test conditions, see AC Test Conditions.
3t
CLZ
4 This parameter is guaranteed, but not tested.
5WE
6CE
and OE are LOW for read cycle.
7 Address valid prior to or coincident with CE
8 All read cycle timings are referenced from the last valid address to the first transitioning address.
9 All write cycle timings are referenced from the last valid address to the first transitioning address.
10 C=30pF, except on High Z and Low Z parameters, where C=5pF.
power-up, a pull-up resistor to V
CC
and t
is HIGH for read cycle.
are specified with CL = 5pF as in Figure B. Transition is measured ±500 mV from steady-state voltage.
CHZ
on CE is required to meet ISB specification.
CC
transition Low.
Thevenin equivalent:
168
Ω
+1.728V
2/24/05, v. 1.0 Alliance Semiconductor P. 6 of 9
Page 7
Package dimensions
AS7C32096A
®
444342414039 38 37 363534333231
44-pin TSOP 2
1234567891011121314
d
A
A
1
b
e
3029
1516
282726
17181920
25
21
24
22
23
c
44-pin TSOP 2
Min(mm) Max(mm)
A 1.2
E
E
1
A
A
0.05 0.15
1
0.95 1.05
2
b 0.30 0.45
c 0.12
0.21
d 18.31 18.52
E
A
2
0–5°
L
E 11.68 11.94
e 0.80 (typical)
10.06 10.26
1
L 0.40 0.60
2/24/05, v. 1.0 Alliance Semiconductor P. 7 of 9
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AS7C32096A
®
Ordering codes
Package Temperature 10 ns 12 ns 15 ns 20 ns
TSOP 2
Note: Add suffix ‘N’ to the above part number for Lead Free Parts. (Ex: AS7C32096A - 10TIN)
Part numbering system
AS7C X 2096A –XX T X X
SRAM
prefix
Commercial AS7C32096A-10TC AS7C32096A-12TC AS7C32096A-15TC AS7C32096A-20TC
Industrial AS7C32096A-10TI AS7C32096A-12TI AS7C32096A-15TI AS7C32096A-20TI
Voltage:
3 - 3.3V CMOS
Device
number
Access time
Package:
T: TSOP 2
Temperature ranges:
C: Commercial, 0°C to 70°C
I: Industrial, –40°C to 85°C
N=Lead Free Parts
2/24/05, v. 1.0 Alliance Semiconductor P. 8 of 9
Page 9
®
AS7C32096A
®
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel: 408 - 855 - 4900
Fax: 408 - 855 - 4999
Copyright © Alliance Semiconductor
All Rights Reserved
Preliminary Information
Part Number: AS7C32096A
Document Version: v. 1.0
www.alsc.com
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered
trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make
changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document.
The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at
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