Datasheet AS7C31026B Datasheet (Alliance Semiconductor)

March 2004

3.3 V 64K X 16 CMOS SRAM

Features

• Industrial and commercial versions

• Organization: 65,536 words × 16 bits

• Center power and ground pins for low noise

• High speed

- 10/12/15/20 ns address access time

- 5, 6, 7, 8 ns output enable access time

• Low power consumption: ACTIVE

- 288 mW / max @ 10 ns

• Low power consumption: STANDBY

- 18 mW / max CMOS I/O

• 6 T 0.18 u CMOS technology

®

• Easy memory expansion with

CE, OE inputs

• TTL-compatible, three-state I/O

• JEDEC standard packaging

- 44-pin 400 mil SOJ

- 44-pin TSOP 2-400

• ESD protection ≥ 2000 volts

• Latch-up current ≥ 200 mA

AS7C31026B

Logic block diagram

A0 A1 A2 A3 A4 A5

WE

UB

OE

LB

CE

I/O0–I/O7

I/O8–I/O15

A6 A7

Row decoder

I/O

buffer

Control circuit

Column decoder

A8

64 K × 16

Array

A9

A11

A10

V

CC

GND

A12

A13

A14

A15

Pin arrangement

44-Pin SOJ (400 mil), TSOP 2

A4 A3 A2 A1 A0

CE I/O0 I/O1 I/O2 I/O3 V

CC

GND

I/O4 I/O5 I/O6 I/O7

WE A15 A14 A13 A12

NC

1

44

AS7C31026B

A5

43

A6

42

A7

41

OE

UB

40

LB

39

I/O15

38

I/O14

37

I/O13

36

I/O12

35

GND

34

V

33

CC

I/O11

32

I/O10

31

I/O9

30

I/O8

29

NC

28

A8

27

A9

26

A10

25

A11

24

NC

23

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

Selection guide

-10 -12 -15 -20 Unit

Maximum address access time Maximum output enable access time Maximum operating current 80 75 70 65 mA Maximum CMOS standby current 5555mA

10 12 15 20 ns

5678ns

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Functional description

The AS7C31026B is a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 65,536 words × 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired.

Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5, 6, 7, 8 ns are ideal for high-performance applications.

When CE is high, the device enters standby mode. A write cycle is accomplished by asserting wr ite ena ble (WE ) an d chi p enable (CE). Data on the input pins I/O0 through I/O15 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE

A read cycle is accomplished by asserting output enable (OE with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output drivers stay in high-impedance mode.

The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O0 through I/O7, and UB controls the higher bits, I/O8 through I/O15.

All chip inputs and outputs are TTL-compatible, and operation is from a single 3.3 V supply. The device is packaged in common industry standard packages.

) and chip enable (CE) with write enable (WE) high. The chips drive I/O pins

Absolute maximum ratings

Parameter Symbol Min Max Unit

Voltage on V Voltage on any pin relative to GND V Power dissipation P Storage temperature (plastic) T Ambient temperature with VCC applied T DC current into outputs (low) I

Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

relative to GND V

CC

t1 t2 D

stg

bias

OUT

–0.50 +5.0 V –0.50 VCC +0.50 V

–1.0W –65 +150 °C –55 +125 °C

–20mA

) or write enable (WE).

Truth table

CE WE OE LB UB I/O0–I/O7 I/O8–I/O15 Mode

H X X X X High Z High Z Standby (I LHLLHD

OUT

L H L H L High Z D LHLLLD LLXLLD LLXLHD

OUT

IN IN

L L X H L High Z D L

L

H X

X H

High Z High Z O utput disable (I

High Z Read I/O0–I/O7 (ICC)

Read I/O8–I/O15 (I Read I/O0–I/O15 (ICC)

Write I/O0–I/O15 (ICC)

D

OUT OUT

D

IN

High Z Write I/O0–I/O7 (ICC)

IN

Write I/O8–I/O15 (ICC)

Key: H = high, L = low, X = don’ t care.

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SB

), I

SBI

CC

)

CC)

)

®

Recommended operating conditions

Parameter Symbol Min Nominal Max Unit

Supply voltage V Input voltage V

commercial T

Ambient operating temperature

V

= -1.0V for pulse width less than 5ns

IL

V

+ 1.5V for pulse width less than 5ns

IH = VCC

industrial T

CC

IH

V

IL A A

3.0 3.3 3.6 V

2.0 – VCC + 0.5 V

–0.5 – 0.8 V

0– 70o C

–40 – 85

DC operating characteristics (over the operating range)1

-10 -12 -15 -20

Parameter Sym Test conditions

Input leakage current

Output leakage current

Operating power supply current

Standby power supply current

Output voltage

|

| I

LI

|

| I

LO

V

I

CC

I

SB

CE

VCC = Max, CE ≥ VCC–0.2 V,

I

SB1

VIN ≥ VCC–0.2 V, f = 0

V

OL

V

OH

IOL = 8 mA, VCC = Min – 0.4 – 0.4 – 0.4 – 0.4 V

IOH = –4 mA, VCC = Min 2.4 – 2.4 – 2.4 – 2.4 – V

= Max

V

CC

= GND to V

IN

VCC = Max

CE = VIH,

= GND to V

OUT

VCC = Max,

≤ VIL, I

f = f

OUT

Max

VCC = Max,

CE ≥ VIH, f = f

≤ 0.2 V or

V

IN

CC

= 0mA

Max

–1–1–1–1µA

–80–75– 70 – 65mA

–30–25–20–20

–5–5–5–5

AS7C31026B

o

C

UnitMin Max Min Max Min Max Min Max

mA

Capacitance (f = 1MHz, Ta = 25 °C, VCC = NOMINAL)

2

Parameter Symbol Signals T est conditions Max Unit

Input capacitance C I/O capacitance C

IN

I/O

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A, CE, WE, OE, LB, UB VIN = 0 V 5 pF

I/O VIN = V

= 0 V 7 pF

OUT

AS7C31026B

t

®

Read cycle (over the operating range)

Parameter Symbol

Read cycle time t Address access time t Chip enable (CE Output enable (OE

) access time t

) access time t Output hold from address change t CE low to output in low Z t CE

high to output in high Z t

OE

low to output in low Z t Byte select access time t Byte select Low to low Z t Byte select High to high Z t OE

high to output in high Z t Power up time t Power down time t

RC AA

ACE

OE

OH CLZ CHZ OLZ

BA BLZ BHZ OHZ

PU PD

3,9

-10

-12 -15 -20 Unit NotesMin Max Min Max Min Max Min Max

10–12–15–20–ns

–10–12–15–20ns3 –10–12–15–20ns3 –5–6–7–8ns 3–3–3–3–ns5 3–3–3–3–ns4, 5 –3–3–4–5ns4, 5 0–0–0–0–ns4, 5 –5–6–7–8ns 0–0–0–0–ns4, 5 –5–6–6–8ns4, 5 –5–6–7–8ns4, 5 0–0–0–0–ns4, 5 – 10 – 12 – 15 20 ns 4, 5

Key to switching waveforms

Read waveform 1 (address controlled)

Address

t

OH

Data

OUT

3,6,7,9

Undefined output/don’t careFalling inputRising input

RC

t

AA

Data validPrevious data valid

t

OH

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Read waveform 2 (OE, CE, UB, LB controlled)

Address

t

AA

OE

t

OLZ

CE

LB, UB

t

BLZ

Data

IN

Write cycle (over the operating range)

Parameter Symbol

Write cycle time t Chip enable (CE

) to write end t Address setup to write end t Address setup time t Write pulse width t Write recovery time t Address hold from end of write t Data valid to write end t Data hold time t Write enable to output in high Z t Output active from write end t Byte select low to end of write t

WC CW AW

AS WP WR AH DW DH WZ OW BW

t

LZ

11

t

ACE

t

-10 -12 -15 -20

10 – 12 – 15 – 20 – ns

8–9–10–12– ns 8–9–10–12– ns 0–0–0–0–ns 7 – 8 – 9 – 12 – ns 0–0–0–0–ns 0–0–0–0–ns 5 – 6 – 8 – 10 – ns 0–0–0–0–ns 5 – 5 – 6 – 7 – 8 ns 4, 5 1 – 1 – 1 – 2 – ns 4, 5 7–8–9–9–ns

3,6,8,9

OE

BA

t

RC

t

OH

t

OHZ

t

HZ

t

BHZ

Data valid

Unit NotesMin Max Min Max Min Max Min Max

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Write waveform 1 (WE controlled)

Address

CE

LB, UB

t

WE

Data

IN

Data

OUT

Data undefined

Write waveform 2 (CE controlled)

Address

t

AS

CE

LB, UB

WE

Data

IN

t

CLZ

Data

OUT

high Z high Z

10,11

AS

10,11

Data undefined

t

AW

t

WC

CW

BW

WZ

WC

CW

BW

WZ

t

WP

t

WP

t

DW

Data valid

t

AH

t

Data valid

t

AH

t

WR

t

DH

high Z

WR

t

DH

t

OW

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AC test conditions

– Output load: see Figure B. – Input pulse level: GND to 3.0 V. See Figure A. – Input rise and fall times: 2 ns. See Figure A. – Input and output timing reference levels: 1.5

+3.0 V

GND

90%

10%

2 ns

Figure A: Input pulse

90%

10%

Notes

1 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification. 2 This parameter is sampled, but not 100% tested. 3 For test conditions, see AC Test Conditions, Figures A and B. 4 These parameters are specified with C 5 This parameter is guaranteed, but not tested.

is high for read cycle.

6WE 7CE

and OE are low for read cycle. 8 Address is valid prior to or coincident with CE 9 All read cycle timings are referenced from the last valid address to the first transitioning address. 10 N/A 11 All write cycle timings are referenced from the last valid address to the first transitioning address. 12 Not applicable. 13 C = 30 pF, except all high Z and low Z parameters where C = 5 pF.

= 5 pF, as in Figures B. Transition is measured ± 500 mV from steady-state voltage.

L

transition low.

Thevenin Equivalent:

168

D

OUT

Ω

+1.728 V

+3.3 V

320

D

OUT

255

Ω

13

C GND

Figure B: 3.3 V Output load

AS7C31026B

Ω

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Package dimensions

AS7C31026B

®

44434241 40 39 38373635343332 31

44-pin TSOP 2

1234567891011121314

D

A

A1

b

e

D

e

44-pin SOJ

Pin 1

B

A

1

b

3029

2827 2625

1516

1718 1920

Seating

plane

23

He

E

c

44-pin TSOP 2

Min

(mm)

Max

(mm)

A 1.2 A1 0.05 0.15 A2 0.95 1.05

212422

b c 0.120

0.30

0.45

0.21

D 18.31 18.52

A2

0–5

°

l

E

10.06

10.26

He 11.68 11.94

e 0.80 (typical)

l 0.40 0.60

44-pin SOJ

400 mil

Min (in) Max (in)

E

1

2

c

A

2

A

E

A 0.128 0.148 A A

0.025 –

1

0.105 0.115

2

B 0.026 0.032

b 0.015 0.020

c 0.007 0.013 D 1.120 1.130 E 0.370 NOM

E E

0.395 0.405

1

0.435 0.445

2

e 0.050 NOM

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Ordering codes

Package\Access time Volt/Temp 10 ns 12 ns 15 ns 20 ns

Plastic SOJ, 400 mil

TSOP 2, 10.2 x 18.4 mm

Note: Add suffix ‘N’ to the above part number for lead free parts (Ex.

Part numbering system

AS7C X 1026B –XX X X X

SRAM

prefix

Voltage:

3 = 3.3 V CMOS

3.3 V commercial AS7C31026B-10JC AS7C31026B-12JC AS7C31026B-15JC AS7C31026B-20JC

3.3 V industrial AS7C31026B-10JI AS7C31026B-12JI AS7C31026B-15JI AS7C31026B-20JI

3.3 V commercial AS7C31026B-10TC AS7C31026B-12TC AS7C31026B-15TC AS7C31026B-20TC

3.3 V industrial AS7C31026B-10TI AS7C31026B-12TI AS7C31026B-15TI AS7C31026B-20TI

AS7C31026B-10JCN)

Device

number

Access

time

Package:

J = SOJ 400 mil

T = TSOP 2, 10.2 x 18.4 mm

Temperature range:

C = commercial: 0° C to 70° C

I = industrial: -40° C to 85° C

N=Lead Free

Part

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Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Te l: 408 - 855 - 4900

Fax: 408 - 855 - 4999 www.alsc.com

trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.