Page 1
March 2004
3.3V 128K X 8 CMOS SRAM (Center power and ground)
Features
• Industrial and commercial temperatures
• Organization: 131,072 x 8 bits
• High speed
- 10/12/15/20 ns address access time
- 5, 6, 7, 8 ns output enable access time
• Low power consumption: ACTIVE
- 252 mW / max @ 10 ns
• Low power consumption: STANDBY
- 18 mW / max CMOS
• 6 T 0.18 u CMOS technology
Logic block diagram
V
CC
GND
Input buffer
A0
A1
A2
A3
A4
A5
A6
A7
A8
512 x 256 x 8
Array
(1,048,576)
Row decoder
Column decoder
Sense amp
Control
circuit
WE
OE
CE
I/O7
I/O0
AS7C31025B
®
• Easy memory expansion with
• Center power and ground
• TTL/LVTTL-compatible, three-state I/O
• JEDEC-standard packages
- 32-pin, 300 mil SOJ
- 32-pin, 400 mil SOJ
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Pin arrangement
32-pin SOJ (300 mil)
32-pin SOJ (400 mil)
1
A0
2
A1
3
A2
4
A3
5
CE
WE
6
7
8
CC
9
10
11
12
13
A4
14
A5
15
A6
16
A7
I/O0
I/O1
V
GND
I/O2
I/O3
CE, OE
A16
32
A15
31
A14
30
A13
29
28
OE
I/O7
27
26
I/O6
25
GND
V
24
CC
23
I/O5
AS7C31025B
22
I/O4
21
A12
A11
20
19
A10
A9
18
17
A8
inputs
A9
A1 1
A10
A12
A13
A14
A15
A16
Selection guide
-10 -12 -15 -20 Unit
Maximum address access time 10 12 15 20 ns
Maximum output enable access time 5678ns
Maximum operating current 70 65 60 55 mA
Maximum CMOS standby current 5555mA
3/24/04, v. 1.3 Alliance Semiconductor P. 1 of 9
Copyright © Alliance Semiconductor. All rights reserved.
Page 2
AS7C31025B
®
Functional description
The AS7C31025B is a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 131,072 x 8
bits. It is designed for memory applications where fast data access, low power, and simple interfa cing are desired.
Equal address access and cycle times (t
high-performance applications. The chip enable input CE permits easy memory and expansion with multiple-bank memory systems.
When CE is high the device enters standby mode. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data
on the input pins I/O0 through I/O7 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention,
external devices should drive I/O pins only after outputs have been disabled with output enable (
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chip drives I/O pins
with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output
drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible, and operation is from a single 3.3 V supply. The AS7C31025B is packaged in common
industry standard packages.
Absolute maximum ratings
Parameter Symbol Min Max Unit
Voltage on V
Voltage on any pin relative to GND V
Power dissipation P
Storage temperature (plastic) T
Ambient temperature with V
DC current into outputs (low) I
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
relative to GND V
CC
CC
, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5, 6, 7, 8 ns are ideal for
AA
OE
applied T
t1
t2
D
stg
bias
OUT
) or write enable (
–0.50 +5.0 V
–0.50 VCC + 0.5 V
–1.0W
–65 +150
–55 +125
–20mA
WE
o
o
).
C
C
Truth table
CE WE OE
H X X High Z Standby (I
L H H High Z Output disable (I
LHL D
LLX D
Key: X = don’t care, L = low, H = high.
3/24/04, v. 1.3 Alliance Semiconductor P. 2 of 9
Data Mode
SB
OUT
IN
Read (ICC)
Write (ICC)
, I
SB1
CC
)
)
Page 3
Recommended operating conditions
Parameter Symbol Min Nominal Max Unit
Supply voltage V
Input voltage
Ambient operating temperature
V
= -1.0V for pulse width less than 5ns
IL
V
+ 1.5V for pulse width less than 5ns
IH = VCC
AS7C31025B
®
CC
V
IH
V
IL
T
A
T
A
3.0 3.3 3.6 V
2.0 – VCC + 0.5 V
–0.5 – 0.8 V
0–70o C
–40 – 85
o
C
DC operating characteristics (over the operating range)
-10 -12 -15 -20
Parameter Sym Test conditions
Input leakage
current
Output leakage
current
Operating power
supply current
Standby power
supply current
Output voltage
Capacitance (f = 1 MHz, T
Input capacitance C
I/O capacitance C
| I
|
VCC = Max, VIN = GND to V
LI
| I
|
LO
VCC = Max, CE = VIH,
V
= GND to V
out
CC
–1–1–1–1µA
CC
–1–1–1–1µA
VCC = Max
I
CC
CE
≤ VIL, f = f
I
OUT
= 0 mA
Max
,
–70–65–60–55
VCC = Max
I
SB
1
I
V
SB1
CE
≥ VIH, f = f
Max
VCC = Max, CE ≥ VCC–0.2 V,
≤ 0.2 V or VIN ≥ VCC –0.2 V,
IN
–30–25–20–20
– 5 – 5 – 5 – 5
f = 0
V
OL
V
OH
IOL = 8 mA, VCC = Min
IOH = –4 mA, VCC = Min
= 25o C, VCC = NOMINAL)
a
–0.4–0.4–0.4–0.4V
2.4–2.4–2.4–2.4– V
2
Parameter Symbol Signals Test conditions Max Unit
IN
I/O
A, CE, WE,
I/O VIN = V
1
OE
VIN = 0 V 5 pF
= 0 V 7 pF
OUT
UnitMin Max Min Max Min Max Min Max
mA
mA
mA
3/24/04, v. 1.3 Alliance Semiconductor P. 3 of 9
Page 4
AS7C31025B
®
Read cycle (over the operating range)
Parameter Symbol
Read cycle time t
Address access time t
Chip enable (
Output enable (
CE
) access time t
OE
) access time t
Output hold from address change t
CE
low to output in low Z t
CE
high to output in high Z t
OE
low to output in low Z t
OE
high to output in high Z t
Power up time t
Power down time t
RC
AA
ACE
OE
OH
CLZ
CHZ
OLZ
OHZ
PU
PD
Key to switching waveforms
Read waveform 1 (address controlled)
Address
D
OUT
t
AA
3,9
-10 -12 -15 -20
Unit NotesMin Max Min Max Min Max Min Max
10 – 12 – 15 – 20 – ns
–10–12–15–20ns 3
–10–12–15–20ns 3
–5–6–7–8ns
3–3–3–3–ns 5
3–3–3–3–ns4, 5
–3–3–4–5ns4, 5
0–0–0–0–ns4, 5
–5–6–7–8ns4, 5
0–0–0–0–ns4, 5
– 10 – 12 – 15 – 20 ns 4, 5
Undefined/don’t careFalling inputRising input
3,6,7,9
t
RC
t
OH
Data valid
Read waveform 2 (CE and OE controlled)
t
CE
OE
t
t
t
PU
ACE
CLZ
D
OUT
Supply
current
3/24/04, v. 1.3 Alliance Semiconductor P. 4 of 9
RC1
t
OE
t
OLZ
50% 50%
3,6,8,9
Data valid
t
OHZ
t
CHZ
t
PD
I
CC
I
SB
Page 5
AS7C31025B
®
Write cycle (over the operating range)
Parameter Symbol
Write cycle time t
Chip enable (
CE
) to write end t
Address setup to write end t
Address setup time t
Write pulse width t
Write recovery time t
Address hold from end of write t
Data valid to write end t
Data hold time t
Write enable to output in high Z t
Output active from write end t
Write waveform 1 (WE controlled)
Address
WE
t
AS
D
IN
D
OUT
WC
CW
AW
AS
WP
WR
AH
DW
DH
WZ
OW
10,11
t
WZ
11
-10 -12 -15 -20
Unit NotesMin Max Min Max Min Max Min Max
10–12–15–20– ns
8 – 9 –10–12– ns
8 – 9 –10–12– ns
0–0–0–0– ns
7–8–9–12– ns
0–0–0–0– ns
0–0–0–0– ns
5–6–8–10– ns
0–0–0–0– ns 4, 5
–5–6–7–8 ns 4, 5
1–1–1–1– ns 4, 5
t
t
AW
WC
t
WP
t
DW
Data valid
t
OW
t
t
t
WR
AH
DH
Write waveform 2 (CE controlled)
10,11
t
AW
t
WC
t
t
AH
WR
Address
t
AS
t
CW
CE
t
WP
t
DW
Data valid
t
DH
D
WE
D
OUT
t
WZ
IN
3/24/04, v. 1.3 Alliance Semiconductor P. 5 of 9
Page 6
®
AC test conditions
– Output load: see Figure B.
– Input pulse level: GND to 3.0 V. See Figure A.
– Input rise and fall times: 2 ns. See Figure A.
– Input and output timing reference levels: 1.5 V.
+3.0 V
GND
90%
10%
2 ns
Figure A: Input pulse
90%
10%
Thevenin equivalent:
168
D
D
OUT
OUT
255
Ω
Ω
Figure B: 3.3 V Output load
Notes
1 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.
2 This parameter is sampled, but not 100% tested.
3 For test conditions, see AC Test Conditions, Figures A and B.
4t
and t
CLZ
5 This parameter is guaranteed, but not 100% tested.
6
WE
is high for read cycle.
CE
and OE are low for read cycle.
7
8 Address is valid prior to or coincident with
9 All read cycle timings are referenced from the last valid address to the first transitioning address.
10 N/A
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 N/A.
13 C = 30 pF, except all high Z and low Z parameters where C = 5 pF.
are specified with CL = 5 pF, as in Figure B. Transition is measured ±500 mV from steady-state voltage.
CHZ
CE
transition low.
+1.728 V
+3.3 V
320
Ω
13
C
GND
AS7C31025B
3/24/04, v. 1.3 Alliance Semiconductor P. 6 of 9
Page 7
Package dimensions
32-pin SOJ
300 mil/400 mil
D
e
E1
AS7C31025B
®
E2
Pin 1
A1
c
A2
E
32-pin SOJ
32-pin SOJ
300 mil
Symbol
Min Max Min Max
A 0.128 0.145 0.132 0.146
A1 0.025 - 0.025 -
A2 0.095 0.105 0.105 0.115
B 0.026 0.032 0.026 0.032
b 0.016 0.020 0.015 0.020
c 0.007 0.010 0.007 0.013
D 0.820 0.830 0.820 0.830
E 0.255 0.275 0.354 0.378
E1 0.295 0.305 0.395 0.405
E2 0.330 0.340 0.435 0.445
e
0.050 BSC 0.050 BSC
400 mil
B
A
b
Seating
plane
3/24/04, v. 1.3 Alliance Semiconductor P. 7 of 9
Page 8
AS7C31025B
®
Ordering Codes
Package \
Access time
300-mil SOJ
400-mil SOJ
Note:
Add suffix ‘N’ to the above part number for lead free parts (Ex.
Part numbering system
AS7C X 1025B –XX X X X
SRAM
prefix
Voltage:
3 = 3.3 V
CMOS
Temperature 10 ns 12 ns 15 ns 20 ns
Commercial AS7C31025B-10TJC AS7C31025B-12TJC AS7C31025B-15TJC AS7C31025B-20TJC
Industrial AS7C31025B-10TJI AS7C31025B-12TJI AS7C31025B-15TJI AS7C31025B-20TJI
Commercial AS7C31025B-10JC AS7C31025B-12JC AS7C31025B-15JC AS7C31025B-20JC
Industrial AS7C31025B-10JI AS7C31025B-12JI AS7C31025B-15JI AS7C31025B-0JI
AS7C31025B-10TJCN)
Device
number
Access
time
Package:
TJ = SOJ 300 mil
J = SOJ 400 mil
Temperature range
C = commercial, 0° C to 70° C
I = industrial, -40° C to 85° C
N=Lead Free Part
3/24/04, v. 1.3 Alliance Semiconductor P. 8 of 9
Page 9
AS7C31025B
®
®
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Te l: 408 - 855 - 4900
Copyright © Alliance Semiconductor
All Rights Reserved
Part Number: AS7C31025B
Document Version: v. 1.3
Fax: 408 - 855 - 4999
www.alsc.com
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered
trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make
changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document.
The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this
data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The
information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate
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