Datasheet AS7C31025A-12TC, AS7C31025A-12JIC, AS7C31025A-12JC, AS7C31025A-10TJI, AS7C31025A-10TJC Datasheet (Alliance Semiconductor Corporation)

January 2001
Advance Information

Copyright © Alliance Semiconductor. All rights reserved.

®

AS7C1025A

AS7C31025A

5V/3.3V 128K X 8 CMOS SRAM (Revolutionary pinout)

2/6/01; V.0.9 Alliance Semiconductor P. 1 of 8

Features

• AS7C1025A (5V version)

• AS7C31025A (3.3V version)

• Industrial and commercial temperatures

• Organization: 131,072 x 8 bits

•High speed

- 10/10/12/15/20 ns address access time

- 3/3/4/5 ns output enable access time

• Low power consumption: ACTIVE

- 660 mW (AS7C1025A) / max @ 10 ns (5V)

- 324 mW (AS7C31025A) / max @ 10 ns (3.3V)

• Low power consumption: STANDBY

- 55 mW (AS7C1025A) / max CMOS (5V)

- 36 mW (AS7C31025A) / max CMOS (3.3V)

• Latest 6T 0.25u CMOS technology

• 2.0V data retention

• Easy memory expansion with

CE, OE

inputs

• Center power and ground

• TTL/LVTTL-compatible, three-state I/O

• JEDEC-standard packages

- 32-pin, 300 mil SOJ

- 32-pin, 400 mil SOJ

- 32-pin, TSOP II

• ESD protection ≥ 2000 volts

• Latch-up current ≥ 200 mA

Logic block diagram

512×256×8

Array

(1,048,576)

Sense amp

Input buffer

A10

A11

A12

A13

A14

A15

A16

I/O0

I/O7

OE
CE

WE

Column decoder

Row decoder

Control

circuit

A9

A0
A1
A2
A3
A4
A5
A6
A7

V

CC

GND

A8

Pin arrangement

1
2
3
4
5
6
7
8

9
10

11
12
13
14
15

16

32
31
30

29
28
27
26
25
24
23
22
21
20
19

18
17

A16

A15
A14
A13
OE
I/O7
I/O6
GND

V

CC

I/O5
I/O4
A12
A11
A10
A9

A8

A0
A1
A2
A3

CE
I/O0
I/O1

V

CC

GND
I/O2

I/O3

WE

A4

A5

A6

A7

AS7C1025A

AS7C31025A

32-pin SOJ (300 mil)
32-pin SOJ (400 mil)

1
2

3
4

5
6

7
8
9

10
11
12

13
14
15
16

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

A0
A1

A2
A3

CE
I/O0
I/O1

V

CC

GND
I/O2
I/O3

WE

A16

A15
A14
A13

OE
I/O7
I/O6
GND

V

CC

I/O5
I/O4

A9

A8

A4
A5
A6
A7

A12
A11
A10

32-pin TSOP II

AS7C1025A

AS7C31025A

Selection guide

AS7C1025A-10

AS7C31025A-10

AS7C1025A-12

AS7C31025A-12

AS7C1025A-15

AS7C31025A-15

AS7C1025A-20

AS7C31025A-20 Unit

Maximum address access time 10 12 15 20 ns

Maximum output enable access
time

33 4 5ns

Maximum
operating
current

AS7C1025A 120 110 100 100 mA

AS7C31025A 90 80 80 80 mA

Maximum
CMOS standby
current

AS7C1025A 10 10 10 15 mA

AS7C31025A 10 10 10 15 mA

®

AS7C1025A

AS7C31025A

2/6/01; V.0.9 Alliance Semiconductor P. 2 of 8

Functional description

The AS7C1025A and AS7C31025A are high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices organized as
131,072 x 8 bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired.

Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 3/3/4/5 ns are ideal for
high-performance applications. The chip enable input CE

permits easy memory and expansion with multiple-bank memory systems.

When

CE

is high the devices enter standby mode. The standard AS7C1025A is guaranteed not to exceed 55 mW power consumption in

standby mode. Both devices also offer 2.0V data retention.

A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0-I/O7 is written on the rising
edge of

WE

(write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been

disabled with

output enable (OE) or write enable

(WE).

A read cycle is accomplished by asserting output enable (

OE

) and chip enable (CE), with write enable (WE) high. The chips drive I/O pins
with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output
drivers stay in high-impedance mode.

All chip inputs and outputs are TTL-compatible, and operation is from a single 5V supply (AS7C1025A) or 3.3V supply (AS7C31025A). The
AS7C1025A and AS7C31025A are packaged in common industry standard packages.

Absolute maximum ratings

NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional oper-
ation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.

Truth table

Key: X = Don’t Care, L = Low, H = High

Parameter Device Symbol Min Max Unit

Vo l t a ge o n V

CC

relative to GND

AS7C1025A V

t1

–0.50 +7.0 V

AS7C31025A V

t1

–0.50 +5.0 V

Voltage on any pin relative to GND V

t2

–0.50 VCC + 0.5 V

Power dissipation P

D

–1.0W

Storage temperature (plastic) T

stg

–65 +150

o

C

Ambient temperature with V

CC

applied T

bias

–55 +125

o

C

DC current into outputs (low) I

OUT

–20mA

CE

WE OE Data Mode

H X X High Z Standby (I

SB

, I

SB1

)

L H H High Z Output disable (I

CC

)

LHL D

OUT

Read (ICC)

LLX D

IN

Write (ICC)

®

AS7C1025A

AS7C31025A

2/6/01; V.0.9 Alliance Semiconductor P. 3 of 8

Recommended operating conditions

†

VIL min. = –3.0V for pulse width less than tRC/2.

DC operating characteristics (over the operating range)1

Capacitance (

f = 1 MHz, Ta = 25 oC, VCC = NOMINAL

)2

Parameter Device Symbol Min Nominal Max Unit

Supply voltage

AS7C1025A V

CC

4.5 5.0 5.5 V

AS7C31025A V

CC

3.0 3.3 3.6 V

Input voltage

AS7C1025A V

IH

2.2 – VCC + 0.5 V

AS7C31025A V

IH

2.0 – VCC + 0.5 V

Both V

IL

†

–0.5 – 0.8 V

Ambient operating temperature

commercial T

A

0–70oC

industrial T

A

–40 – 85

o

C

Parameter Sym Test conditions Device

-10 -12 -15 -20

UnitMin Max Min Max Min Max Min Max

Input
leakage
current

| I

LI

| V

CC

= Max, VIN = GND to V

CC

Both – 1 – 1 – 1 – 1 µA

Output
leakage
current

| I

LO

|

VCC = Max, CE = VIH, V

out

= GND

to V

CC

Both – 1 – 1 – 1 – 1 µA

Operating
power
supply
current

I

CC

CE = VIL, f = f

Max, IOUT

= 0 mA

AS7C1025A – 120 – 110 – 100 – 100

mA

AS7C31025A – 90 – 80 – 80 – 80

Standby
power
supply
current

1

I

SB

CE = VIH, f = f

Max

, f

OUT

= 0

AS7C1025A – 30 – 25 – 20 – 20

mA

AS7C31025A – 30 – 25 – 20 – 20

I

SB1

CE

≥ V

CC

–0.2V, V

IN

≤ 0.2V or V

IN

≥ V

CC

–0.2V, f = 0, f

OUT

= 0

AS7C1025A – 10 – 10 – 10 – 15

mA

AS7C31025A – 10 – 10 – 10 – 15

Output
voltage

V

OL

IOL = 8 mA, VCC = Min AS7C1025A – .04 – 0.4 – 0.4 – 0.4 V

V

OH

IOH = –4 mA, VCC = Min AS7C31025A 2.4 2.4 – 2.4 – 2.4 – V

Data
retention
current

I

CCDR

VCC = 2.0V

CE

≥ V

CC

– 0.2V

V

IN

≥ V

CC

– 0.2V or

V

IN

≤ 0.2V

AS7C1025A – 1 – 1 – 1 5

mA

AS7C31025A – 1 – 1 – 1 – 5 mA

Parameter Symbol Signals Test conditions Max Unit

Input capacitance C

IN

A, CE, WE,

OE

VIN = 0V 5 pF

I/O capacitance C

I/O

I/O VIN = V

OUT

= 0V 7 pF

®

AS7C1025A

AS7C31025A

2/6/01; V.0.9 Alliance Semiconductor P. 4 of 8

Read cycle (over the operating range)

3,9

Key to switching waveforms

Read waveform 1 (address controlled)

3,6,7,9

Read waveform 2 (CE and OE controlled)

3,6,8,9

Parameter Symbol

-10 -12 -15 -20

Unit NotesMin Max Min Max Min Max Min Max

Read cycle time t

RC

10 – 12 – 15 – 20 – ns

Address access time t

AA

– 10 – 12 – 15 – 20 ns 3

Chip enable (

CE

) access time t

ACE

– 10 – 12 – 15 – 20 ns 3

Output enable (

OE

) access time t

OE

–3– 3–4 – 5 ns

Output hold from address change t

OH

2–3 –3– 3 – ns 5

CE

Low t

o output in low Z t

CLZ

0–0 –0– 0 – ns 4, 5

CE

Low to output in high Z t

CHZ

–3– 3–4 – 5 ns 4, 5

OE

Low to output in low Z t

OLZ

0–0 –0– 0 – ns 4, 5

OE

High to output in high Z t

OHZ

–3– 3–4 – 5 ns 4, 5

Power up time t

PU

0–0 –0– 0 – ns 4, 5

Power down time t

PD

– 10 – 12 – 15 – 20 ns 4, 5

Undefined/don’t careFalling inputRising input

Address

D

OUT

Data valid

t

OH

t

AA

t

RC

current

Supply

OE

D

OUT

t

OE

t

OLZ

t

ACE

t

CHZ

t

CLZ

t

PU

t

PD

I

CC

I

SB

50% 50%

Data valid

t

RC1

CE

t

OHZ

®

AS7C1025A

AS7C31025A

2/6/01; V.0.9 Alliance Semiconductor P. 5 of 8

Write cycle (over the operating range)

11

Write waveform 1 (WE controlled)

10,11

Write waveform 2 (CE controlled)

10,11

Parameter Symbol

-10 -12 -15 -20

Unit NotesMin Max Min Max Min Max Min Max

Write cycle time t

WC

10 12 – 15 – 20 – ns

Chip enable (

CE

) to write end t

CW

8 10 – 12 – 12 – ns

Address setup to write end t

AW

89–10–12–ns

Address setup time t

AS

00–0–0–ns

Write pulse width t

WP

78–9–12–ns

Address hold from end of write t

AH

00–0–0–ns

Data valid to write end t

DW

56–8–10–ns

Data hold time t

DH

00–0–0–ns4, 5

Write enable to output in high Z t

WZ

6– 6–6 – 8 ns 4, 5

Output active from write end t

OW

11–1–2–ns4, 5

t

AW

t

AH

t

WC

Address

WE

D

OUT

t

DH

t

OW

t

DW

t

WZ

t

WP

t

AS

Data valid

D

IN

t

AW

Address

CE

WE

D

OUT

t

CW

t

WP

t

DW

t

DH

t

AH

t

WZ

t

WC

t

AS

Data valid

D

IN

®

AS7C1025A

AS7C31025A

2/6/01; V.0.9 Alliance Semiconductor P. 6 of 8

Data retention characteristics (over the operating range)

Data retention waveform

AC test conditions

Notes

1During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.

2 This parameter is sampled, but not 100% tested.

3 For test conditions, see AC Test Conditions, Figures A, B, and C.

4t

CLZ

and t

CHZ

are specified with CL = 5pF, as in Figure C. Transition is measured ±500mV from steady-state voltage.

5 This parameter is guaranteed, but not 100% tested.

6WE

is High for read cycle.

7CE

and OE are Low for read cycle.

8 Address valid prior to or coincident with CE

transition Low.

9 All read cycle timings are referenced from the last valid address to the first transitioning address.

10 CE

or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle.

11 All write cycle timings are referenced from the last valid address to the first transitioning address.

12 NA.

13 C=30pF, except all high Z and low Z parameters, where C=5pF.

Parameter Symbol Test conditions Min Max Unit

V

CC

for data retention V

DR

VCC = 2.0V

CE

≥ V

CC

– 0.2V

V

IN

≥ V

CC

– 0.2V or

V

IN

≤ 0.2V

2.0 – V

Data retention current I

CCDR

– 500 µA

Chip enable to data retention time t

CDR

0–ns

Operation recovery time t

R

t

RC

–ns

Input leakage current | I

LI

| –1µA

V

CC

CE

t

R

t

CDR

Data retention mode

V

CC

V

CC

VDR ≥ 2.0V

V

IH

V

IH

V

DR

255W

– Output load: see Figure B or Figure C.

– Input pulse level: GND to 3.0V. See Figure A.

– Input rise and fall times: 2 ns. See Figure A.

– Input and output timing reference levels: 1.5V.

C(14)

320W

D

OUT

GND

+3.3V

168W

Thevenin equivalent:

D

OUT

+1.728V (5V and 3.3V)

Figure C: 3.3V Output load

255W

C(14)

480W

D

OUT

GND

+5V

Figure B: 5V Output load

10%

90%

10%

90%

GND

+3.0V

Figure A: Input pulse

2 ns

®

AS7C1025A

AS7C31025A

2/6/01; V.0.9 Alliance Semiconductor P. 7 of 8

Package dimensions

Symbol

32-pin TSOP II (mm)

Min Max

A –1.2

A1 0.05 0.15

b 0.3 0.52

C 0.12 0.21

D 20.82 21.08

E1 10.03 10.29

E 11.56 11.96

e 1.27 BSC

L 0.40 0.60

ZD 0.95 REF.

α 0° 5°

32-pin TSOP II

NN/2+1

1N/2

D

E1

E

L

α

c

ZD

c

b

A1

A

Seating plane

e

D

E1

Pin 1

b

B

A1

A2

c

E

Seating

Plane

E2

A

32-pin SOJ
300 mil/400 mil

Symbol

32-pin SOJ

300 mil

32-pin SOJ

400 mil

Min Max Min Max

A -0.145-0.145

A1 0.025 - 0.025 -

A2 0.086 0.105 0.086 0.115

B 0.026 0.032 0.026 0.032

b 0.014 0.020 0.015 0.020

c 0.006 0.013 0.007 0.013

D 0.820 0.830 0.820 0.830

E 0.250 0.275 0.360 0.380

E1 0.292 0.305 0.395 0.405

E2 0.330 0.340 0.435 0.445

e

0.050 BSC 0.050 BSC

®

AS7C1025A

AS7C31025A

© Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered tr ademarks of A lliance . A ll oth er b ran d an d
product names may be the trademarks of their respective companies. Alliance reserves the right to m ak e ch an ges to th is d ocu m e nt an d its p rod u cts at a ny tim e with ou t notic e. Allia nce assum es no
responsibility for any errors that may app ear in th is doc um e nt. T h e d ata c ontain ed h ere in re pr esent s Allian ce ’s best data a nd /or e stim ate s at the ti me of issuan ce. Al lianc e reser ves the righ t to
change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specificatio ns a re p ossible. T he info rm a tion in this
product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or
customer. A llian ce d oe s no t assum e any respo n sibility or liability arisi ng o ut o f th e ap plic ation or use o f any product described herein, and disclaims any express or implied warranties related to
the sale and/or use o f A llianc e pr o duc ts inclu din g liab ility o r w arra ntie s related to fitn ess fo r a p articu lar p urp ose, m erc han tabi lity , or infrin ge me n t of a ny int ellectua l pr op erty righ ts, ex cep t as
express agreed to in A llian ce’s T erm s an d C on ditio n s of Sale (which are av ailable from Alliance). Al l sales of A lliance pr odu cts are m ade ex clusively acc ord ing to A llian ce’s T erm s an d
Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights
of Alliance o r third pa rties. A llian ce doe s no t au thoriz e its pr oducts for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result
in significant inju ry to the u ser, a nd the in clu sion o f A llia nce pro d ucts in such lif e- supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance
against all claims arising from such use.

2/6/01; V.0.9 Alliance Semiconductor P. 8 of 8

Ordering codes

Part numbering system

Package \

Access time Voltage Temperature 10 ns 12 ns 15 ns 20 ns

TSOP II

5V

Commercial AS7C1025A-10TC AS7C1025A-12TC AS7C1025A-15TC AS7C1025A-20TC

Industrial AS7C1025A-10TI AS7C1025A-12TI AS7C1025A-15TI AS7C1025A-20TI

3.3V

Commercial AS7C31025A-10TC AS7C31025A-12TC AS7C31025A-15TC AS7C31025A-20TC

Industrial AS7C31025A-10TI AS7C31025A-12TI AS7C31025A-15TI AS7C31025A-20TI

300-mil SOJ

5V

Commercial AS7C1025A-10TJC AS7C1025A-12TJC AS7C1025A-15TJC AS7C1025A-20TJC

Industrial AS7C1025A-10TJI AS7C1025A-12TJI AS7C1025A-15TJI AS7C1025A-20TJI

3.3V

Commercial AS7C31025A-10TJC AS7C31025A-12TJC AS7C31025A-15TJC AS7C31025A-20TJC

Industrial AS7C31025A-10TJI AS7C31025A-12TJI AS7C31025A-15TJI AS7C31025A-20TJI

400-mil SOJ

5V

Commercial AS7C1025A-10JC AS7C1025A-12JC AS7C1025A-15JC AS7C1025A-20JC

Industrial AS7C1025A-10JI AS7C1025A-12JI AS7C1025A-15JI AS7C1025A-20JI

3.3V

Commercial AS7C31025A-10JC AS7C31025A-12JC AS7C31025A-15JC AS7C31025A-20JC

Industrial AS7C31025A-10JI AS7C31025A-12JI AS7C31025A-15JI AS7C31025A-20JI

AS7C X 1025 –XX X X

SRAM
prefix

Blank=5V CMOS

3=3.3V CMOS

Device

number

Access

time

Package:

T = TSOP II

J = SOJ

Temperature range

C = Commercial, 0°C to 70°C

I = Industrial, -40°C to 85°C