Datasheet AS7C31025-15JC, AS7C31025-12TJI, AS7C31025-12TJC, AS7C31025-12TI, AS7C31025-12TC Datasheet (Alliance Semiconductor Corporation)

March 2001

5V/3.3V 128Kx8 CMOS SRAM (Revolutionary pinout)

Features

• AS7C1025 (5V version)

• AS7C31025 (3.3V version)

• Industrial and commercial temperatures

• Organization: 131,072 words × 8 bits

• High speed

- 12/15/20 ns address access time

- 6,7,8 ns output enable access time

• Low power consumption: ACTIVE

- 715 mW (AS7C1025) / max @ 12 ns (5V)

- 360 mW (AS7C31025) / max @ 12 ns (3.3V)

Logic block diagram

V

CC

GND

Input buffer

A0
A1
A2
A3
A4
A5
A6
A7
A8

Row decoder

512×256×8

Array

(1,048,576)

Sense amp

I/O7

I/O0

®

• Low power consumption: STANDBY

- 27.5 mW (AS7C1025) / max CMOS (5V)

- 1.8 mW (AS7C31025) / max CMOS (3.3V)

• 2.0V data retention

• Easy memory expansion with CE

, OE inputs

• Center power and ground

• TTL/LVTTL-compatible, three-state I/O

• JEDEC-standard packages

- 32-pin, 300 mil SOJ

- 32-pin, 400 mil SOJ

- 32-pin TSOP II

• ESD protection ≥ 2000 volts

• Latch-up current ≥ 200 mA

Pin arrangement

32-pin TSOP II

A0
A1

A2
A3

CE
I/O0
I/O1

V
GND
I/O2
I/O3

WE

A4
A5
A6
A7

1
2

3
4

5
6
7
8

CC

9

10
11
12

13
14
15
16

32

A16

31

A15

30

A14

29

A13

28

OE

27

I/O7

26

I/O6

25

GND

24

V

CC

23

I/O5

22

I/O4

AS7C1025

AS7C31025

21

A12

20

A11

19

A10

18

A9

17

A8

AS7C1025

AS7C31025

32-pin SOJ (300 mil)

32-pin SOJ (400 mil)

1

A0

2

A1

3

A2

4

A3

5

CE

V

WE

6
7

8

CC

9
10

AS7C1025

11
12
13

A4

14

A5

15

A6

16

A7

I/O0
I/O1

GND
I/O2

I/O3

A16

32

A15

31

A14

30

A13

29
28

OE
I/O7

27
26

I/O6

25

GND
V

24

CC

23

I/O5

AS7C31025

22

I/O4

21

A12
A11

20
19

A10
A9

18
17

A8

Column decoder

A9

A10

A11

A12

A13

A14

Control

circuit

A15

A16

WE

OE
CE

Selection guide

AS7C1025-12

AS7C31025-12

Maximum address access time 12 15 20 ns

Maximum output enable access time 3 4 5 ns

Maximum operating current

AS7C1025 130 85 80 mA

AS7C31025 100 85 80 mA

AS7C1025 5 5 5 mA

Maximum CMOS standby current

AS7C31025 5 5 5 mA

Shaded areas contain advance information.

AS7C1025-15

AS7C31025-15

AS7C1025-20

AS7C31025-20 Unit

3/23/01; v.1.0 Alliance Semiconductor P. 1 of 9

Copyright © Alliance Semiconductor. All rights reserved.

AS7C1025

AS7C31025

®

Functional description

The AS7C1025 and AS7C31025 are high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices
organized as 131,072 words × 8 bits. They are designed for memory applications where fast data access, low power, and
simple interfacing are desired.

Equal address access and cycle times (t
for high-performance applications. The chip enable input CE
memory systems.

When

is high the devices enter standby mode. The standard AS7C1025 is guaranteed not to exceed 27.5 mW power

CE

consumption in standby mode, and typically requires only 5 mW. Both devices also offer 2.0V data retention.

A write cycle is accomplished by asserting write enable (

(write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive

written on the rising edge of

WE

I/O pins only after outputs have been disabled with

A read cycle is accomplished by asserting output enable (
drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or
write enable is active, output drivers stay in high-impedance mode.

All chip inputs and outputs are TTL-compatible, and operation is from a single 5V supply (AS7C1025) or 3.3V supply
(AS7C31025). The AS7C1025 and AS7C31025 are packaged in common industry standard packages.

, tRC, tWC) of 12/15/20 ns with output enable access times (tOE) of 6,7,8 ns are ideal

AA

permits easy memory and expansion with multiple-bank

) and chip enable (CE). Data on the input pins I/O0-I/O7 is

WE

output enable (OE) or write enable (

) and chip enable (CE), with write enable (WE) high. The chips

OE

WE

).

Absolute maximum ratings

Parameter Device Symbol Min Max Unit

Vo l t a g e o n V

relative to GND

CC

AS7C31025 V

Voltage on any pin relative to GND V

Power dissipation P

Storage temperature (plastic) T

AS7C1025 V

Ambient temperature with V

applied T

CC

DC current into outputs (low) I

NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.

t1

t1

t2

D

stg

bias

OUT

–0.50 +7.0 V

–0.50 +5.0 V

–0.50 VCC + 0.5 V

–1.0W

–65 +150

–55 +125

o

C

o

C

–20mA

Truth table

CE WE OE

H X X High Z Standby (I

L H H High Z Output disable (I

LHL D

LLX D

Key: X = Don’t Care, L = Low, H = High

Data Mode

OUT

IN

Read (ICC)

Write (ICC)

, I

)

SB

SB1

)

CC

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Recommended operating conditions

Parameter Device Symbol Min Nominal Max Unit

Supply voltage

AS7C1025 V

AS7C31025 V

AS7C1025 V

Input voltage

AS7C31025 V

commercial T

Ambient operating temperature

industrial T

†

VIL min = –3.0V for pulse width less than tRC/2.

DC operating characteristics (over the operating range)1

Parameter Sym Test conditions Device

Input leakage
current

| I

LI

Output
leakage

| I

LO

current

Operating
power supply

I

CC

current

I

Standby

SB

power supply

1

current

Output
voltage

Shaded areas contain advance information.

I

SB1

V

OL

V

OH

= Max, VIN = GND to V

| V

CC

V

= Max, CE = VIH, V

CC

|

GND to V

CC

out

CC

=

AS7C1025 – 130 – 120 – 110

CE = VIL, f = f

Max, IOUT

= 0 mA

AS7C31025 – 100 – 85 – 80

AS7C1025 – 50 – 40 – 40

CE = VIH, f = f

CE

V

IN

≥ V

≥ V

CC

CC

–0.2V, V

–0.2V, f = 0, f

, f

Max

≤ 0.2V or

IN

OUT

= 0

OUT

AS7C31025 – 50 – 40 – 40

AS7C1025 – 5 – 5 – 5

= 0

AS7C31025 – 5 – 5 – 5

IOL = 8 mA, VCC = Min – 0.4 – 0.4 – 0.4 V

IOH = –4 mA, VCC = Min 2.4–2.4–2.4– V

®

AS7C31025

CC

CC

IH

IH

V

IL

A

A

-12 -15 -20

–1–1–1µA

–1–1–1µA

4.5 5.0 5.5 V

3.0 3.3 3.6 V

2.2 – VCC + 0.5 V

2.0 – VCC + 0.5 V

†

–0.5 – 0.8 V

0–70oC

–40 – 85

AS7C1025

o

C

UnitMin Max Min Max Min Max

mA

mA

mA

Capacitance (

f = 1 MHz, Ta = 25 oC, VCC = NOMINAL

)2

Parameter Symbol Signals Test conditions Max Unit

Input capacitance C

I/O capacitance C

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IN

I/O

A, CE, WE,

OE

I/O VIN = V

VIN = 0V 5 pF

= 0V 7 pF

OUT

AS7C1025

AS7C31025

®

Read cycle (over the operating range)

Parameter Symbol

Read cycle time t

Address access time t

CE

Chip enable (

Output enable (

) access time t

OE

) access time t

Output hold from address change t

CE

Low to output in low Z t

CE

Low to output in high Z t

OE

Low to output in low Z t

OE

High to output in high Z t

Power up time t

Power down time t

RC

AA

ACE

OE

OH

CLZ

CHZ

OLZ

OHZ

PU

PD

Key to switching waveforms

Read waveform 1 (address controlled)

Address

D

OUT

t

AA

3,9

3,6,7,9

t

-12 -15 -20

Unit NotesMin Max Min Max Min Max

12 – 15 – 20 – ns

–12–15–20 ns 3

–12–15–20 ns 3

–6–7–8 ns

3–3–3– ns 5

0–0–0– ns 4, 5

–3–4–5 ns 4, 5

0–0–0– ns 4, 5

–3–4–5 ns 4, 5

0–0–0– ns 4, 5

–12–15–20 ns 4, 5

Undefined/don’t careFalling inputRising input

RC

t

OH

Data valid

Read waveform 2 (CE and OE controlled)

t

CE

OE

D

OUT

Supply

current

t

ACE

t

CLZ

t

PU

RC1

t

OE

t

OLZ

50% 50%

3,6,8,9

Data valid

t

OHZ

t

CHZ

t

PD

I

CC

I

SB

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AS7C1025

AS7C31025

®

Write cycle (over the operating range)

Parameter Symbol

Write cycle time t

CE

Chip enable (

) to write end t

Address setup to write end t

Address setup time t

Write pulse width t

Address hold from end of write t

Data valid to write end t

Data hold time t

Write enable to output in high Z t

Output active from write end t

Shaded areas contain advance information.

Write waveform 1 ( WE controlled)

Address

WE

t

AS

D

IN

D

OUT

WC

CW

AW

AS

WP

AH

DW

DH

WZ

OW

10,11

11

-12 -15 -20

Unit NotesMin Max Min Max Min Max

12 – 15 – 20 – ns

8–12–12– ns

8–12–12– ns

0–0–0– ns

8–9–12– ns

0–0–0– ns

6–8–12– ns

0 – 0 – 0 – ns 4, 5

– 5 – 5 – 5 ns 4, 5

3 – 3 – 3 – ns 4, 5

t

WC

t

WZ

t

AW

t

WP

t

DW

Data valid

t

AH

t

DH

t

OW

Write waveform 2 (CE controlled)

10,11

t

WC

t

AW

t

AH

Address

t

AS

t

CW

CE

t

WP

t

DW

t

DH

Data validD

D

WE

OUT

t

WZ

IN

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AS7C1025

AS7C31025

®

Data retention characteristics (over the operating range)

Parameter Symbol Test conditions Min Max Unit

for data retention V

V

CC

Data retention current I

Chip enable to data retention time t

Operation recovery time t

Input leakage current | I

DR

CCDR

CDR

R

| –1µA

LI

V

Data retention waveform

Data retention mode

V

CC

CE

V

CC

t

CDR

V

IH

VDR ≥ 2.0V

AC test conditions

– 5V output load: see Figure B or Figure C.

– Input pulse level: GND to 3.0V. See Figure A.

– Input rise and fall times: 2 ns. See Figure A.

– Input and output timing reference levels: 1.5V.

13

VCC = 2.0V

CE

≥ V

≥ V

IN

V

IN

V

DR

+5V

– 0.2V

CC

– 0.2V or

CC

≤ 0.2V

2.0 – V

–500µA

0–ns

t

RC

V

CC

V

IH

Thevenin equivalent:

D

168W

OUT

–ns

t

R

+1.728V (5V and 3.3V)

+3.3V

D

+3.0V

GND

90%

10%

2 ns

Figure A: Input pulse

90%

10%

OUT

255W

C(14)

GND

Figure B: 5V Output load

Notes

1During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.

2 This parameter is sampled, but not 100% tested.

3 For test conditions, see AC Test Conditions, Figures A, B, and C.

4t

and t

480W

CLZ

5 This parameter is guaranteed, but not 100% tested.

6WE

7CE

and OE are Low for read cycle.

8 Address valid prior to or coincident with CE

9 All read cycle timings are referenced from the last valid address to the first transitioning address.

10 CE

or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle.

11 All write cycle timings are referenced from the last valid address to the first transitioning address.

12 NA.

13 2V data retention applies to commercial temperature operating range only.

14 C=30pF, except all high Z and low Z parameters, where C=5pF.

are specified with CL = 5pF, as in Figure C. Transition is measured ±500mV from steady-state voltage.

CHZ

is High for read cycle.

transition Low.

D

OUT

255W

C(14)

GND

Figure C: 3.3V Output load

320W

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Typical DC and AC characteristics

AS7C1025

AS7C31025

®

Normalized supply current ICC, I

vs. supply voltage V

1.4

1.2
I

SB

1.0

, I

CC

0.8

CC

0.6
I

0.4

Normalized I

SB

0.2

0.0

MIN

NOMINAL

Supply voltage (V)

Normalized access time t

vs. supply voltage V

1.5

1.4

1.3

Ta = 25° C

1.2

1.1

1.0

Normalized access time

0.9

SB

CC

Normalized supply current ICC, I

vs. ambient temperature T

1.4

1.2

SB

1.0

, I

CC

0.8

SB

a

I

CC

0.6
I

0.4

Normalized I

SB

0.2

Normalized supply current I

vs. ambient temperature T

625

25

(log scale)

SB1

VCC = VCC(NOMINAL)

5

1

0.2

Normalized I

0.04

SB1
a

0.0

MAX

–55 80

Ambient temperature (°C)

AA

CC

Normalized access time t
vs. ambient temperature T

1.5

1.4

1.3

VCC = VCC(NOMINAL)

1.2

1.1

1.0

Normalized access time

0.9

35–10

125

-55 80

35-10

125

Ambient temperature (°C)

AA

a

Normalized supply current I

vs. cycle frequency 1/tRC, 1/t

1.4

1.2
VCC = VCC(NOMINAL)

1.0
Ta = 25° C

CC

CC

WC

0.8

0.6

Normalized I

0.4

0.2

0.8

140

120

MIN

NOMINAL

Supply voltage (V)

Output source current I

vs. output voltage V

MAX

OH

OH

0.8
–55 80

35–10

Ambient temperature (°C)

Output sink current I

vs. output voltage V

140

120

OL

OL

125

0.0
075

Cycle frequency (MHz)

Typical access time change ∆t

vs. output capacitive loading

35

30

VCC = VCC(NOMINAL)VCC = VCC(NOMINAL)VCC = VCC(NOMINAL)

100

Ta = 25° C

80

60

40

20

Output source current (mA)

0

0 750

V

Output voltage (V)

100

Ta = 25° C

80

60

40

Output sink current (mA)

20

0

CC

00

V

Output voltage (V)

25

(ns)

20

AA

15

10

Change in t

5

0

CC

Capacitance (pF)

5025

500250

100

AA

1000

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Package dimensions

NN/2+1

E1

1N/2

D

ZD

E

A

®

32-pin TSOP II

Seating plane

AS7C1025

AS7C31025

32-pin TSOP II (mil)

Symbol

A–1.2

A1 0.05 0.15

b0.30.52

C 0.12 0.21

D 20.82 21.08

E1 10.03 10.29

E 11.56 11.96

e 1.27 BSC

L 0.40 0.60

ZD 0.95 REF.

α 0° 5°

Min Max

Pin 1

c

L

A1

b

α

c

32-pin SOJ

32-pin SOJ
300 mil/400 mil

D

e

E1

E2

A1

A2

E

B

b

c

Seating

Plane

Symbol

A - 0.145 - 0.145

A1 0.025 - 0.025 -

A

A2 0.086 0.105 0.086 0.115

B 0.026 0.032 0.026 0.032

b 0.014 0.020 0.015 0.020

c 0.006 0.013 0.007 0.013

D 0.820 0.830 0.820 0.830

E 0.250 0.275 0.360 0.380

300 mil

Min Max Min Max

32-pin SOJ

400 mil

E1 0.292 0.305 0.395 0.405

E2 0.330 0.340 0.435 0.445

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Ordering codes

Package \ Access time

sTSOP II

300-mil SOJ

400-mil SOJ

Part numbering system

Vo lt ag e Te m pe r a tu r e

5V

3.3V

5V

3.3V

5V

3.3V

Commercial AS7C1025-12TC AS7C1025-15TC AS7C1025-20TC

Industrial AS7C1025-12TI AS7C1025-15TI AS7C1025-20TI

Commercial AS7C31025-12TC AS7C31025-15TC AS7C31025-20TC

Industrial AS7C31025-12TI AS7C31025-15TI AS7C31025-20TI

Commercial AS7C1025-12TJC AS7C1025-15TJC AS7C1025-20TJC

Industrial AS7C1025-12TJI AS7C1025-15TJI AS7C1025-20TJI

Commercial AS7C31025-12TJC AS7C31025-15TJC AS7C31025-20TJC

Industrial AS7C31025-12TJI AS7C31025-15TJI AS7C31025-20TJI

Commercial AS7C1025-12JC AS7C1025-15JC AS7C1025-20JC

Industrial AS7C1025-12JI AS7C1025-15JI AS7C1025-20JI

Commercial AS7C31025-12JC AS7C31025-15JC AS7C31025-20JC

Industrial AS7C31025-12JI AS7C31025-15JI AS7C31025-20JI

AS7C1025

AS7C31025

®

12 ns 15 ns 20 ns

AS7C X 1025 –XX X X

SRAM
prefix

Blank=5V CMOS

3=3.3V CMOS

Device

number

Access

time

Package:

T = TSOP II

J = SOJ

Temperature range

C = Commercial, 0°C to 70°C

I = Industrial, -40°C to 85°C

3/23/01; v.1.0 Alliance Semiconductor P. 9 of 9

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