• High speed
– 10/12/15/20/25/35 ns address access time
– 3/3/4/5/6/8 ns output enable access time
• Low power consumption
– Active:660 mW max (10 ns cycle)
– Standby:11 mW max, CMOS I/O
2.75 mW max, CMOS I/O, L version
– Very low DC component in active power
• 2.0V data retention (L version)
32K×8 CMOS SRAM (Common I/O)
• Equal access and cycle times
• Easy memory expansion with CE
• TTL-compatible, thre e-sta te I/O
• 28-pin JEDEC standard packages
– 300 mil PDIP and SOJ
Socket compatible with 7C512 and 7C1024
– 330 mil SOIC
–8×13.4 TSOP
• ESD protection > 2000 volts
• Latch-up current > 200 mA
AS7C256
AS7C256L
and OE inputs
LOGIC BLOCK DIAGRAM
Vcc
GND
INPUT BUFFER
A0
A1
A2
A3
A4
A5
A6
A14
ROW DECODER
256×128×8
ARRAY
(262,144)
COLUMN DECODER
A8A
A9A10A11A12A
7
SELECTION GUIDE
PIN ARRANGEME NT
DIP, SOJ, SOIC
I/O7
SENSE AMP
CONTROL
CIRCUIT
13
WE
OE
CE
I/O0
TSOP 8×13.4
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
OEA10
A11
A9
A8
A13
WE
Vcc
A14
A12
A7
A6
A5
A4
A3A2
1
2
3
4
5
6
7
8
9
AS7C256
10
11
12
13
14
22
23
24
25
26
27
28
AS7C256
1
2
3
4
5
6
7
Vcc
28
WE
27
26
A13
25
A8
24
A9
23
A11
OE
22
A10
21
20
CE
19
I/O7
18
I/O6
17
I/O5
16
I/O4
15
I/O3
21
CE
20
I/O7
19
I/O6
18
I/O5
17
I/O4
16
I/O3
15
14
GND
13
I/O2
12
I/O1
11
I/O0
10
A0
9
8
AS7C256-02AS7C256-01
A1
7C256-10 7C256-12 7C256-15 7C256-20 7C256-25 7C256-35 Unit
Maximum Address Access Time101215202535ns
Maximum Output Enable Access Time334568ns
Maximum Operating Current1201151101009080mA
Maximum CMOS Standby Current
2.02.02.02.02.02.0mA
L0.50.50.50.50.50.5mA
ALLIANCESEMICONDUCTOR
Page 2
AS7C256
AS7C256L
FUNCTIONAL DESCRIPTION
The AS7C256 is a high performance CMOS 262,144-bit
Static Random Access Memory (SRAM) organized as
32,768 words × 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (t
, tRC, tWC) of
AA
10/12/15/20/25/35 ns with output enable access times (t
of 3/3/4/5/6/8 ns are ideal for high performance applications. A chip enable (CE
) input permits easy memory
expansion with mult iple-bank memory organizations.
When CE
is HIGH the device enters standby mode. The
standard AS7C256 is guaranteed not to exceed 11 mW
A write cycle is accomplishe d by asserti n g chip enable (CE
and write enable (WE
) LOW. Data on the input pins
I/O0-I/O7 is writt en on the r ising edge of WE
(write cycle 2). To avoid bus contention, external
or CE
devices should drive I/O pins only after outputs have been
disabled with output enable (OE
)
OE
A read cycle is accompl ished by assert ing chip enable (CE
and output enable (OE
) LOW, with write enable (WE)
) or write enable (WE).
HIGH. The chip drives I/O pins with the data word referenced by the input address. When chip enable or output
enable is HIGH, or wri te enable is LOW, output drivers stay
in high-impedance mode.
(write cycle 1)
power consumption in standby mode; the L version is guaranteed not to exceed 2.75 mW, and typically requires only
500 µW. The L version also offers 2.0V data retention, with
maximum power consumption in this mode of 300 µW.
All chip inputs and outputs are TTL-compa tible, and operation is from a single 5V supply. The AS7C256 is packaged
in all high volume industry standard packages.
ABSOLUTE MAXIMUM RATINGS
ParameterSymbolMinMaxUnit
Voltage on Any Pin Relative to G N DV
Power DissipationP
Storage Temperature (Plastic)T
Temperatur e Under BiasT
DC Output CurrentI
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress
rating only and functional operatio n of the device at these or any other conditions outside those indicated in the operationa l sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
.
t
D
stg
bias
out
–0.5+7.0V
–1.0W
–55+150
–10 +85
–20mA
o
C
o
C
)
)
TRUT H TABLE
CE
HXXHigh ZStandby (I
LHHHigh ZOutput Disable
LHLD
LLXD
Key: X = Don’t Care, L = LOW, H = HIGH
WEOEDataMode
out
in
Read
Write
SB
, I
)
SB1
2
Page 3
AS7C256
AS7C256L
RECOMMEND ED OPER ATING C ONDITI ONS(Ta = 0°C to +70°C)
ParameterSymbolMinTypMaxUnit
Supply Voltage
Input Voltage
min = –3.0V for pulse width less than tRC/2.
*V
IL
DC OPERATING CHARACTERISTICS
ParameterSymbol Test Conditions
Input Leakage
Current
Output Leakage
Current
Operating Power
Supply Current
Standby
Power Supply
Current
Output Voltage
|ILI|
|ILO|
I
CC
I
SB
I
SB1
V
V
VCC = Max,
V
= GND to V
in
CE = VIH, VCC = Max,
V
= GND to V
out
CE = VIL, f = f
I
= 0 mA
out
CE = VIH, f = f
CE > VCC–0.2V, f = 0,
V
≤ 0.2V or
in
V
≥ V
CC
–0.2V
in
IOL = 8 mA, VCC = Min–0.4–0.4–0.4–0.4–0.4–0.4V
OL
IOH = –4 mA, VCC = Min2.4–2.4–2.4–2.4–2.4–2.4–V
OH
CC
max,
max
1
CC
V
CC
4.55.05.5V
GND0.00.00.0V
V
IH
V
IL
2.2–VCC+1V
–0.5*–0.8V
(VCC = 5V±10% , GND = 0V, Ta = 0°C to +70°C)
-10-12-15-20-25-35
UnitMin Max Min Max Min Max Min Max Min Max Min Max
Unit NotesMin Max Min Max Min Max Min Max Min Max Min Max
Address
t
AA
D
out
t
RC
3, 6, 8, 9
1
TIMING WAVEFORM OF READ CYCLE 2(CE Controlled)
Data Valid
t
OH
CE
t
OE
OE
D
out
Supply
Current
t
t
CLZ
PU
t
ACE
t
OLZ
Data Valid
50%50%
t
OHZ
t
CHZ
t
PD
I
CC
I
SB
AS7C256-04
4
Page 5
AS7C256
AAAA
AAAA
AAAA
AAAA
AA
AA
AA
AA
t
AW
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AA
AA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAA
AAA
AAA
Address
CE
WE
D
in
D
out
Data Valid
t
CW
t
WP
t
DW
t
DH
t
AH
t
WZ
t
WC
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAA
AAA
AAA
t
AS
AS7C256-06
AS7C256L
WRITE CYC LE(VCC = 5V±10% , GND = 0V, Ta = 0°C to +70°C)
11
-10-12-15-20-25-35
ParameterSymbol
Write Cycle Timet
Chip Enable to Write En dt
Address Setup to Write Endt
Address Setup Timet
Write Pulse Widtht
Address Hold From End of Writet
Data Valid to Write Endt
Data Hold Timet
Write Enable to Output in High Zt
Output Active from Write Endt
Unit NotesMin Max Min Max Min Max M in Max Min Max Min Max
Address
t
WP
WE
t
AS
D
in
t
WZ
D
out
10, 11
TIMING WAVEFOR M OF WRITE CYCLE 2(CE Controlled)
5
t
DW
Data Valid
t
OW
t
DH
AS7C256-05
Page 6
AS7C256
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAA
AAA
AS7C256L
DATA RETENTION CHARACTERISTICS(L Version Only)
ParameterSymbolTest ConditionsMinMaxUnit
V
for Data Retenti o nV
CC
Data Retention CurrentI
Chip Enable to Data Retention Timet
Operation Recovery Timet
Input Leakage Current
DATA RETENTION WAVEFORM
V
CC
CE
4.5V4.5V
V
IH
AC TEST CONDITIONS
– Output load: see Figure B,
except for t
– Input pulse level: GND to 3.0V. See Figure A.
– Input rise and fall times: 5 ns. See Figure A.
– Input and output timing reference levels: 1.5V.
CLZ
and t
see Figure C.
CHZ
DR
CCDR
CDR
R
VCC = 2.0V
≥ V
CE
≥ V
V
in
V
CC
CC
≤ 0.2V
in
–0.2V
–0.2V or
2.0–V
–150µA
0–ns
t
RC
–ns
| ILI |–1µA
(L Version Only)
Data retention mode
V
≥ 2.0V
DR
V
IH
168Ω
t
R
+1.728V
+5V
AS7C256-07
t
CDR
V
DR
Thevenin Equivalent:
D
out
+5V
480
GND
Ω
D
out
255Ω
Figure C: Output Load for t
+3.0V
GND
90%
10%
90%
10%
Figure A: Input Waveform
D
out
255Ω30 pF*
Figure B: Output Load
AS7C256-08AS7C256-09AS7C256-10
NOTES
1. During VCC power-up, a pull-up resistor to VCC on CE is requir ed to me et ISB specification.
2. This parameter is sampl ed an d not 100% tested.
3. For test conditions, see AC Test Conditio ns, Figures A, B, C.
4. t
CLZ
and t
are specified with CL = 5pF as in Figure C. Transition is measured ±500mV from steady-state voltage.
CHZ
5. This parame ter is guarante e d but not teste d.
6. WE
is HIGH for read cycle.
7. CE
and OE are LOW for read cycl e.
8. Address valid prior to or coincident with CE
transition LOW.
9. All read cycle timings are referenced from the last valid address to the first transitioning address.
10. CE
or WE must be HIGH during address transitions.
11. All write cycle timings are referenced from the last valid address to the first transitioning address.
6
480
5 pF*
GND
Ω
*including scope
and jig capacitance
, t
CLZ
CHZ
Page 7
TYP I CAL DC AN D AC CHARAC TERIS TICS
Output voltage (V)
0.03.75
5.0
2.51.25
0
20
60
80
40
100
120
140
Output source current (mA)
Output source current I
OH
Output voltage (V)
0.03.75
5.0
2.51.25
Output si nk current (mA )
Output sink current I
OL
vs. output voltage V
OL
vs. output voltage V
OH
0
20
60
80
40
100
120
140
VCC = 5.0V
Ta = 25°C
VCC = 5.0V
Ta = 25°C
Capacitance (pF)
0750
1000
500250
0
5
15
20
10
25
30
35
Change in t
AA
(ns)
Typical access time change ∆t
AA
vs. output capac itive loading
VCC = 4.5V
AS7C256
AS7C256L
Normalized supply current ICC, I
vs. supply voltage V
1.4
1.2
I
SB
1.0
, I
CC
0.8
CC
0.6
I
Normalized I
0.4
SB
0.2
0.0
4.05.5
5.04.5
Supply voltage (V)
Normalized access time t
vs. supply voltage V
1.5
1.4
1.3
1.2
1.1
CC
CC
AA
6.0
SB
Normalized supply current ICC, I
vs. ambient temperature T
1.4
1.2
I
SB
1.0
, I
CC
0.8
CC
0.6
0.4
Normalized I
0.2
I
SB
0.0
–5580
35–10
Ambient temperature (°C)
Normaliz e d acc ess time t
vs. ambient tempe rat ure T
REPRESENT AT IVE S, DISTRIB UT OR S, AND SA LES OFF ICE S
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