Datasheet AS7C3256A-20TC, AS7C3256A-20JC, AS7C3256A-15TI, AS7C3256A-15TC, AS7C3256A-15JI Datasheet (Alliance Semiconductor Corporation)

March 2001
Advance Information

AS7C256A

AS7C3256A

®

5V/3.3V 32K X 8 CMOS SRAM (Common I/O)

Features

• AS7C256A (5V version)

• AS7C3256A (3.3V version)

• Industrial and commercial temperature

• Organization: 32,768 words × 8 bits

• High speed

- 10/12/15/20 ns address access time

- 3/3/4/5 ns output enable access time

• Very low power consumption: ACTIVE

- 495mW (AS7C256A) / max @ 10 ns

- 216mW (AS7C3256A) / max @ 10 ns

Logic block diagram

V

CC

GND

Input buffer

A0

A1

A14

A2

A3

A4

A5

A6

Row decoder

256 X 128 X 8

(262,144)

Column decoder

A8A

A9A10A11A12A

7

Array

13

Sense amp

Control

circuit

WE

OE

CE

• Very low power consumption: STANDBY

- 11 mW (AS7C256A) / max CMOS I/O

- 3.6 mW (AS7C3256A) / max CMOS I/O

• Latest 6T 0.25u CMOS technology

• 2.0V data retention

• Easy memory expansion with CE

• TTL-compatible, three-state I/O

• 28-pin JEDEC standard packages

-300 mil SOJ

-8 × 13.4 TSOP

• ESD protection ≥ 2000 volts

• Latch-up current ≥ 200 mA

Pin arrangement

28-pin TSOP I (8×13.4)

1

OE A10

A11

A9
A8

A13

I/O7

I/O0

WE

V

CC

A14
A12

A7
A6
A5
A4
A3 A2

Note: This part is compatible with both pin numbering

(22)

2

(23)

3

(24)

4

(25)

5

(26)

6

(27)

7

(28)

AS7C256A

8

(1)

AS7C3256A

9

(2)

10

(3)

11

(4)

12

(5)
(6)

13

(7)

14

conventions used by various manufacturers.

(21)
(20)
(19)
(18)
(17)
(16)
(15)
(14)
(13)
(12)
(11)
(10)
(9)
(8)

and OE inputs

28-pin SOJ (300 mil)

A14

CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1

A12

I/O0

I/O1

I/O2

GND

28
27
26
25
24
23
22
21
20
19
18
17
16
15

1
2
3

A7

4

A6

5

A5

6

A4

7

A3

8

A2

9

A1

10

A0

11
12
13
14

AS7C256A

AS7C3256A

28

V
27
26
25
24
23
22
21
20
19
18
17
16
15

CC

WE

A13

A8

A9

A11

OE

A10

CE

I/O7

I/O6

I/O5

I/O4

I/O3

Selection guide

AS7C256A-10

AS7C3256A-10

Maximum address access time 10 12 15 20 ns

Maximum output enable access time 3 3 4 5 ns

AS7C256A 90 80 70 70 mA

Maximum operating current

AS7C3256A 60 50 45 45 mA

Maximum CMOS standby
current

3/7/01; V.0.9.2 Alliance Semiconductor P. 1 of 8

AS7C256A 2 2 2 5 mA

AS7C3256A 1 1 1 2 mA

AS7C256A-12

AS7C3256A-12

AS7C256A-15

AS7C3256A-15

Copyright © Alliance Semiconductor. All rights reserved.

AS7C256A-20

AS7C3256A-20 Unit

AS7C256A

AS7C3256A

®

Functional description

The AS7C(3)256A is a 5V/3.3V high-performance CMOS 262,144-bit Static Random-Access Memory (SRAM) device organized
as 32,768 words × 8 bits. It is designed for memory applications requiring fast data access at low voltage, including Pentium
PowerPC

TM

, and portable computing. Alliance’s advanced circuit design and process techniques permit 3.3V operation without

sacrificing performance or operating margins.

The device enters standby mode when

is high. CMOS standby mode consumes ≤3.6 mW. Normal operation offers 75% power

CE

reduction after initial access, resulting in significant power savings during CPU idle, suspend, and stretch mode. Both versions of
the AS7C256A offer 2.0V data retention.

Equal address access and cycle times (t
ideal for high-performance applications. The chip enable (

, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 3/3/4/5 ns are

AA

) input permits easy memory expansion with multiple-bank

CE

memory organizations.

) and write enable (WE) LOW. Data on the input pins I/O0-I/O7 is

A write cycle is accomplished by asserting chip enable (
written on the rising edge of

(write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/

WE

O pins only after outputs have been disabled with

A read cycle is accomplished by asserting chip enable (

CE

output enable (OE) or write enable (

) and output enable (OE) LOW, with write enable (WE) high. The chip

CE

WE

).

drives I/O pins with the data word referenced by the input address. When chip enable or output enable is high, or write enable
is low, output drivers stay in high-impedance mode.

All chip inputs and outputs are TTL-compatible and 5V tolerant. Operation is from a single 3.3±0.3V supply. The AS7C(3)256A
is packaged in high volume industry standard packages.

TM

,

Absolute maximum ratings

Parameter Device Symbol Min Max Unit

Vol t a g e o n V

relative to GND

CC

AS7C3256A V

Voltage on any pin relative to GND V

Power dissipation P

Storage temperature (plastic) T

AS7C256A V

Ambient temperature with V

applied T

CC

DC current into outputs (low) I

Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.

t1

t1

t2

D

stg

bias

OUT

–0.5 +7.0 V

–0.5 +5.0 V

–0.5 VCC + 0.5 V

–1.0W

–65 +150

–55 +125

o

C

o

C

–20mA

Truth table

CE WE OE

H X X High Z Standby (I

L H H High Z Output disable (I

LHLD

LLXD

X = Don’t care, L = Low, H = High

Key:

Data Mode

OUT

IN

Read (ICC)

Write (ICC)

, I

)

SB

SB1

)

CC

3/7/01; V.0.9.2 Alliance Semiconductor P. 2 of 8

AS7C256A

AS7C3256A

®

Recommended operating conditions

Parameter Device Symbol Min Typical Max Unit

Supply voltage

Input voltage

Ambient operating temperature

*

VIL min = –2.0V for pulse width less than tRC/2.

AS7C256A V

AS7C3256A V

AS7C256A V

AS7C3256A V

—V

commercial T

industrial T

CC

CC

IH

IH

*

IL

A

A

DC operating characteristics (over the operating range)1

Parameter Sym Test conditions Device

Input leakage
current

Output leakage
current

Operating
power supply
current

Standby power
supply current

Output voltage

Data retention
current

|I

|I

I

I

I

V

V

I

V

|

LI

V

V

|

LO

V

V

CC

f = f

V

SB

f = f

V
V

SB1

V

OLIOL

OHIOH

V

CE

CCDR

V

0.2V

= Max,

CC

= GND to V

in

= Max,

CC

= GND to V

OUT

= Max, CE ≤ V

CC

, I

Max

= Max, CE ≤ V

CC

, I

Max

= Max, CE > V

CC

< GND + 0.2V or

IN

> VCC–0.2V, f = 0

IN

OUT

OUT

CC

= 0mA

= 0mA

CC

IL

IL

CC

Both –1–1–1µA

Both

AS7C256A

AS7C3256A

AS7C256A

AS7C3256A

AS7C256A

–0.2V

AS7C3256A

= 8 mA, VCC = Min Both – 0.4 – 0.4 – 0.4 V

= –4 mA, VCC = Min Both 2.4 – 2.4 – 2.4 – V

= 2.0V

CC

> V

-0.2V

CC

> VCC -0.2V or VIN <

IN

Both .5 .5 .5 1 mA

4.5 5.0 5.5 V

3.0 3.3 3.6 V

2.2 – VCC+0.5 V

2.0 – VCC+0.5 V

*

-0.5

–0.8V

0–70oC

–40 – 85

o

-10 -12 -15 -20

–1–1–1µA

90 – 80 – 70 – 70

60 – 50 – 45 – 45

30 – 25 – 20 – 20

30 – 25 – 20 – 20

2–2– 2 –5.0

1–1– 1 –2.0

C

UnitMin Max Min Max Min Max Min Max

mA

mA

mA

Capacitance (f = 1MHz, Ta = room temperature, VCC = NOMINAL)

2

Parameter Symbol Signals Test conditions Max Unit

Input capacitance C

I/O capacitance C

3/7/01; V.0.9.2 Alliance Semiconductor P. 3 of 8

IN

I/O

A, CE, WE,

OE

I/O Vin = V

Vin = 0V 5 pF

= 0V 7 pF

out

AS7C256A

AS7C3256A

®

Read cycle (over the operating range)

Parameter Symbol

Read cycle time t

Address access time t

Chip enable (CE

Output enable (OE

) access time

) access time

Output hold from address change t

CE

LOW to output in low Z

CE

HIGH to output in high Z

OE

LOW to output in low Z

OE

HIGH to output in high Z

Power up time t

Power down time t

RC

AA

t

ACE

t

OE

OH

t

CLZ

t

CHZ

t

OLZ

t

OHZ

PU

PD

Key to switching waveforms

Read waveform 1 (address controlled)

3,9

-10 -12 -15 -20

Unit NotesMin Max Min Max Min Max Min Max

10 - 12 – 15 – 20 – ns

- 10 – 12 – 15 – 20 ns 3

- 10 – 12 – 15 – 20 ns 3

-3–3–4–5ns

2-3–3–3– ns 5

0-0–0–0– ns4, 5

-3–3–4–5ns4, 5

0-0–0–0– ns4, 5

-3–3–4–5ns4, 5

0-0–0–0– ns4, 5

- 10 – 12 – 15 – 20 ns 4, 5

Undefined output/don’t careFalling inputRising input

3,6,7,9

t

RC

Address

D

out

Read waveform 2 (CE controlled)

CE

OE

t

t

t

CLZ

PU

ACE

D

out

Supply

current

t

AA

Data valid

3,6,8,9

1

t

RC

t

OE

t

OLZ

Data valid

50% 50%

t

OH

t

PD

t

OHZ

t

CHZ

I

CC

I

SB

3/7/01; V.0.9.2 Alliance Semiconductor P. 4 of 8

AS7C256A

AS7C3256A

®

Write cycle (over the operating range)

Parameter Symbol

Write cycle time t

Chip enable to write end t

Address setup to write end t

Address setup time t

Write pulse width t

Address hold from end of write t

Data valid to write end t

Data hold time t

Write enable to output in high Z t

Output active from write end t

Shaded areas contain advance information.

Write waveform 1 (WE controlled)

Address

WC

CW

AW

AS

WP

AH

DW

DH

WZ

OW

10,11

11

-10 -12 -15 -20

Unit NotesMin Max Min Max Min Max Min Max

10 - 12 – 15 – 20 – ns

8 - 10 – 12 – 12 – ns

8-9–10–12– ns

0--0–0–0– ns

7-8–9–12– ns

0-0–0–0– ns

5-6–8–10– ns

0-0–0–0– ns4, 5

-6–6–6–6 ns4, 5

1-1–1–2– ns4, 5

t

WC

t

AW

t

AH

WE

t

AS

D

in

D

out

Write waveform 2 (CE controlled)

Address

t

AS

CE

WE

D

in

D

out

10,11

t

t

WZ

WZ

t

AW

t

t

CW

t

WC

WP

t

WP

t

t

DW

Data valid

DW

Data valid

t

AH

t

DH

t

OW

t

DH

3/7/01; V.0.9.2 Alliance Semiconductor P. 5 of 8

AS7C256A

AS7C3256A

®

Data retention characteristics (over the operating range)

Parameter Symbol Test conditions Min Max Unit

for data retention V

V

CC

Chip enable to data retention time t

Operation recovery time t

Input leakage current | I

Data retention waveform

DR

CDR

R

| –1µA

LI

VCC = 2.0V

≥ V

CE

V

≥ V

IN

≤ 0.2V

V

IN

CC

CC

or

–0.2V

–0.2V

Data retention mode

2.0 – V

0–ns

t

RC

–ns

V

CC

CE

VCC VCC

t

CDR

V

IH

≥

V

2.0V

DR

V

DR

AC test conditions

- Output load: see Figure B or Figure C.

- Input pulse level: GND to 3.0V. See Figure A.

- Input rise and fall times: 2 ns. See Figure A.

- Input and output timing reference levels: 1.5V.

+5V

Ω

480

C(14)

GND

ad

+3.0V

GND

90%

10%

2 ns

Figure A: Input pulse

90%

10%

D

out

Ω

255

Figure B: Output lo

Notes

1During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.

2 This parameter is sampled, but not 100% tested.

3 For test conditions, see

4 These parameters are specified with CL = 5pF, as in Figures B or C. Transition is measured

5 This parameter is guaranteed, but not tested.

6WE

is High for read cycle.

7CE

and OE are Low for read cycle.

8 Address valid prior to or coincident with CE

9 All read cycle timings are referenced from the last valid address to the first transitioning address.

10 CE

or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle.

11 All write cycle timings are referenced from the last valid address to the first transitioning address.

12 CE1

and CE2 have identical timing.

13 C=30pF, except on High Z and Low Z parameters, where C=5pF.

AC Test Conditions

, Figures A, B, C.

transition Low.

±

500mV from steady-state voltage.

t

R

V

IH

Thevenin equivalent

D

out

+1.72V (5V and 3.3V)

Ω

168

+3.3V

320

D

out

Ω

350

C(14)

GND

Figure C: Output load

Ω

3/7/01; V.0.9.2 Alliance Semiconductor P. 6 of 8

Package diagrams

e

Pin 1

AS7C256A

AS7C3256A

®

28-pin SOJ

D

A1

E

A2

E1

E2

B

A

b

c

Seating

Plane

A1
A2

E1
E2

A

B
b

c

D

E

e

Min Max

- 0.140

0.025 -

0.095 0.105

0.028 TYP

0.018 TYP

0.010 TYP

- 0.730

0.245 0.285

0.295 0.305

0.327 0.347

0.050 BSC

b

E

e

c

L

A1AA2

A1

D

Hd

pin 1(7) pin 5(8)

pin 1(22)

pin 8(21)

α

Hd

28-pin

Note: This part is compatible with both pin numbering

conventions used by various manufacturers.

28-pin TSOP

8×13.4

Min Max

A

A2 0.95 1.05

b

c

D

e
E

L

α 0° 5°

–1.20

0.10 0.20

0.15 0.25

0.10 0.20

11.60 11.80

0.55 nominal

8.0 nominal

13.30 13.50

0.50 0.70

3/7/01; V.0.9.2 Alliance Semiconductor P. 7 of 8

AS7C256A

AS7C3256A

®

Ordering information

Package / Access time Volt/Temp 10 ns 12 ns 15 ns 20 ns

5V commercial AS7C256A-10JC AS7C256A-12JC AS7C256A-15JC AS7C256A-20JC

Plastic SOJ, 300 mil

TSOP 8x13.4

Part numbering system

AS7C 3 256A –XX X C or I

SRAM prefix 3 = 3.3V supply Device number Access time

3.3V commercial AS7C3256A-10JC AS7C3256A-12JC AS7C3256A-15JC AS7C3256A-20JC

5V industrial AS7C256A-10JI AS7C256A-12JI AS7C256A-15JI AS7C256A-20JI

3.3V industrial AS7C3256A-10JI AS7C3256A-12JI AS7C3256A-15JI AS7C3256A-20JI

5V commercial AS7C256A-10TC AS7C256A-12TC AS7C256A-15TC AS7C256A-20TC

3.3V commercial AS7C3256A-10TC AS7C3256A-12TC AS7C3256A-15TC AS7C3256A-20TC

5V industrial AS7C256A-10TI AS7C256A-12TI AS7C256A-15TI AS7C256A-20TI

3.3V industrial AS7C3256A-10TI AS7C3256A-12TI AS7C3256A-15TI AS7C3256A-20TI

Commercial temperature range:

o

C to 70 0C

Package: J = SOJ 300 mil

T = TSOP 8x13.4

0

Industrial temperature range:

-40C to 85C

3/7/01; V.0.9.2 Alliance Semiconductor P. 8 of 8

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notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information
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