Datasheet AS7C3256-20TI, AS7C3256-20TC, AS7C3256-20PC, AS7C3256-20JI, AS7C3256-20JC Datasheet (Alliance Semiconductor Corporation)

January 2001
Advance Information

Copyright © Alliance Semiconductor. All rights reserved.

AS7C256

AS7C3256

1/10/2001 Alliance Semiconductor P. 1 of 9

5V/3.3V 32K X 8 CMOS SRAM (Common I/O)

®

Features

• AS7C256 (5V version)

• AS7C3256 (3.3V version)

• Industrial and commercial temperature

• Organization: 262,144 words × 16 bits

• High speed

- 12/15/20 ns address access time

- 5/6/7/9 ns output enable access time

• Very low power consumption: ACTIVE

- 660mW (AS7C256) / max @ 12 ns

- 216mW (AS7C3256) / max @ 12 ns

• Very low power consumption: STANDBY

- 22 mW (AS7C256) / max CMOS I/O

- 7.2 mW (AS7C3256) / max CMOS I/O

• 2.0V data retention

• Easy memory expansion with CE

and OE inputs

• TTL-compatible, three-state I/O

• 28-pin JEDEC standard packages

-300 mil PDIP

-300 mil SOJ

-8 × 13.4 TSOP

• ESD protection ≥ 2000 volts

• Latch-up current ≥ 200 mA

Logic block diagram

A8A

7

256 X 128 X 8

Array

(262,144)

Input buffer

A0

A1

A2

A3

A4

A5

A6

A14

A9A10A11A12A

13

I/O0

I/O7

V

CC

GND

OE

CE

WE

Column decoder

Row decoder

Control

circuit

Sense amp

Pin arrangement

1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17

V

CC

WE
A13

A8
A9

A11
OE
A10
CE
I/O7

I/O6

I/O5
I/O4

I/O3

A14
A12

A7
A6

A5

A4
A3
A2
A1
A0

I/O0

I/O1
I/O2

GND

AS7C256

AS7C3256

16
15

1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17

V

CC

WE

A13

A8

A9

A11

OE A10

CE
I/O7
I/O6
I/O5
I/O4

I/O3
A14
A12

A7
A6
A5
A4
A3 A2

A1

A0

I/O0

I/O1

I/O2

GND

AS7C256

AS7C3256

16
15

28-pin TSOP I (8×13.4)

28-pin DIP, SOJ (300 mil)

Note: This part is compatible with both pin numbering

conventions used by various manufacturers.

(21)
(20)
(19)
(18)
(17)
(16)
(15)
(14)
(13)
(12)
(11)
(10)
(9)
(8)

(22)
(23)
(24)
(25)
(26)
(27)
(28)
(1)
(2)
(3)
(4)
(5)
(6)
(7)

Selection guide

AS7C256-10

AS7C3256-10

AS7C256-12

AS7C3256-12

AS7C256-15

AS7C3256-15

AS7C256-20

AS7C3256-20 Unit

Maximum address access time 10 12 15 20 ns

Maximum output enable access time 5 6 7 ns

Maximum operating current

AS7C256 120 115 110 mA

AS7C3256 60 55 50 mA

Maximum CMOS standby
current

AS7C256 4 4 4 mA

AS7C3256 2 2 2 mA

®

AS7C256

AS7C3256

1/10/2001 Alliance Semiconductor P. 2 of 9

Functional description

The AS7C(3)256 is a 5V/3.3V high-performance CMOS 262,144-bit Static Random-Access Memory (SRAM) device organized
as 262,144 words × 16 bits. It is designed for memory applications requiring fast data access at low voltage, including
Pentium

TM

, PowerPCTM, and portable computing. Alliance’s advanced circuit design and process techniques permit 3.3V

operation without sacrificing performance or operating margins.

The device enters standby mode when

CE

is high. CMOS standby mode consumes ≤3.6 mW. Normal operation offers 75% power

reduction after initial access, resulting in significant power savings during CPU idle, suspend, and stretch mode. Both versions
of the AS7C256 offer 2.0V data retention.

Equal address access and cycle times (t

AA

, tRC, tWC) of 12/15/20 ns with output enable access times (tOE) of 5/6/7/9 ns are

ideal for high-performance applications. The chip enable (

CE

) input permits easy memory expansion with multiple-bank

memory organizations.

A write cycle is accomplished by asserting chip enable (

CE

) and write enable (WE) LOW. Data on the input pins I/O0-I/O7 is

written on the rising edge of

WE

(write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive

I/O pins only after outputs have been disabled with

output enable (OE) or write enable (

WE

).

A read cycle is accomplished by asserting chip enable (

CE

) and output enable (OE) LOW, with write enable (WE) high. The
chip drives I/O pins with the data word referenced by the input address. When chip enable or output enable is high, or write
enable is low, output drivers stay in high-impedance mode.

All chip inputs and outputs are TTL-compatible and 5V tolerant. Operation is from a single 3.3±0.3V supply. The
AS7C(3)256A is packaged in high volume industry standard packages.

Absolute maximum ratings

Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute max­imum rating conditions for extended periods may affect reliability.

Truth table

Key:

X = Don’t care, L = Low, H = High

Parameter Device Symbol Min Max Unit

Vol t a g e o n V

CC

relative to GND

AS7C256 V

t1

–0.5 +7.0 V

AS7C3256 V

t1

–0.5 +5.0 V

Voltage on any pin relative to GND V

t2

–0.5 VCC + 0.5 V

Power dissipation P

D

–1.0W

Storage temperature (plastic) T

stg

–65 +150

o

C

Ambient temperature with V

CC

applied T

bias

–55 +125

o

C

DC current into outputs (low) I

OUT

–20mA

CE WE OE

Data Mode

H X X High Z Standby (I

SB

, I

SB1

)

L H H High Z Output disable (I

CC

)

LHLD

OUT

Read (ICC)

LLXD

IN

Write (ICC)

®

AS7C256

AS7C3256

1/10/2001 Alliance Semiconductor P. 3 of 9

Recommended operating conditions

*

VIL min = –2.0V for pulse width less than tRC/2.

DC operating characteristics (over the operating range)1

Capacitance (f = 1MHz, Ta = room temperature, VCC = NOMINAL)

2

Parameter Device Symbol Min Typical Max Unit

Supply voltage

AS7C256 V

CC

4.5 5.0 5.5 V

AS7C3256 V

CC

3.0 3.3 3.6 V

Input voltage

AS7C256 V

IH

2.2 – VCC+0.5 V

AS7C3256 V

IH

2.0 – VCC+0.5 V

—V

IL

*

-0.5

*

–0.8V

Ambient operating temperature

commercial T

A

0–70oC

industrial T

A

–40 – 85

o

C

Parameter Sym Test conditions Device

-10 -12 -15 -20

UnitMin Max Min Max Min Max Min Max

Input leakage
current

|I

LI

|

V

CC

= Max,

V

in

= GND to V

CC

–1–1–1µA

Output leakage
current

|I

LO

|

V

CC

= Max,

V

OUT

= GND to V

CC

–1–1–1µA

Operating
power supply
current

I

CC

V

CC

= Max, CE ≤ V

IL

f = f

Max

, I

OUT

= 0mA

AS7C256

– 120 – 115 – 110

mA

AS7C3256

–60– 55 – 50

Standby power
supply current

I

SB

V

CC

= Max, CE ≤ V

IL

f = f

Max

, I

OUT

= 0mA

AS7C256

–40– 35 – 30

mA

AS7C3256

–20– 20 – 20

I

SB1

V

CC

= Max, CE > V

CC

–0.2V

V

IN

< GND + 0.2V or

V

IN

> VCC–0.2V, f = 0

AS7C256

– 4.0 – 4.0 – 4.0

mA

AS7C3256

– 2.0 – 2.0 – 2.0

Output voltage

V

OLIOL

= 8 mA, VCC = Min – 0.4 – 0.4 – 0.4 V

V

OHIOH

= –4 mA, VCC = Min 2.4 – 2.4 – 2.4 – V

Parameter Symbol Signals Test conditions Max Unit

Input capacitance C

IN

A, CE, WE,

OE

Vin = 0V 5 pF

I/O capacitance C

I/O

I/O Vin = V

out

= 0V 7 pF

®

AS7C256

AS7C3256

1/10/2001 Alliance Semiconductor P. 4 of 9

Read cycle (over the operating range)

3,9

Key to switching waveforms

Read waveform 1 (address controlled)

3,6,7,9

Read waveform 2 (CE controlled)

3,6,8,9

Parameter Symbol

-10 -12 -15 -20

Unit NotesMin Max Min Max Min Max Min Max

Read cycle time t

RC

12 – 15 – 20 – ns

Address access time t

AA

–12–15–20ns 3

Chip enable (CE

) access time

t

ACE

–12–15–20ns 3

Output enable (OE

) access time

t

OE

–5–6–7ns

Output hold from address change t

OH

3–3–3–ns 5

CE

LOW to output in low Z

t

CLZ

3–3–3–ns4, 5

CE

HIGH to output in high Z

t

CHZ

–3–4–5ns4, 5

OE

LOW to output in low Z

t

OLZ

0–0–0–ns4, 5

OE

HIGH to output in high Z

t

OHZ

–3–4–5ns4, 5

Power up time t

PU

0–0–0–ns4, 5

Power down time t

PD

–12–15–20ns 4, 5

Undefined output/don’t careFalling inputRising input

Address

D

out

Data valid

t

OH

t

AA

t

RC

Supply

current

CE

OE

D

out

t

RC

1

t

OE

t

OLZ

t

ACE

t

CHZ

t

CLZ

t

PU

t

PD

I

CC

I

SB

50% 50%

t

OHZ

Data valid

®

AS7C256

AS7C3256

1/10/2001 Alliance Semiconductor P. 5 of 9

Write cycle (over the operating range)

11

Shaded areas contain advance information.

Write waveform 1 (WE controlled)

10,11

Write waveform 2 (CE controlled)

10,11

Parameter Symbol

-10 -12 -15 -20

Unit NotesMin Max Min Max Min Max

Write cycle time t

WC

12 – 15 – 20 – ns

Chip enable to write end t

CW

8–10–12– ns

Address setup to write end t

AW

8–10–12– ns

Address setup time t

AS

0–0–0– ns

Write pulse width t

WP

8–9–12– ns

Address hold from end of write t

AH

0–0–0– ns

Data valid to write end t

DW

6–8–10– ns

Data hold time t

DH

0–0–0– ns4, 5

Write enable to output in high Z t

WZ

–5–5–5 ns4, 5

Output active from write end t

OW

3–3–3– ns4, 5

t

AW

t

AH

t

WC

Address

WE

D

in

D

out

t

DH

t

OW

t

DW

t

WZ

t

WP

t

AS

Data valid

t

AW

Address

CE

WE

D

in

D

out

Data valid

t

CW

t

WP

t

DW

t

DH

t

AH

t

WZ

t

WC

t

AS

®

AS7C256

AS7C3256

1/10/2001 Alliance Semiconductor P. 6 of 9

Data retention characteristics (over the operating range)

13

Data retention waveform

AC test conditions

Notes

1During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.

2 This parameter is sampled, but not 100% tested.

3 For test conditions, see

AC Test Conditions

, Figures A, B, C.

4 These parameters are specified with CL = 5pF, as in Figures B or C. Transition is measured

±

500mV from steady-state voltage.

5 This parameter is guaranteed, but not tested.

6WE

is High for read cycle.

7CE

and OE are Low for read cycle.

8 Address valid prior to or coincident with CE

transition Low.

9 All read cycle timings are referenced from the last valid address to the first transitioning address.

10 CE

or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle.

11 All write cycle timings are referenced from the last valid address to the first transitioning address.

12 CE1

and CE2 have identical timing.

13 2V data retention applies to the commercial operating range only.

14 C=30pF, except on High Z and Low Z parameters, where C=5pF.

Parameter Symbol Test conditions Min Max Unit

V

CC

for data retention V

DR

VCC = 2.0V

CE

≥ V

CC

–0.2V

V

IN

≥ V

CC

–0.2V

or

V

IN

≤ 0.2V

2.0 – V

Data retention current I

CCDR

–500µA

––µA

Chip enable to data retention time t

CDR

0–ns

Operation recovery time t

R

t

RC

–ns

Input leakage current | I

LI

| –1µA

V

CC

CE

t

R

t

CDR

Data retention mode

VCC VCC

V

DR

≥

2.0V

V

IH

V

IH

V

DR

350

Ω

C(14)

320

Ω

D

out

GND

+3.3V

168

Ω

D

out

+1.72V (5V and 3.3V)

Figure C: Output load

255

Ω

C(14)

480

Ω

D

out

GND

+5V

Figure B: Output lo

ad

Thevenin equivalent

- Output load: see Figure B or Figure C.

- Input pulse level: GND to 3.0V. See Figure A.

- Input rise and fall times: 2 ns. See Figure A.

- Input and output timing reference levels: 1.5V.

10%

90%

10%

90%

GND

+3.0V

Figure A: Input pulse

2 ns

®

AS7C256

AS7C3256

1/10/2001 Alliance Semiconductor P. 7 of 9

Typical DC and AC characteristics

Supply voltage (V)

MIN

MAX

NOMINAL

0.0

0.2

0.6

0.8

0.4

1.0

1.2

1.4

Normalized I

CC

, I

SB

Normalized supply current ICC, I

SB

Ambient temperature (°C)

–55 80

125

35–10

0.0

0.2

0.6

0.8

0.4

1.0

1.2

1.4

Normalized I

CC

, I

SB

Normalized supply current ICC, I

SB

vs. ambient temperature T

a

vs. supply voltage V

CC

I

CC

I

SB

I

CC

I

SB

Ambient temperature (°C)

-55 80

125

35-10

0.2

1

0.04

5

25

625

Normalized I

SB1

(log scale)

Normalized supply current ISB1

vs. ambient temperature T

a

VCC = VCC(NOMINAL)

Supply voltage (V)

MIN

MAX

NOMINAL

0.8

0.9

1.1

1.2

1.0

1.3

1.4

1.5

Normalized access time

Normalized access time t

AA

Ambient temperature (°C)

–55 80

125

35–10

0.8

0.9

1.1

1.2

1.0

1.3

1.4

1.5

Normalized access time

Normalized access time t

AA

Cycle frequency (MHz)

075

100

5025

0.0

0.2

0.6

0.8

0.4

1.0

1.2

1.4

Normalized I

CC

Normalized supply current I

CC

vs. ambient temperature T

a

vs. cycle frequency 1/tRC, 1/t

WC

vs. supply voltage V

CC

VCC = VCC(NOMINAL)

Ta = 25°C

VCC = VCC(NOMINAL)Ta = 25°C

Output voltage (V)

V

CC

0

20

60

80

40

100

120

140

Output source current (mA)

Output source current I

OH

Output voltage (V)

V

CC

Output sink current (mA)

Output sink current I

OL

vs. output voltage V

OL

vs. output voltage V

OH

0

20

60

80

40

100

120

140

VCC = VCC(NOMINAL)PL

Ta = 25°C

VCC = VCC(NOMINAL)

Ta = 25°C

Capacitance (pF)

0 750

1000

500250

0

5

15

20

10

25

30

35

Change in t

AA

(ns)

Typical access time change ∆t

AA

vs. output capacitive loading

VCC = V

CC(NOMINAL)

00

®

AS7C256

AS7C3256

1/10/2001 Alliance Semiconductor P. 8 of 9

Package diagrams

c

eA

α

Seating

b

A1

E1

E

D

e

L

S

Plane

B

A

Pin 1

28-pin PDIP

Min Max

A - 0.175

A1 0.010 -

B 0.058 0.064

b 0.016 0.022

c 0.008 0.014

D - 1.400

E 0.295 0.320

E1 0.278 0.298

e0.100 BSC

eA 0.330 0.370

L 0.120 0.140

α 0° 15°

S - 0.055

28-pin SOJ

Min Max

A

- 0.140

A1

0.025 -

A2

0.095 0.105

B

0.028 TYP

b

0.018 TYP

c

0.010 TYP

D

- 0.730

E

0.245 0.285

E1

0.295 0.305

E2

0.327 0.347

e

0.050 BSC

28-pin
8×13.4

Min Max

A

–1.20

A1

0.10 0.20

A2 0.95 1.05

b

0.15 0.25

c

0.10 0.20

D

11.60 11.80

e

0.55 nominal

e

D

E1

Pin 1

b

B

A1

A2

c

E

Seating

Plane

E2

A

e

b

E

HdD

c

L

A1AA2

α

28-pin

pin 8(21)

pin 1(7) pin 5(8)

pin 1(22)

Note: This part is compatible with both pin numbering

conventions used by various manufacturers.

© Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names
may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors
that may appear in this document. The data conta ined herein represents Alliance’s bes t da ta a nd/or e s timate s at the time of issuance. Alliance reserves the right to change or correct this data at any time, without
notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information
for potential customers and users, and is not intended to operate as, or provide, any guarantee or warran tee to any user or customer. Alliance does not assume any responsibility or liability arising out of the
application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including lia bility or warranties related to fitne ss for a par­ticular purpose, merchantability , or infringement of any intellectual property rights , except as express agreed to in Alliance’s Terms and Conditions of Sale (which are available from Alliance). All sales of Alli­ance products are made exclusively according to A lliance’s Terms and Conditions of Sale. The purchase of products from Alliance doe s not convey a license under any patent rights, copyrights, mask works
rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or
failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and
agrees to indemnify Alliance against all claims arising from such use.

®

AS7C256

AS7C3256

1/10/2001 Alliance Semiconductor P. 9 of 9

Ordering information

Part numbering system

Package / Access time Volt/Temp 10 ns 12 ns 15 ns 20 ns

Plastic DIP, 300 mil

5V commercial AS7C256-10PC AS7C256-12PC AS7C256-15PC AS7C256-20PC

3.3V commercial AS7C3256-10PC AS7C3256-12PC AS7C3256-15PC AS7C3256-20PC

Plastic SOJ, 300 mil

5V commercial AS7C256-10JC AS7C256-12JC AS7C256-15JC AS7C256-20JC

3.3V commercial AS7C3256-10JC AS7C3256-12JC AS7C3256-15JC AS7C3256-20JC

5V industrial AS7C256-10JI AS7C256-12JI AS7C256-15JI AS7C256-20JI

3.3V industrial AS7C3256-10JI AS7C3256-12JI AS7C3256-15JI AS7C3256-20JI

TSOP 8x13.4

5V commercial AS7C256-10TC AS7C256-12TC AS7C256-15TC AS7C256-20TC

3.3V commercial AS7C3256-10TC AS7C3256-12TC AS7C3256-15TC AS7C3256-20TC

5V industrial AS7C256-10TI AS7C256-12TI AS7C256-15TI AS7C256-20TI

3.3V industrial AS7C3256-10TI AS7C3256-12TI AS7C3256-15TI AS7C3256-20TI

AS7C 3 256 –XX X C or I

SRAM prefix 3 = 3.3V supply Device number Access time

Package: J = SOJ 300 mil

T = TSOP 8x13.4

Commercial temperature range:
0

o

C to 70 0C

Industrial temperature range:

-40C to 85C