Page 1
查询AS7C252MFT18A供应商
January 2005
2.5V 2M × 18 Flow-through synchronous SRAM
Features
• Organization: 2,097152 words × 18 bits
• Fast clock to data access: 7.5/8.5/10 ns
•Fast OE
• Fully synchronous flow-through operation
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Individual byte write and global write
Logic block diagram
access time: 3.5/4.0 ns
CLK
ADV
ADSC
ADSP
A[20:0]
GWE
BW
BWE
BW
CE0
CE1
CE2
b
a
ZZ
Power
down
21
• Multiple chip enables for easy expansion
• 2.5V core power supply
• Linear or interleaved burst control
• Snooze mode for reduced power-standby
• Common data inputs and data outputs
LBO
CLK
CS
Burst logic
CLR
Address
register
DQb
Byte Write
registers
CLK
DQa
Byte Write
registers
CLK
Enable
register
CE
CLK
Enable
delay
register
CLK
Q
D
CS
CLK
DQ
DQ
DQ
DQ
21
AS7C252MFT18A
®
2M x 18
OE
Output
registers
CLK
18
2
Memory
array
18
Input
registers
CLK
19
21
OE
18
DQ[a,b]
Selection guide
-75 -85 -10 Units
Minimum cycle time
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
1/17/05, v 1.2 Alliance Semiconductor 1 of 19
8.5 10 12 ns
7.5 8.5 10 ns
325 300 275 mA
130 130 130 mA
90 90 90 mA
Copyright © Alliance Semiconductor. All rights reserved.
Page 2
AS7C252MFT18A
®
2.5V 32 Mb Synchronous SRAM products list
Org Part Number Mode Speed
2MX18 AS7C252MPFS18A PL-SCD 200/166/133 MHz
1MX32
1MX36 AS7C251MPFS36A PL-SCD 200/166/133 MHz
2MX18
1MX32
1MX36 AS7C251MPFD36A PL-DCD 200/166/133 MHz
2MX18 AS7C252MFT18A FT 7.5/8.5/10 ns
1MX32 AS7C251MFT32A FT 7.5/8.5/10 ns
1MX36
2MX18
1MX32
1MX36
2MX18
1MX32
1MX36
AS7C251MPFS32A PL-SCD 200/166/133 MHz
AS7C252MPFD18A PL-DCD 200/166/133 MHz
AS7C251MPFD32A PL-DCD 200/166/133 MHz
AS7C251MFT36A FT 7.5/8.5/10 ns
AS7C252MNTD18A NTD-PL 200/166/133 MHz
AS7C251MNTD32A NTD-PL 200/166/133 MHz
AS7C251MNTD36A NTD-PL 200/166/133 MHz
AS7C252MNTF18A NTD-FT 7.5/8.5/10 ns
AS7C251MNTF32A NTD-FT 7.5/8.5/10 ns
AS7C251MNTF36A NTD-FT 7.5/8.5/10 ns
1,2
1 Core Power Supply: VDD = 2.5V + 0.125V
2 I/O Supply Voltage: VDDQ = 2.5V +
0.125V
PL-SCD : Pipelined Burst Synchronous SRAM - Single Cycle Deselect
PL-DCD : Pipelined Burst Synchronous SRAM - Double Cycle Deselect
FT : Flow-through Burst Synchronous SRAM
1
NTD
-PL : Pipelined Burst Synchronous SRAM with NTD
NTD-FT : Flow-through Burst Synchronous SRAM with NTD
TM
TM
1NTD: No Turnaround Delay. NTDTM is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property of
their respective owners.
1/17/05, v 1.2 Alliance Semiconductor 2 of 19
Page 3
Pin assignment
100-pin TQFP - top view
NC
NC
NC
V
DDQ
V
SSQ
NC
NC
DQb0
DQb1
V
SSQ
V
DDQ
DQb2
DQb3
NC
V
DD
NC
V
SS
DQb4
DQb5
V
DDQ
V
SSQ
DQb6
DQb7
DQPb
NC
V
SSQ
V
DDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
®
DD
AACE0
100
CE1NCNC
99989796959493929190898887868584838281
BWb
BWa
CE2
V
VSSCLK
GWE
BWEOEADSC
ADSP
ADVAA
TQFP 14 x 20mm
AS7C252MFT18A
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
V
DDQ
V
SSQ
NC
DQPa
DQa7
DQa6
V
SSQ
V
DDQ
DQa5
DQa4
V
SS
NC
V
DD
ZZ
DQa3
DQa2
V
DDQ
V
SSQ
DQa1
DQa0
NC
NC
V
SSQ
V
DDQ
NC
NC
NC
31323334353637383940414243444546474849
AAA
LBO
1/17/05, v 1.2 Alliance Semiconductor 3 of 19
A
A1
A0
NC
A
AAAAAAA
SS
DD
V
V
50
A
A
Page 4
AS7C252MFT18A
®
Functional description
The AS7C252MFT18A is a high-performance CMOS 32-Mbit synchronous Static Random Access Memory (SRAM) device organized as
2,097152 words × 18 bits.
Fast cycle times of 8.5/10/12 ns with clock access times (t
Burst operation is initiated in one of two ways: the controller address strobe (ADSC
advance pin (ADV
Read cycles are initiated with ADSP
when ADSP
) allows subsequent internally generated burst addresses.
(regardless of WE and ADSC) using the new external address clocked into the on-chip address register
is sampled low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation, the data
accessed by the current address registered in the address registers by the positive edge of CLK are carried to the data-out buffer. ADV is
ignored on the clock edge that samples ADSP asserted, but is sampled on all subsequent clock edges. Address is incremented internally for
the next access of the burst when ADV
LBO
unconnected or driven high, burst operations use an interleaved count sequence. With
is sampled low and both address strobes are high. Burst mode is selectable with the
sequence.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 18
bits regardless of the state of individual BW[a,b] inputs. Alternately, when GWE is high, one or more bytes may be written by asserting BWE
and the appropriate individual byte BWn signals.
BWn
is ignored on the clock edge that samples ADSP low, but it is sampled on all subsequent clock edges. Output buffers are disabled when
is sampled LOW regardless of OE. Data is clocked into the data input register when BWn is sampled low. Address is incremented
BWn
internally to the next burst address if BWn and ADV are sampled low.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP are
as follows:
• ADSP
must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
) of 7.5/8.5/10 ns. Three chip enable (CE) inputs permit easy memory expansion.
CD
), or the processor address strobe (ADSP). The burst
LBO
input. With
LBO
driven low, the device uses a linear count
•WE signals are sampled on the clock edge that samples ADSC low (and ADSP high).
• Master chip enable CE0 blocks ADSP, but not ADSC.
The AS7C252MFT18A family operates from a core 2.5V power supply. These devices are available in 100-pin TQFP package.
TQFP capacitance
Parameter Symbol Test conditions Min Max Unit
Input capacitance C
I/O capacitance C
*Guaranteed not tested
IN
I/O
*
*
VIN = 0V - 5 pF
V
= 0V - 7 pF
OUT
TQFP thermal resistance
Description Conditions Symbol Typ ic al Units
Thermal resistance
(junction to ambient)
Thermal resistance
(junction to top of case)
1 This parameter is sampled
1–layer θ
1
1
Test conditions follow standard test methods and
procedures for measuring thermal impedance,
per EIA/JESD51
4–layer θ
JA
JA
θ
JC
40 °C/W
22 °C/W
8 °C/W
1/17/05, v 1.2 Alliance Semiconductor 4 of 19
Page 5
Signal descriptions
AS7C252MFT18A
®
Pin I/O Properties
Description
CLK I CLOCK Clock. All inputs except OE, ZZ, and LBO are synchronous to this clock.
A,A0,A1 I SYNC Address. Sampled when all chip enables are active and when ADSC
DQ[a,b] I/O SYNC Data. Driven as output when the chip is enabled and when OE
CE0
ISYNC
CE1, CE2 ISYNC
ADSP
ADSC
ADV
GWE
BWE
I SYNC Address strobe processor. Asserted low to load a new address or to enter standby mode.
I SYNC Address strobe controller. Asserted low to load a new address or to enter standby mode.
I SYNC Advance. Asserted low to continue burst read/write.
ISYNC
I SYNC Byte write enable. Asserted low with GWE high to enable effect of BW[a,b] inputs.
Master chip enable. Sampled on clock edges when ADSP
is blocked. Refer to the “Synchronous truth table” for more information.
ADSP
Synchronous chip enables, active high, and active low, respectively. Sampled on clock edges when
ADSC
is active or when CE0 and ADSP are active.
Global write enable. Asserted low to write all 18 bits. When high, BWE
enable.
or ADSC is active. When CE0 is inactive,
Write enables. Used to control write of individual bytes when GWE
BW[a,b] ISYNC
BW[a,b]
is active with GWE high and BWE low, the cycle is a write cycle. If all BW[a,b] are inactive,
or ADSP are asserted.
is active.
and BW[a,b] control write
is high and BWE is low. If any of
the cycle is a read cycle.
OE
LBO ISTATIC
I ASYNC Asynchronous output enable. I/O pins are driven when OE is active and chip is in read mode.
Selects Burst mode. When tied to V
or left floating, device follows interleaved Burst order. When
DD
driven Low, device follows linear Burst order. This signal is internally pulled High.
ZZ I ASYNC Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
NC - - No connect
Snooze Mode
SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to I
SNOOZE MODE is dictated by the length of time the ZZ is in a High state.
The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.
When the ZZ pin becomes a logic High, I
is guaranteed after the time t
SB2
is met. After entering SNOOZE MODE, all inputs except ZZ is
ZZI
disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.
Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting
SNOOZE MODE during t
, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE.
PUS
1/17/05, v 1.2 Alliance Semiconductor 5 of 19
. The duration of
SB2
Page 6
®
Write enable truth table (per byte)
Function GWE BWE BWa BWb
Write All Bytes
Write Byte a
Write Byte b
Read
Key: X = don’t care, L = low, H = high, n = a, b;
LXXX
HLLL
HLLH
HLHL
HHXX
HLHH
BWE, BWn
= internal write signal.
Asynchronous Truth Table
Operation ZZ OE I/O Status
Snooze mode H X High-Z
Read
Write L X Din, High-Z
Deselected L X High-Z
Notes:
1. X means “Don’t Care”
2. ZZ pin is pulled down internally
3. For write cycles that follows read cycles, the output buffers must be disabled with OE
4. Snooze mode means power down state of which stand-by current does not depend on cycle times
5. Deselected means power down state of which stand-by current depends on cycle times
L L Dout
L H High-Z
, otherwise data bus contention will occur.
AS7C252MFT18A
Burst sequence table
Interleaved burst address (LBO = 1) Linear burst address (LBO = 0)
A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0
1st Address
nd
2
Address
rd
3
Address
th
4
Address
0 00 11 01 1
0 10 01 11 0
1 01 10 00 1
1 11 00 10 0
1st Address
nd
2
Address
rd
3
Address
th
4
Address
0 00 11 01 1
0 11 01 10 0
1 01 10 00 1
1 11 00 11 0
1/17/05, v 1.2 Alliance Semiconductor 6 of 19
Page 7
AS7C252MFT18A
®
Synchronous truth table
1
CE0
CE1 CE2 ADSP ADSC ADV
[4]
WRITE
[2]
OE Address accessed CLK Operation DQ
HXXXLX X X NA L to H DeselectHi−Z
L L X L X X X X NA L to H Deselect Hi−Z
L L X H L X X X NA L to H Deselect Hi−Z
L X H L X X X X NA L to H Deselect Hi−Z
L X H H L X X X NA L to H Deselect Hi−Z
L H L L X X X L External L to H Begin read Q
L H L L X X X H External L to H Begin read Hi−Z
L H L H L X H L External L to H Begin read Q
L H L H L X H H External L to H Begin read Hi−Z
XXXHHL H L Next L to HContinue readQ
XXXHHL H H Next L to HContinue readHi−Z
XXXHHH H L Current L to HSuspend readQ
XXXHHH H H Current L to HSuspend readHi−Z
HXXXHL H L Next L to HContinue readQ
HXXXHL H H Next L to HContinue readHi−Z
HXXXHH H L Current L to HSuspend readQ
HXXXHH H H Current L to HSuspend readHi−Z
L H L H L X L X External L to H Begin write D
XXXHHL L X Next L to HContinue writeD
HXXXHL L X Next L to HContinue writeD
XXXHHH L X Current L to HSuspend writeD
HXXXHH L X Current L to HSuspend writeD
1 X = don’t care, L = low, H = high
2 For WRITE, L means any one or more byte write enable signals (BWa or BWb) and BWE are LOW or GWE is LOW. WRITE = HIGH for all BWx, BWE, GWE HIGH. See
"Write enable truth table (per byte)," on page 6 for more information.
3 For write operation following a READ,
4 ZZ pin is always Low.
OE
must be high before the input data set up time and held high throughout the input hold time
3
1/17/05, v 1.2 Alliance Semiconductor 7 of 19
Page 8
AS7C252MFT18A
®
Absolute maximum ratings
Parameter Symbol Min Max Unit
Power supply voltage relative to GND V
Input voltage relative to GND (input pins) V
Input voltage relative to GND (I/O pins) V
Power dissipation P
Short circuit output current I
Storage temperature T
Temperature under bias T
Stresses greater than those listed under “Absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only, and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect reliability.
Recommended operating conditions
Parameter Symbol Min Nominal Max Unit
Supply voltage for inputs V
Supply voltage for I/O V
Ground supply Vss 0 0 0 V
DD
DDQ
DD
, V
IN
IN
d
OUT
stg
bias
DDQ
–0.3 +3.6 V
–0.3 VDD + 0.3 V
–0.3 V
DDQ
–1.8W
– 20 mA
–65 +150
–65 +135
2.375 2.5 2.625 V
2.375 2.5 2.625 V
+ 0.3 V
o
o
C
C
1/17/05, v 1.2 Alliance Semiconductor 8 of 19
Page 9
DC electrical characteristics
Parameter Sym Conditions Min Max Unit
Input leakage current
Output leakage current |I
Input high (logic 1) voltage V
Input low (logic 0) voltage V
Output high voltage V
Output low voltage V
†
LBO and ZZ pins have an internal pull-up or pull-down, and input leakage = ±10 µA.
*
V
max < VDD +1.5V for pulse width less than 0.2 X t
IH
**
V
min = -1.5 for pulse width less than 0.2 X t
IL
†
|ILI|V
|OE ≥ VIH, VDD = Max, 0V < V
LO
IH
IL
OH
OL
CYC
CYC
DD
IOH = –4 mA, V
IOL = 8 mA, V
IDD operating conditions and maximum limits
AS7C252MFT18A
®
= Max, 0V < VIN < V
OUT
DD
< V
DDQ
Address and control pins 1.7* VDD+0.3 V
I/O pins 1.7* V
Address and control pins -0.3** 0.7 V
I/O pins -0.3** 0.7 V
= 2.375V 1.7 – V
DDQ
= 2.625V – 0.7 V
DDQ
-2 2 µA
-2 2 µA
+0.3 V
DDQ
Parameter Sym Conditions -75 -85 -10 Unit
Operating power supply current
1
Standby power supply current
1 ICC given with no output loading. ICC increases with faster cycle times and greater output loading.
I
I
I
CC
I
SB
SB1
SB2
CE0 < VIL, CE1 > VIH, CE2 < VIL, f = f
= 0 mA, ZZ < V
I
OUT
All VIN ≤ 0.2V or >
f = f
VDD – 0.2V,
, ZZ < V
Max
Deselected, f = 0, ZZ < 0.2V,
all VIN ≤ 0.2V or ≥ VDD – 0.2V
Deselected, f = f
Max
all VIN ≤ VIL or ≥ V
IL
Deselected,
IL
, ZZ ≥ VDD – 0.2V,
IH
Max
,
325 300 275 mA
130 130 130
90 90 90
80 80 80
mA
1/17/05, v 1.2 Alliance Semiconductor 9 of 19
Page 10
Timing characteristics over operating range
Parameter Sym
Cycle time t
Clock access time t
Output enable low to data valid t
Clock high to output low Z t
Data output invalid from clock high t
Output enable low to output low Z t
Output enable high to output high Z t
Clock high to output high Z t
Output enable high to invalid output t
Clock high pulse width t
Clock low pulse width t
Address setup to clock high t
Data setup to clock high t
Write setup to clock high t
Chip select setup to clock high t
Address hold from clock high t
Data hold from clock high t
Write hold from clock high t
Chip select hold from clock high t
ADV
setup to clock high t
ADSP
setup to clock high t
ADSC
setup to clock high t
ADV
hold from clock high t
ADSP
hold from clock high t
ADSC
hold from clock high t
1 See “Notes” on page 16.
CYC
CD
OE
LZC
OH
LZOE
HZOE
HZC
OHOE
CH
CL
AS
DS
WS
CSS
AH
DH
WH
CSH
ADVS
ADSPS
ADSCS
ADVH
ADSPH
ADSCH
AS7C252MFT18A
®
–75 –85 –10
Min Max Min Max Min Max
Unit Notes
8.5–10–12– ns
–7.5–8.5–10ns
–3.5–4.0–4.0ns
2.5 – 2.5 – 2.5 – ns 2,3,4
2.5 – 2.5 – 2.5 – ns 2
0–0–0–ns2,3,4
- 3.5 – 4.0 – 4.0 ns 2,3,4
- 4.0 – 5.0 – 5.0 ns 2,3,4
0–0–0–ns
2.5 – 3.0 – 3.0 – ns 5
2.5 – 3.0 – 3.0 – ns 5
2.0 – 2.0 – 2.0 – ns 6
2.0 – 2.0 – 2.0 – ns 6
2.0 – 2.0 – 2.0 – ns 6,7
2.0 – 2.0 – 2.0 – ns 6,8
0.5 – 0.5 – 0.5 – ns 6
0.5 – 0.5 – 0.5 – ns 6
0.5 – 0.5 – 0.5 – ns 6,7
0.5 – 0.5 – 0.5 – ns 6,8
2.0 – 2.0 – 2.0 – ns 6
2.0 – 2.0 – 2.0 – ns 6
2.0 – 2.0 – 2.0 – ns 6
0.5 – 0.5 – 0.5 – ns 6
0.5 – 0.5 – 0.5 – ns 6
0.5 – 0.5 – 0.5 – ns 6
1
Snooze Mode Electrical Characteristics
Description Conditions Symbol Min Max Units
Current during Snooze Mode ZZ > V
IH
ZZ active to input ignored t
ZZ inactive to input sampled t
ZZ active to SNOOZE current t
ZZ inactive to exit SNOOZE current t
1/17/05, v 1.2 Alliance Semiconductor 10 of 19
I
SB2
PDS
PUS
ZZI
RZZI
80 mA
2cycle
2cycle
2cycle
0
Page 11
Key to switching waveforms
AS7C252MFT18A
®
Timing waveform of read cycle
CLK
Address
GWE
CE0, CE2
ADSP
ADSC
, BWE
t
ADSPS
t
t
CSS
AS
t
ADSPH
t
AH
t
WS
t
CSH
t
ADSCS
t
WH
don’t careFalling inputRising input
t
CYC
t
CH
t
ADSCH
LOAD NEW ADDRESS
A2A1 A3
t
CL
Undefined
CE1
t
ADVS
t
ADVH
ADV
ADV inserts wait states
OE
t
OE
t
LZOE
Dout
Read
Q(A1)
Q(A1)
Suspend
Read
Q(A1)
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. BW[a:d] is don’t care.
t
HZOE
Read
Q(A2)
t
OH
t
CD
Burst
Read
2Ý10
Q(A2Ý10)
Suspend
Read
)
Q(A
2Ý10
Q(A2Ý01) Q(A3Ý01)
Burst
Read
2Ý01
Q(A
)
Q(A
Q(A2Ý11)
Burst
Read
2Ý11
)
Q(A
Q(A3)
Read
Q(A3) DSEL
)
Q(A
Burst
Read
3Ý01
Q(A3Ý10)
Burst
Read
3Ý10
)
Q(A
Q(A3Ý11)
t
HZC
Burst
Read
3Ý11
)
Q(A
)
1/17/05, v 1.2 Alliance Semiconductor 11 of 19
Page 12
Timing waveform of write cycle
t
CH
CLK
t
ADSPS
t
ADSPH
ADSP
ADSC
t
AS
t
AH
Address
BWE
BW[a:b]
A1
A2
t
CYC
t
CL
®
ADSC LOADS NEW ADDRESS
A3
AS7C252MFT18A
t
ADSCS
t
ADSCH
t
WS
t
WH
CE0, CE2
CE1
ADV
OE
Din
t
CSS
Read
Q(A1)
t
CSH
D(A1)
Suspend
Write
D(A1)
ADV SUSPENDS BURST
D(A2Ý01)
Read
Q(A2)
Suspend
Write
D(A2)
D(A
ADV
Burst
Write
2Ý01
D(A2Ý10) D(A3)D(A2) D(A2Ý01) D(A3Ý01) D(A3Ý10)
Suspend
Write
2Ý01
D(A
)
D(A2Ý11)
ADV
Burst
)
Write
2Ý10
D(A
ADV
Burst
Write
)
D(A
2Ý11
Write
D(A3)
)
D(A
t
ADVS
t
Burst
Write
3Ý01
t
ADVH
DS
t
DH
ADV
Burst
Write
)
3Ý10
D(A
)
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low.
1/17/05, v 1.2 Alliance Semiconductor 12 of 19
Page 13
®
Timing waveform of read/write cycle (ADSP Controlled; ADSC High)
t
CYC
t
CL
t
AS
t
AH
A3
t
WS
t
WH
CLK
ADSP
Address
BWE
BW[a:b]
CE0, CE2
A1
t
ADSPS
t
ADSPH
t
CH
A2
AS7C252MFT18A
CE1
ADV
OE
t
DS
Din
t
CD
t
Suspend
Read
Q(A1)
HZOE
t
Dout
LZC
Read
Q(A1)
Q(A1)
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low.
Read
Q(A2)
D(A2)
t
ADVS
t
DH
t
LZOE
Suspend
Write
D(A2)
t
ADVH
t
OE
Read
Q(A3)
Q(A3)
Q(A
ADV
Burst
Read
3Ý01
t
OH
Q(A3Ý01)
)
Q(A
Q(A3Ý10) Q(A3Ý11)
ADV
Burst
Read
3Ý10
ADV
Burst
Read
)
Q(A
3Ý11
)
Suspend
Read
3Ý11
Q(A
)
1/17/05, v 1.2 Alliance Semiconductor 13 of 19
Page 14
®
Timing waveform of read/write cycle(ADSC controlled, ADSP = HIGH)
t
CYC
CLK
t
CH
t
CL
AS7C252MFT18A
ADSC
ADDRESS
BWE
BW[a:b]
CE0,CE2
CE1
OE
Dout
t
ADSCS
t
CSS
A1
t
LZOE
t
ADSCH
t
CSH
t
OE
Q(A1)
A2
Q(A2)
A3
A4
Q(A3)
t
HZOE
Q(A4)
A5
A6
t
WS
A7
t
t
AS
WH
A8
t
AH
A9
A10
t
CD
Q(A9)
Q(A10)
t
OH
Din
READ
Q(A1)
READ
Q(A2)
READ
Q(A3)
READ
Q(A4)
D(A5)
t
DS
WRITE
D(A5)
D(A6)
t
DH
WRITE
D(A6)
D(A7)
WRITE
D(A7)
D(A8)
WRITE
D(A8)
READ
Q(A9)
READ
Q(A10)
Note: ADV is don’t care here.
1/17/05, v 1.2 Alliance Semiconductor 14 of 19
Page 15
Timing waveform of power down cycle
CLK
AS7C252MFT18A
®
t
CYC
t
CH
t
CL
ADSP
ADSC
ADDRESS
BWE
BW[a:b]
CE0,CE2
CE1
ADV
OE
t
ADSPS
t
CSS
A1
t
ADSPS
t
CSH
A2
t
WS
t
WH
t
OE
t
LZOE
READ
Q(A1)
Q(A1)
t
PDS
ZZ Setup Cycle
t
ZZI
READ
Q(A1Ý01)
t
HZC
t
HZOE
t
PUS
ZZ Recovery Cycle Normal Operation Mode
t
RZZI
I
SB2
Sleep
State
READ
Q(A2)
Q(A2)
Q(A2(Ý01))
READ
Q(A2Ý01)
Dout
I
supply
Din
ZZ
1/17/05, v 1.2 Alliance Semiconductor 15 of 19
Page 16
AS7C252MFT18A
®
AC test conditions
• Output load: For t
• Input pulse level: GND to 2.5V. See Figure A.
• Input rise and fall time (measured at 0.25V and 2.25V): 2 ns. See Figure A.
• Input and output timing reference levels: 1.25V.
+2.5V
90%
10%
GND
Figure A: Input waveform
Notes
1 For test conditions, see “AC test conditions”, Figures A, B, and C.
2 This parameter is measured with output load condition in Figure C.
3 This parameter is sampled but not 100% tested.
4t
5t
6 This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must
7 Write refers to
8 Chip select refers to
is less than t
HZOE
is measured as high if above VIH, and tCL is measured as low if below VIL.
CH
meet the setup and hold times for all rising edges of CLK when chip is enabled.
GWE, BWE
LZC
LZOE
CE0, CE1
, t
90%
, and t
, and
, t
LZOE
10%
is less than t
HZC
BW[a,b].
, and
CE2
HZOE
D
.
, t
, see Figure C. For all others, see Figure B.
HZC
Z0 = 50
Ω
50
Ω
OUT
VL = V
30 pF*
Figure B: Output load (A)
at any given temperature and voltage.
LZC
DDQ
Thevenin equivalent:
+2.5V
319
D
353
OUT
Ω/1538Ω
/2
Ω/1667Ω
5 pF*
GND
*including scope
and jig capacitance
Figure C: Output load(B)
1/17/05, v 1.2 Alliance Semiconductor 16 of 19
Page 17
Package dimensions
100-pin quad flat pack (TQFP)
TQFP
Min Max
A1 0.05 0.15
A2 1.35 1.45
b 0.22 0.38
c 0.09 0.20
D 13.90 14.10
E 19.90 20.10
e 0.65 nominal
Hd 15.85 16.15
He 21.80 22.20
L 0.45 0.75
L1 1.00 nominal
α 0° 7°
Dimensions in millimeters
He
AS7C252MFT18A
®
Hd
D
b
e
E
c
L1
A1 A2
α
L
1/17/05, v 1.2 Alliance Semiconductor 17 of 19
Page 18
AS7C252MFT18A
®
Ordering information
Package & Width -75 -85 -10
TQFP x 18
Note: Add suffix ‘N’ to the above part number for Lead Free Parts (Ex. AS7C252MFT18A-85TQCN)
Part numbering guide
AS7C 25 2M FT 18 A –XX TQ C/I X
12345678910
1.Alliance Semiconductor SRAM prefix
2.Operating voltage: 25 = 2.5V
3.Organization: 2M = 2M
4.Flow-through mode
5.Organization: 18 = x 18
6.Production version: A = first production version
7.
Clock access time: [-75 = 7.5 ns;-85 = 8.5 ns; -10 = 10.0 ns]
8.Package type: TQ = TQFP
9.Operating temperature: C = commercial (
10. N = Lead free part
AS7C252MFT18A-75TQC AS7C252MFT18A-85TQC AS7C252MFT18A-10TQC
AS7C252MFT18A-75TQI AS7C252MFT18A-85TQI AS7C252MFT18A-10TQI
0° C to 70° C); I = industrial (
-40
°
C to 85° C)
1/17/05, v 1.2 Alliance Semiconductor 18 of 19
Page 19
AS7C252MFT18A
®
®
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel: 408 - 855 - 4900
Copyright © Alliance Semiconductor
All Rights Reserved
Part Number: AS7C252MFT18A
Document Version: v 1.2
Fax: 408 - 855 - 4999
www.alsc.com
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of
Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its
products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best
data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under
development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for
potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility
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