Datasheet AS7C31026-20TI, AS7C31026-20TC, AS7C31026-20JC, AS7C31026-20BC, AS7C31026-15TI Datasheet (Alliance Semiconductor Corporation)

March 2001

AS7C1026

AS7C31026

®

5V/3.3V 64K×16 CMOS SRAM

Features

• AS7C1026 (5V version)

• AS7C31026 (3.3V version)

• Industrial and commercial versions

• Organization: 65,536 words x 16 bits

• Center power and ground pins for low noise

• High speed

- 12/15/20 ns address access time

- 6,7,8 ns output enable access time

• Low power consumption: ACTIVE

- 880 mW (AS7C1026) / max @ 12 ns

- 396 mW (AS7C31026) / max @ 12 ns

Logic block diagram

A0

A1

WE

UB
OE

LB
CE

I/O0–I/O7

I/O8–I/O15

A2
A3
A4
A5
A6
A7

Row decoder

I/O

buffer

64K × 16

Array

Control circuit

Column decoder

A8

A9

A10

A11

A12

A13

A14

• Low power consumption: STANDBY

- 28 mW (AS7C1026) / max CMOS I/O

- 18 mW (AS7C31026) / max CMOS I/O

• 2.0V data retention

• Easy memory expansion with CE

, OE inputs

• TTL-compatible, three-state I/O

• JEDEC standard packaging

- 44-pin 400 mil SOJ

- 44-pin 400 mil TSOP II

- 48-ball 6 mm × 8 mm CSP mBGA

• ESD protection ≥ 2000 volts

• Latch-up current ≥ 200 mA

Pin arrangement

44-Pin SOJ, TSOP II (400 mil)

V

CC

A4

I/O0
I/O1
I/O2
I/O3

V

GND
I/O4
I/O5
I/O6
I/O7

WE
A15
A14
A13
A12

NC

A3
A2
A1
A0
CE

CC

GND

A15

44

1
2
3
4
5
6
7
8
9
10
11
12
13
14

AS7C1026

15
16
17
18
19
20
21
22

A5
A6

43

A7

42
41
40
39
38
37
36
35
34
33
32
31

AS7C31026

30
29
28
27
26
25
24
23

48-CSP mini Ball-Grid-Array Package

OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
V

CC

I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC

123456
ALB OE A
BI/O8 UB
CI/O9
DV

I/O10
I/O11

SS

EVDDI/O12
FI/O14

I/O13

A14 A15 I/O5 I/O6

A1A

0

A3 A4 CE I/O0

A5 A6 I/O1 I/O2
NC A7 I/O3 V
NC NC I/O4 V

G I/O15 NC A12 A13 WE I/O7
HNC A8 A9A10A11NC

NC

2

DD

SS

Selection guide

AS7C1026-12

AS7C31026-12

Maximum address access time 12 15 20 ns

Maximum output enable access time 6 8 10 ns

AS7C1026 160 150 140 mA

Maximum operating current

AS7C31026 110 100 90 mA

AS7C1026 10 10 15 mA

Maximum CMOS standby current

AS7C31026 10 10 15 mA

Shaded areas indicate preliminary information.

3/23/01; v.1.0 Alliance Semiconductor P. 1 of 10

AS7C1026-15

AS7C31026-15

AS7C1026-20

AS7C31026-20 Unit

Copyright © Alliance Semiconductor. All rights reserved.

AS7C1026

AS7C31026

®

Functional description

The AS7C1026 and AS7C31026 are high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices
organized as 65,536 words x 16 bits. They are designed for memory applications where fast data access, low power, and simple
interfacing are desired.

Equal address access and cycle times (t
for high-performance applications.

When CE

is high the devices enter stanby mode. The AS7C1026 is guaranteed not to exceed 28 mW power consumption in

CMOS standby mode. The devices also offer 2.0V data retention.

A write cycle is accomplished by asserting write enable (WE
written on the rising edge of WE

(write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/

O pins only after outputs have been disabled with output enable (OE

A read cycle is accomplished by asserting output enable (OE
I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write
enable is active, output drivers stay in high-impedance mode.

The devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be
written and read. LB

controls the lower bits, I/O0–I/O7, and UB controls the higher bits, I/O8–I/O15.

All chip inputs and outputs are TTL-compatible, and operation is from a single 5V supply (AS7C1026) or 3.3V supply
(AS7C31026). the device is packaged in common industry standard packages. Chip scale BGA packaging, easy to use in
manufacturing, provides the smallest possible footprint. This 48-ball JEDEC-registered package has a ball pitch of 0.75 mm and
external dimensions of 8 mm × 6 mm.

, tRC, tWC) of 12/15/20 ns with output enable access times (tOE) of 6,7,8 ns are ideal

AA

) and chip enable (CE). Data on the input pins I/O0–I/O15 is

) or write enable (WE).

) and chip enable (CE), with write enable (WE) high. the chips drive

Absolute maximum ratings

Parameter Symbol Min Max Unit

Vol tage on V

relative to GND

CC

AS7C31026 V

Voltage on any pin relative to GND V

Power dissipation P

Storage temperature (plastic) T

Ambient temperature with VCC applied T

DC current into outputs (low) I

Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.

AS7C1026 V

t1

t1

t2

D

stg

bias

OUT

–0.50 +7.0 V

–0.50 +5.0 V

–0.50 VCC +0.50 V

–1.0W

–65 +150 °C
–55 +125 °C

–20mA

Truth table

CE

H X X X X High Z High Z Standby (I

LHLLHD

LHLHLHigh ZD

LHLLLD

LLXLL D

LLXLHD

WE OE LB UB I/O0–I/O7 I/O8–I/O15 Mode

OUT

OUT

IN

IN

High Z Read I/O0–I/O7 (ICC)

Read I/O8–I/O15 (I

Read I/O0–I/O15 (ICC)

Write I/O0–I/O15 (ICC)

D

OUT

OUT

D

IN

High Z Write I/O0–I/O7 (ICC)

), I

)

SB

SBI

CC)

3/23/01; v.1.0 Alliance Semiconductor P. 2 of 10

AS7C1026

AS7C31026

®

CE

WE OE LB UB I/O0–I/O7 I/O8–I/O15 Mode

LLXHLHigh ZDINWrite I/O8–I/O15 (ICC)

L
L

Key: H = High, L = Low, X = don’t care.

H
X

H
X

X

H

X
H

High Z High Z Output disable (I

Recommended operating conditions

Parameter Device Symbol Min Typ Max Unit

AS7C1026 V

Supply voltage

AS7C31026 (–10) V

AS7C31026 (12/15/20) V

AS7C1026 V

Input voltage

AS7C31026 V

commercial T

Ambient operating temperature

industrial T

†

VIL min = –3.0V for pulse width less than tRC/2.

DC operating characteristics (over the operating range)

Parameter Sym Test conditions Device

Input leakage
current

Output leakage
current

Operating power
supply current

Standby

| I

|

LI

|

| I

LO

I

CC

I

SB

power supply
current

I

SB1

Output
voltage

Shaded areas indicate preliminary information.

V

OL

V

OH

V

V

= Max

CC

V

= GND to V

IN

V

= Max

CC

CE

= VIH,

V

= GND to V

OUT

V

= Max, CE ≤ V

CC

CC

CC

IL

AS7C1026 – 160 – 150 – 140 mA

outputs open,

f = f

Max

= 1/t

VCC = Max, CE

RC

≤ V

,

IL

AS7C31026 – 110 – 100 – 90 mA

AS7C1026 – 50 – 50 – 50

outputs open,

f = f

Max

= Max, CE ≥ V

CC

V

≤ GND + 0.2V or

IN

V

≥ V

IN

CC

= 1/t

RC

–0.2V,

CC

–0.2V, f = 0

AS7C31026 – 35 – 35 – 35

AS7C1026 – 10 – 10 – 15

AS7C31026 – 10 – 10 – 15

IOL = 8 mA, VCC = Min – 0.4 – 0.4 – 0.4 V

IOH = –4 mA, VCC = Min 2.4 – 2.4 – 2.4 – V

CC

CC

CC

IH

IH

V

IL

A

A

1

-12 -15 -20

–1–1 –1µA

–1–1 –1µA

4.5 5.0 5.5 V

3.15 3.3 3.6 V

3.0 3.3 3.6 V

2.2 – VCC + 0.5 V

2.0 – VCC + 0.5 V

†

–0.5

–0.8 V

0– 70 °C

–40 – 85 °C

CC

)

UnitMin Max Min Max Min Max

mA

mA

Capacitance (f = 1MHz, T

= 25 °C, V

a

= NOMINAL)

CC

2

Parameter Symbol Signals Test conditions Max Unit

Input capacitance C

I/O capacitance C

3/23/01; v.1.0 Alliance Semiconductor P. 3 of 10

IN

I/O

A, CE, WE, OE, LB, UB VIN = 0V 5 pF

I/O VIN = V

= 0V 7 pF

OUT

AS7C1026

AS7C31026

®

Read cycle (over the operating range)

Parameter Symbol

Read cycle time t

Address access time t

Chip enable (CE

Output enable (OE

Output hold from address change t

Low to output in low Z t

CE

CE

High to output in high Z t

Low to output in low Z t

OE

Byte select access time t

Byte select Low to low Z t

Byte select High to high Z t

OE

High to output in high Z t

Power up time t

Power down time t

Shaded areas indicate preliminary information.

) access time t

) access time t

3,9

RC

AA

ACE

OE

OH

CLZ

CHZ

OLZ

BA

BLZ

BHZ

OHZ

PU

PD

-12 -15 -20

Unit NotesMin Max Min Max Min Max

12 – 15 – 20 – ns

–12–15–20ns 3

–12–15–20ns 3

–6–7–8ns

4–4–4–ns 5

0–0–0–ns4, 5

–6–6–8ns4, 5

0–0–0–ns4, 5

–6–7–8ns

0–0–0–ns4,5

–6–6–8ns4,5

–6–6–8ns4, 5

0–0–0–ns4, 5

–12–15–20ns 4, 5

Key to switching waveforms

Read waveform 1 (address controlled)

Address

t

OH

Data

OUT

3,6,7,9

Read waveform 2 (OE, CE, UB, LB controlled)

Address

OE

t

OLZ

CE

t

LZ

LB, UB

t

BLZ

Data

IN

t

AA

3,6,8,9

t

AA

t

ACE

Undefined output/don’t careFalling inputRising input

t

RC

t

OH

Data validPrevious data valid

t

RC

t

OE

t

BA

t

OH

t

OHZ

t

HZ

t

BHZ

Data valid

3/23/01; v.1.0 Alliance Semiconductor P. 4 of 10

AS7C1026

AS7C31026

®

Write cycle (over the operating range)

11

Parameter Symbol

Write cycle time t

Chip enable (CE

) to write end t

Address setup to write end t

Address setup time t

Write pulse width t

Address hold from end of write t

Data valid to write end t

Data hold time t

Write enable to output in high Z t

Output active from write end t

Byte select low to end of write t

Shaded areas indicate preliminary information.

Write waveform 1 (WE controlled)

Address

CE

LB, UB

WE

Data

IN

Data

OUT

Write waveform 2 (CE controlled)

Address

t

AS

CE

LB, UB

WE

Data

IN

t

CLZ

Data

OUT

high Z high Z

10,11

t

AS

Data undefined

10,11

Data undefined

WC

CW

AW

AS

WP

AH

DW

DH

WZ

OW

BW

-12 -15 -20

Unit NotesMin Max Min Max Min Max

12 – 15 – 20 – ns

8 – 12 – 13 – ns

9 – 10 – 12 – ns

0–0–0– ns

8 – 10 – 12 – ns

0–0–0– ns

6–8–10– ns

0–0–0– ns 5

–6–6–8 ns 4, 5

1–1–2– ns 4, 5

8–9–12– ns

t

WC

t

t

DH

high Z

t

DH

t

t

OW

t

OW

WR

WR

t

CW

t

BW

t

AW

t

WP

t

DW

Data valid

t

WZ

t

WC

t

CW

t

AW

t

BW

t

WP

t

DW

Data valid

t

WZ

3/23/01; v.1.0 Alliance Semiconductor P. 5 of 10

AS7C1026

AS7C31026

®

Data retention characteristics (over the operating range)

Parameter Symbol Test conditions Min Max Unit

V

for data retention V

CC

Data retention current I

Chip deselect to data retention time t

Operation recovery time t

Input leakage current |I

DR

CCDR

CDR

R

|–1µA

LI

V

Data retention waveform

Data retention mode

V

CC

CE

V

CC

t

CDR

V

IH

V

DR

AC test conditions

- Output load: see Figure B or Figure C, except as noted.

- Input pulse level: GND to 3.0V. See Figure A.

- Input rise and fall times: 2 ns. See Figure A.

- Input and output timing reference levels: 1.5V.

13

VCC = 2.0V

CE

≥ V

≥ V

IN

V

≤ 0.2V

IN

≥

2.0V

V

DR

+5V

–0.2V

CC

–0.2V or

CC

2.0 – V

t

V

CC

V

IH

Thevenin Equivalent:

D

OUT

168W

–1 ma

0–ns

RC

t

R

+1.728V (5V and 3.3V)

+3.3V

–ns

D

+3.0V

GND

90%

10%

2 ns

Figure A: Input pulse

90%

10%

OUT

255W C(14)

GND

Figure B: 5V Output load

Notes

1During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.
2 This parameter is sampled, but not 100% tested.
3 For test conditions, see AC Test Conditions, Figures A, B, and C.

480W

4 These parameters are specified with C
5 This parameter is guaranteed, but not tested.
6WE

is High for read cycle.

7CE

and OE are Low for read cycle.
8 Address valid prior to or coincident with CE
9 All read cycle timings are referenced from the last valid address to the first transitioning address.
10 CE

or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 Not applicable.
13 2V data retention applies to commercial temperature range operation only.
14 C=30pF, except all high Z and low Z parameters where C=5pF.

= 5pF, as in Figures B or C. Transition is measured ± 500 mV from steady-state voltage.

L

transition Low.

D

OUT

255W

C(14)

GND

Figure C: 3.3V Output load

320W

3/23/01; v.1.0 Alliance Semiconductor P. 6 of 10

Typical DC and AC characteristics

AS7C1026

AS7C31026

®

Normalized supply current ICC, I

vs. supply voltage V

1.4

1.2
I

SB

1.0

, I

CC

0.8

CC

0.6
I

0.4

Normalized I

SB

0.2

0.0

MIN

NOMINAL

Supply voltage (V)

Normalized access time t

vs. supply voltage V

1.5

1.4

T

= 25° C

a

1.3

1.2

1.1

SB

CC

Normalized supply current ICC, I

vs. ambient temperature T

1.4

SB

a

1.2
I

SB

1.0

, I

CC

0.8

CC

0.6
I

0.4

Normalized I

SB

0.2

Normalized supply current I

vs. ambient temperature T

625

VCC = VCC(NOMINAL)

25

5

1

0.2

0.04

Normalized ISB1 (log scale)

SB1
a

0.0

MAX

–55 80

Ambient temperature (°C)

AA

CC

Normalized access time t

vs. ambient temperature T

1.5

35–10

125

-55 80

35-10

125

Ambient temperature (°C)

AA

a

Normalized supply current I

vs. cycle frequency 1/tRC, 1/t

1.4

CC

WC

VCC = VCC(NOMINAL)

1.4

VCC = VCC(NOMINAL)

1.3

1.2

1.1

1.2

1.0

0.8

0.6

T

= 25° C

a

125

Normalized ICC

0.4

0.2

0.0
075

Cycle frequency (MHz)

Typical access time change ∆t

vs. output capacitive loading

35

30

VCC = VCC(NOMINAL)

25

1.0

Normalized access time

0.9

0.8
MIN

Supply voltage (V)

Output source current I

vs. output voltage V

140

VCC = VCC(NOMINAL)

120

T

= 25° C

a

100

NOMINAL

OH

OH

MAX

1.0

Normalized access time

0.9

0.8
–55 80

35–10

Ambient temperature (°C)

Output sink current I

vs. output voltage V

140

VCC = VCC(NOMINAL)

120

T

= 25° C

100

a

OL

OL

(ns)

80

60

40

20

Output source current (mA)

0

0 750

V

Output voltage (V)

80

60

40

Output sink current (mA)

20

0

CC

00

V

Output voltage (V)

20

AA

15

10

Change in t

5

0

CC

Capacitance (pF)

5025

500250

100

AA

1000

3/23/01; v.1.0 Alliance Semiconductor P. 7 of 10

Package dimensions

AS7C1026

AS7C31026

®

444342414039 383736 353433 32 31

44-pin TSOP II

1 2 3 4 5 6 7 8 9 10 11121314

D

A

A1

b

e

D

e

44-pin SOJ

Pin 1

B

A

1

b

3029

1516

Seating

Plane

2827 2625

1718 1920

A

E

212422

1

A2

E

23

He

E

c

44-pin TSOP II

Min

(mm)

Max

(mm)

A1.2

A1 0.05

A2 0.95 1.05

b

0.30

0.45

c 0.127 (typical)

D 18.28 18.54

10.03

E

10.29

0–5

l

°

He 11.56 11.96

e0.80 (typical)

l 0.40 0.60

44-pin SOJ

400 mL

Min Max

2

c

A

2

A 0.128 0.148
A
A

0.025 –

1

1.105 1.115

2

B 0.026 0.032

b 0.015 0.020

c 0.007 0.013

E

2

D 1.120 1.130

E 0.370 NOM

E
E

0.395 0.405

1

0.435 0.445

2

e 0.050 NOM

3/23/01; v.1.0 Alliance Semiconductor P. 8 of 10

48-ball FBGA

AS7C1026

AS7C31026

®

Bottom View

654321

A

B

C

D

F

G

H

J

A

B1

Ball A1

C1

Top V i ew

Ball #A1 index

SRAM DIE

B

C

Elastomer

E2

Detail View

A

Die

Y

0.3/T

µ

p

Side View

E2

E

E1

D

E

Die

Minimum Typical Maximum

A–0.75–

B 5.90 8.00 8.10

B1 – 3.75 –

C 7.90 8.00 8.10

C1 – 5.25 –

D–0.35–

E––1.20

E1 – 0.68 –

E2 0.22 0.25 0.27

Notes
1 Bump counts: 48 (8 row x 6 column).
2 Pitch: (x,y) = 0.75 mm x 0.75 mm (typ).
3 Units: millimeters.
4 All tolerance are +/- 0.050 unless otherwise

specified. 5 Typ: typical. 6 Y is coplanarity: 0.08 (max).

Y––0.08

3/23/01; v.1.0 Alliance Semiconductor P. 9 of 10

®

Ordering codes

Package \ Access time Volt/Temp 12 ns 15 ns 20 ns

5V commercial AS7C1026-12JC AS7C1026-15JC AS7C1026-20JC

Plastic SOJ, 400 mil

5V industrial AS7C1026-12JI AS7C1026-15JI AS7C1026-20JI

3.3V commercial AS7C31026-12JC AS7C31026-15JC AS7C31026-20JC

5V commercial AS7C1026-12TC AS7C1026-15TC AS7C1026-20TC

TSOP II, 18.4×10.2 mm

3.3V commercial AS7C31026-12TC AS7C31026-15TC AS7C31026-20TC

3.3V industrial AS7C31026-12TI AS7C31026-15TI AS7C31026-20TI

5V commercial AS7C1026-12BC AS7C1026-15BC AS7C1026-20BC

CSP BGA, 8×6 mm

3.3V commercial AS7C31026-12BC AS7C31026-15BC AS7C31026-20BC

3.3V industrial AS7C31026-12BI AS7C31026-15BI AS7C31026-20BI

NA: not available.

Shaded areas indicate preliminary information.

Part numbering system

AS7C X 1026 –XX X C

SRAM
prefix

Blank=5V CMOS

3=3.3V CMOS

Device

number

Access

time

Package: J=SOJ 400 mil

T=TSOP type 2, 18.4 × 10.2 mm

B=CSP BGA, 8 × 6 mm

Te m pe rat ur e r an ge,

C=Commercial: 0° C to 70° C

I=Industrial: -40° C to 85° C

AS7C1026

AS7C31026

3/23/01; v.1.0 Alliance Semiconductor P. 10 of 10

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