Datasheet AS7C1025B Datasheet (Alliance Semiconductor)

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March 2004

5V 128K X 8 CMOS SRAM (Center power and ground)

Features

• Industrial and commercial temperatures

• Organization: 131,072 x 8 bits

• High speed

- 10/12/15/20 ns address access time

- 5/6/7/8 ns output enable access time

• Low power consumption: ACTIVE

- 605mW / max @ 10 ns

• Low power consumption: STANDBY

- 55 mW / max CMOS

• 6 T 0.18 u CMOS technology

• Easy memory expansion with

• Center power and ground

• TTL/LVTTL-compatible, three-state I/O

Logic block diagram

GND

Input buffer

A0 A1 A2 A3 A4 A5 A6 A7 A8

512 x 256 x 8

Array

(1,048,576)

Row decoder

CE, OE

inputs

Sense amp

I/O7

I/O0

• JEDEC-standard packages

- 32-pin, 300 mil SOJ

- 32-pin, 400 mil SOJ

• ESD protection ≥ 2000 volts

• Latch-up current ≥ 200 mA

Pin arrangement

32-pin SOJ (300 mil) 32-pin SOJ (400 mil)

A0 A1

A2 A3

CE I/O0 I/O1 V

GND

I/O2 I/O3

A4 A5 A6 A7

AS7C1025B

1 2

3 4 5 6 7

8 9 10

AS7C1025B

11 12 13 14 15

A16

A15

A14

A13

29 28

OE I/O7

27 26

I/O6

GND V

I/O5

I/O4

A12 A11

20 19

A10 A9

18 17

OE CE

Column decoder

A1 1

A10

A12

A13

A14

A15

Control

circuit

A16

Selection guide

-10 -12 -15 -20 Unit

Maximum address access time 10 12 15 20 ns Maximum output enable access time 5 6 7 8 ns Maximum operating current 110 100 90 80 mA Maximum CMOS standby current 10 10 10 10 mA

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AS7C1025B

Functional description

The AS7C1025B is a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices organized as 131,072 x 8 bits. They are designed for memory applications where fast data access, low power , and simple interfacing are desired.

Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5/6/7/8 ns are ideal for highperformance applications. The chip enable input CE

When CE standby power is reached (I

A write cycle is accomplished by asserti ng write enable ( the rising edge of outputs have been disabled with output enable (

A read cycle is accomplished by asserting output enable ( with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output drivers stay in high-impedance mode.

All chip inputs and outputs are TTL-compatible, and operation is from a single 5 V supply. The AS7C1025B is packaged in common industry standard packages.

is high, the device enters standby mode. If inputs are still toggling, the device will consume ISB power. If the bus is static, then full

). For example, the AS7C1026B is guaranteed not to exceed 55 mW under nominal full standby conditions.

SB1

(write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after

permits easy memory and expansion with multiple-bank memory systems.

) and chip enable (CE). Data on the input pins I/O0 through I/O7 is written on

) or write enable (

) and chip enable (CE), with write enable (WE) high. The chips drive I/O pins

Absolute maximum ratings

Parameter Symbol Min Max Unit

Voltage on V Voltage on any pin relative to GND V Power dissipation P Storage temperature (plastic) T Ambient temperature with V DC current into outputs (low) I

NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

relative to GND V

applied T

t1 t2 D

stg

bias

OUT

–0.50 +7.0 V –0.50 VCC + 0.5 V

–1.0W –65 +150 –55 +125

–20mA

Truth table

CE WE OE

H X X High Z Standby (I L H H High Z Output disable (I LHL D LLX D

Key: X = don’t care, L = low, H = high.

Data Mode

OUT

Read (ICC)

Write (ICC)

, I

SB1

)

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Recommended operating conditions

Parameter Symbol Min Nominal Max Unit

Supply voltage V

Input voltage

Ambient operating temperature

VIL min = -1.0V for pulse width less than 5ns V

max = VCC+2.0V for pulse width less than 5ns.

commercial T

industrial T

AS7C1025B

IL A A

4.5 5.0 5.5 V

2.2 – VCC + 0.5 V

–0.5 – 0.8 V

0–70o C

–40 – 85

DC operating characteristics (over the operating range)

Parameter Symbol Test co nditio ns

Input leakage current | ILI | VCC = Max, VIN = GND to V Output leakage

current Operating power

supply current Standby power supply

current

Output voltage

| I

SB1

OHIOH

= Max, CE = VIH,

= GND to V

out

VCC = Max

≤ VIL, f = f

CE VCC = Max

≥ VIH, f = f

CE VCC = Max

≥ VCC–0.2 V,

CE VIN ≤ 0.2 V or VIN ≥ VCC –0.2 V, f = 0

IOL = 8 mA, VCC = Min – 0.4 – 0.4 – 0.4 – 0.4 V

= –4 mA, VCC = Min 2.4 2.4 – 2.4 – 2.4 – V

Max, IOUT

Max

Capacitance (f = 1 MHz, T

Parameter Symbol Signals Test conditions Max Unit

Input capacitance C I/O capacitance C

= 25o C, VCC = NOMINAL)

I/O

= 0 mA

A, CE, WE,

–1–1–1–1µA

– 110 – 100 – 90 – 80 mA

–50–45–45–40mA

–

I/O VIN = V

-10 -12 -15 -20

10 10 10 10 mA

VIN = 0 V 5 pF

= 0 V 7 pF

OUT

UnitMin Max Min Max Min Max Min Max

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AS7C1025B

Read cycle (over the operating range)

Parameter Symbol

Read cycle time t Address access time t Chip enable ( Output enable (

) access time t

) access time t Output hold from address change t CE

low to output in low Z t

low to output in high Z t

low to output in low Z t

high to output in high Z t Power up time t Power down time t

RC AA

ACE

OE OH

CLZ

CHZ

OLZ

OHZ

PU PD

Key to switching waveforms

Read waveform 1 (address controlled)

ddress

OUT

3,9

-10 -12 -15 -20 Unit NotesMin Max Min Max Min Max Min Max

10 - 12 – 15 – 20 – ns

- 10 – 12 – 15 – 20 ns 3

-5–6–7–8 ns 3 - 3 – 3 – 3 – ns 5 3 - 3 – 3 – 3 – ns 4, 5

- 4 – 5 – 6 – 7 ns 4, 5 0 - 0 – 0 – 0 – ns 4, 5

- 10 – 12 – 15 – 20 ns 4, 5

Undefined/don’t careFalling inputRising input

3,6,7,9

Data valid

Read waveform 2 (CE and OE controlled)

OUT

Supply

current

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ACE

CLZ

RC1

OLZ

50% 50%

3,6,8,9

Data valid

OHZ

CHZ

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AS7C1025B

Write cycle (over the operating range)

Parameter Symbol

Write cycle time t Chip enable (

) to write end t Address setup to write end t Address setup time t Write pulse width t Write recovery time t Address hold from end of write t Data valid to write end t Data hold time t Write enable to output in high Z t Output active from write end t

Write waveform 1 (WE controlled)

Address

OUT

WC CW AW

AS WP WR AH DW DH WZ OW

10,11

-10 -12 -15 -20 Unit NotesMin Max Min Max Min Max Min Max

10 - 12 – 15 – 20 – ns

8-9–10–12– ns 8-9–10–10– ns 0-0–0–0– ns 7 - 8 – 9 – 12 – ns 0-0–0–0– ns 0-0–0–0– ns 5 - 6 – 8 – 10 – ns 0 - 0 – 0 – 0 – ns 4, 5

- 5 – 6 – 7 – 8 ns 4, 5

1 - 1 – 1 – 2 – ns 4, 5

Data valid

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AS7C1025B

Write waveform 2 (CE controlled)

Address

OUT

AC test conditions

– Output load: see Figure B. – Input pulse level: GND to 3.5 V. See Figure A. – Input rise and fall times: 2 ns. See Figure A. – Input and output timing reference levels: 1.5 V.

+3.5 V

GND

90%

10%

2 ns

Figure A: Input pulse

90%

10%

10,11

Data valid

OUT

255

Ω

Figure B: 5 V Output load

+5 V

480

C GND

Ω

Thevenin equivalent:

168

OUT

Ω

+1.728 V

Notes

1 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification. 2 This parameter is sampled, but not 100% tested. 3 For test conditions, see AC Test Conditions, Figures A and B. 4t

and t

CLZ

5 This parameter is guaranteed, but not 100% tested. 6

is high for read cycle.

and OE are low for read cycle. 8 Address is valid prior to or coincident with 9 All read cycle timings are referenced from the last valid address to the first transitioning address. 10 N/A 11 All write cycle timings are referenced from the last valid address to the first transitioning address. 12 N/A. 13 C = 30 pF, except all high Z and low Z parameters where C = 5 pF .

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are specified with CL = 5 pF, as in Figure B. Transition is measured ±500 mV from steady-state voltage.

CHZ

transition low.

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Package dimensions

AS7C1025B

32-pin SOJ 300 mil/400 mil

Pin 1

Symbol

32-pin SOJ

300 mil

Min Max Min Max

32-pin SOJ

400 mil

A 0.128 0.145 0.132 0.146

A1 0.025 - 0.025 -

A2 0.095 0.105 0.105 0.115

B 0.026 0.032 0.026 0.032

b 0.016 0.020 0.015 0.020 c 0.007 0.010 0.007 0.013

Seating

plane

D 0.820 0.830 0.820 0.830

E 0.255 0.275 0.354 0.378 E1 0.295 0.305 0.395 0.405 E2 0.330 0.340 0.435 0.445

e 0.050 BSC 0.050 BSC

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AS7C1025B

Ordering Codes

Package \

Access time

300-mil SOJ Commercial AS7C1025B-10TJC AS7C1025B-12TJC AS7C1025B-15TJC AS7C1025B-20TJC

400-mil SOJ Commercial AS7C1025B-10JC AS7C1025B-12JC AS7C1025B-15JC AS7C1025B-20JC

Note: Add suffix ‘N’ to the above part number for LEAD FREE parts. (Ex AS7C1025B-10TJCN)

Part numbering system

AS7C 1025B –XX X X X

SRAM

prefix

Temperature 10 ns 12 ns 15 ns 20 ns

Industrial AS7C1025B-10TJI AS7C1025B-12TJI AS7C1025B-15TJI AS7C1025B-20TJI

Industrial AS7C1025B-10JI AS7C1025B-12JI AS7C1025B-15JI AS7C1025B-20JI

Device number Access time

Package:

TJ = SOJ 300 mil

J = SOJ 400 mil

Temperature range

C = commercial, 0° C to 70° C

I = industrial, -40° C to 85° C

N = LEAD FREE

PART

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AS7C1025B

Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Te l: 408 - 855 - 4900

Fax: 408 - 855 - 4999 www.alsc.com

trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.