Page 1
October 2000
AS6VA5128
®
2.7V to 3.3V 512K × 8 Intelliwatt™ low-power CMOS SRAM
Features
• AS6VA5128
• Intelliwatt™ active power circuitry
• Indust ri al and commerci al temperature ranges availabl e
• Organization: 524,288 words × 8 bits
• 2.7V to 3.3V at 55 ns
• Low power consumption: ACTIVE
- 132 mW at 3.3V and 55 ns
• Low power consumption: STANDBY
-66 µW max at 3.3V
Logic block diagram
V
CC
GND
Input buffer
A0
A1
A2
A3
A4
A5
A6
A7
A8
Row decoder
Column decoder
A9
512K × 8
Array
(4,194,304)
A10
A11
A12
A13
Sense amp
Control
circuit
A14
A15
A16
I/O8
I/O1
WE
OE
CS
• 1.2V data retention
• Equ al access and cycl e tim es
• Easy memory expansion with CS
, OE inputs
• Smallest footprint packages
- 36(48)-ball FBGA
- 32-pin TSO P I a n d TSOP II pack ag e s ar e availabl e on
Alliance AS6UB5128 product family (available January
2001)
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
48-CSP BGA Package
123456
AA
BI/O5A
CI/O
DV
EV
FI/O
GI/O8OE CS A
HA9A
0
6
SS
CC
7
(shading indicates no ball)
A
1
2
NC A
WE A
NC A
10
A
A
A
18
A
11
17
16
12
A
3
4
5
6
A
7
A
15
A
13
A
I/O
I/O
V
V
I/O
I/O
A
8
1
2
CC
SS
3
4
14
Selection guide
V
Range
CC
Product
Min
(V)
Typ
(V)
2
Max
(V)
Speed
(ns)
Operating (I
Max (mA) Max (
AS6VA5128 2.7 3.0 3.3 55 2 20
10/6/00 ALLIANCE SEMICONDUCTOR 1
Power Dissipation
) Standby (I
CC
Copyright ©2000 Alliance Semiconductor. All rights reserved.
)
SB1
A)
µµµµ
Page 2
AS6VA5128
®
Functional description
The AS6VA5128 is a low-power CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as
524,288 words × 8 bits. It is designed for memory applications where slow data access, low power, and simple interfacing
are desired.
Equal address access and cycle times (t
selects (CS
When CS
) permit easy memory expansion with multiple-bank memory systems.
is high, the device enters standby mode: the AS6VA5128 is guarante ed n ot to exc eed 66 µW power consumption
at 3.3V and 55ns. The device also returns data when V
A write cycle is accomplished by asserting write ena ble (WE
written on the rising edge of WE
(write cycle 1) or CS (write cycle 2). To avoid bus con tention, external devices should drive
I/O pins only after outputs have been disabled with output enable (OE
A read cycle is accomplished by asserting output enable (OE
drives I/O pins with the data word referenced by the input address. When either chip select or output enable is inactive, or
write enable i s acti ve, output drivers stay in high-im pedance mode.
All chip inputs and outputs are CMOS-compatible, and operation is from a single 2.7V to 3.3V supply. The device is
available in the JEDEC standard 36(48)-ball FBGA package.
Absolute maximum ratings
Parameter Device Symbol Min Max Unit
Voltage on V
Voltage on any I/O pin relative to GND V
Power dissipation P
Storage temperature (plastic) T
Tempe rature with V
DC output current (low) I
Note: Stresse s greater than th ose listed under A bsolute Maximu m Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
relative to V
CC
CC
SS
applied T
, tRC, tWC) of 55 ns are ideal for low-power applications. Active high and low chip
AA
is reduced to 1.5V for even lower power consumption.
CC
) and ch ip select (CS ) low. Data on the input pins I/O1–I/O8 is
) or write enable (WE).
), chi p select (CS), wi th write enabl e (WE) High. The chip
V
tI/O
bias
OUT
tIN
D
stg
–0.5 VCC + 0.5 V
–0.5 V
–1.0W
–65 +150 °C
–55 +125 °C
–20mA
Truth table
CS
HXXI
LXXI
LHHI
LHLI
LLXI
Key: X = Don’t care, L = Low, H = High.
WE OE Supply Current I/O1–I/O8 Mode
2
SB
SB
CC
CC
CC
High Z Standby (ISB)
High Z Standby (ISB)
High Z Output disable (ICC)
D
OUT
D
IN
ALLIANCE SEMICONDUCTOR
Read (ICC)
Write (ICC)
10/6/00
Page 3
AS6VA5128
®
Recommended operating condition (over the operating range)
Param eter Descr ip t ion Test Cond itions Min Max Unit
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
CC1
1MHz
Output HIGH Voltage IOH = –2.1mA VCC = 2.7V 2.4 V
Output LOW Voltage IOL = 2.1mA VCC = 2.7V 0.4 V
Input HIGH Voltage VCC = 2.7V 2.2 VCC + 0.5 V
Input LOW Voltage VCC = 2.7V –0.5 0.8 V
Input Load Current GND < VIN < V
Output Load Current GND < VO < VCC; Outputs High Z –1 +1 µA
VCC Operating Supply
Average V
@
Supply Current at 1
Current
Operating
CC
MHz
CS
I
= 0mA, f = 0,
OUT
V
= VIL or V
IN
CS
< 0.2V, V
or V
IN
= VIL,
IH
<
IN
0.2V,
> VCC – 0.2V,
f = 1 mS
CC
–1 +1 µA
VCC = 3.3V 2 mA
= 3.3V 5 mA
V
CC
I
CC2
I
SB
I
SB1
I
SBDR
Average VCC Operating
Supply Current
CS Power Down
Current; TTL Inputs
CS Power Down
Current; CMOS Inputs
Data Retention
CS ≠ VIL, VIN = VIL
or V
, f = f
IH
Max
CS > VIH, other i nputs
= 0V – V
CS
> VCC – 0.2V,
CC
other inputs = 0V –
V
, f = f
CC
CS
> VCC – 0.1V,
Max
f = 0
V
= 3.3V (55 ns) 40 mA
CC
VCC = 3.3V 100 µA
VCC = 3.3V 20 µA
V
= 1.2V 2 µA
CC
Capacitance (f = 1 MHz, Ta = Room temperature, VCC = NOMINAL)2
Parameter Symbol Signals Test conditions Max Unit
Input capacitance C
I/O capacitance C
IN
I/O
A, CS, WE, OE VIN = 0V 5 pF
I/O VIN = V
= 0V 7 pF
OUT
10/6/00
ALLIANCE SEMICONDUCTOR
3
Page 4
AS6VA5128
®
Read cycle (over the operating range)
3,9
Parameter Symbol Min Max Unit Notes
Read cycle time t
Address access time t
Chip select (CS
Output enable (OE
) acces s time t
) access tim e t
Output hold from address change t
low to output in low Z t
CS
CS
high to output in high Z t
OE
low to output in low Z t
high to output in high Z t
OE
Power up time t
Power down time t
Key to switching waveforms
Read waveform 1 (address controlled)
Address
D
OUT
3,6,7,9
t
OH
t
AA
RC
AA
ACS
OE
OH
CLZ
CHZ
OLZ
OHZ
PU
PD
55 – ns
–55ns3
–55ns3
–25ns
10 – ns 5
10 – ns 4, 5
020ns4, 5
5 – ns 4, 5
020ns4, 5
0 – ns 4, 5
–55ns4, 5
Undefined/don’t careFalling inputRising input
t
RC
t
OH
Data validPrevious da ta valid
Read waveform 2 (CS, OE controlled)
t
RC1
CS
t
OE
OE
t
OLZ
t
ACE
D
OUT
t
CLZ
Supply
current
4
t
PU
50% 50%
ALLIANCE SEMICONDUCTOR
3,6,8,9
t
OHZ
t
CHZ
Data valid
t
PD
I
CC
I
SB
10/6/00
Page 5
AS6VA5128
®
Writ e cycle (ove r the operating range)
11
Parameter Symbol Min Max Unit Notes
Write cycle time t
Chip select to write end t
Address setup to write end t
Address setup time t
Write pulse width t
Address hold from end of write t
Data valid to write end t
Data hold time t
Write enable to output in high Z t
Output acti ve from write end t
Write waveform 1 (WE controlled)
Address
WE
t
AS
D
IN
10,11
t
WZ
t
t
AW
WC
WC
CW
AW
AS
WP
AH
DW
DH
WZ
OW
t
WP
55 – ns
40 – ns 12
40 – ns
0–ns12
35 – ns
0–ns
25 – ns
0–ns4, 5
020ns4, 5
5–ns4, 5
t
AH
t
OW
t
DH
t
DW
Data valid
D
OUT
Write waveform 2 (CS controlled)
Address
t
AS
CS
WE
IN
D
OUT
10,11
t
WZ
t
AW
t
CW
t
t
WC
WP
t
DW
Data vali dD
t
AH
t
DH
10/6/00
ALLIANCE SEMICONDUCTOR
5
Page 6
AS6VA5128
®
Data retention characteristics (over the operating range)
Parameter Symbol Test conditions Min Max Unit
for data retention V
V
CC
Data retention curre nt I
Chip deselect to data reten tion time t
Operation recovery time t
DR
CCDR
CDR
R
VCC = 1.2V
CS
≥ VCC – 0.1V or
V
≥ VCC – 0.1V or
IN
V
≤ 0.1V
IN
Data retention waveform
Data retentio n mode
V
CC
CS
V
CC
t
CDR
V
IH
VDR ≥ 1.2V
V
AC test loads and waveforms
V
CC
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
R1
(a)
V
OUTPUT
R2
INCLUDING
JIG AND
SCOPE
R1
CC
5 pF
(b)
DR
13,5
R2
1.2V 3.3 V
–4µA
0–ns
t
RC
OUTPUT
Typ
V
CC
GND
V
CC
t
R
V
IH
The venin equivalent:
ALL IN PU T PU L SES
90%
10%
–ns
R
TH
< 5 ns
(c)
V
90%
10%
Parameters V
= 3.0V VCC = 2.5V V
CC
R1 1105 16670 15294 Ohms
R2 1550 15380 11300 Ohms
R
TH
V
TH
645 8000 6500 Ohms
1.75V 1.2V 0.85V Volts
Notes
1During VCC power-up, a pull-up resistor to VCC on CS is required to me et ISB specification.
2 This parameter is sampled, but not 100% tested.
3 For test conditions, see AC Test Conditions.
4t
and t
CLZ
5 This parameter is guarant ee d, but not tested. 6
WE is HIGH for read cycle.
7
CS and OE are LOW for read cycle.
8 Address valid prior to or coincident with
9 All read cycle timing s are re fe renc ed fr om the las t valid addre ss to the first trans it i oning addr es s.
10
CS or WE must be HIGH during address transitions. Either CS or WE asserting high terminates a write cycle.
11 All write cycl e tim ings are ref e re nc e d from the last valid address to the first trans itionin g address.
12 N/A.
13 1.2V data rete n tion a pplie s t o comm e rc ial an d indu strial temperat ure ra n ge ope ra tio n s.
14 C = 30pF, except at high Z and low Z parameters, where C = 5pF.
6
are specified with CL = 5pF as in Figure C. Transition is measured ±500 mV from steady-state voltage.
CHZ
CS transition LOW.
ALLIANCE SEMICONDUCTOR
= 2.0V Unit
CC
10/6/00
Page 7
Typical DC and AC characteristics
Normaliz ed supply current
1.4
1.2
1.0
CC
0.8
0.6
Normalized I
0.4
0.2
0.0
1.7
2.2 2.7 3.2 3.7 1.7 2.2 2.7 3.2 3.7
Supply voltage (V)
VIN = VCC typ
T
= 25° C
A
AA
Normalized T
1.0
0.75
0.5
0.25
0.0
®
Normalized access time
vs. su pp l y volt agevs. su pply vo ltage
TA = 25° C
Supply Voltage (V )
Normalized standby current
vs. ambient temperature
3.0
2.5
2.0
SB2
VCC = VCC typ
V
1.5
1.0
0.5
Norma l i zed I
0.0
–0.5
–55 10525
Ambient te mp erature (°C )
= VCC typ
IN
AS6VA5128
Normalized standby current
1.4
1.2
1.0
SB
0.8
0.6
Normalized I
0.4
0.2
0.0
11.9
vs. su pply vo ltage
VIN = VCC typ
= 25° C
T
A
2.8
Supply voltage (V)
I
SB2
3.7
Normalized I
vs. Cycle Time
1.5
V
= 3.6V
CC
Normalized I
1.0
0.50
IN
= 25° C
T
A
0.10
1 5 10 15
Supply vol tage (V)
CC
10/6/00
ALLIANCE SEMICONDUCTOR
7
Page 8
AS6VA5128
Package diagrams and dimensions
®
36(48) -ba l l FB G A
Bottom View
123456
A
B
C
D
E
F
G
H
A
B1
Ball #A1
C1
A
Top View
Ball #A1 in dex
SRAM Die
B
C
Elastomer
Side View
E2
E
E1
D
Die
Minimum Typical Maximum
A – 0.75 –
B 6.90 7.00 7.10
B1 – 3.75 –
C 10.90 11.00 11.10
C1 – 5.25 –
D 0.30 0.35 0.40
E––1.20
E1 – 0.68 –
E2 0.22 0.25 0.27
Y––0.08
Detail View
A
E2
E
Die
Y
0.3/Typ
Notes
1. Bump counts: 36(48) (8 row × 6 column).
2. Pitch: (x,y) = 0.75 mm × 0.75 mm (typ).
3. Units: millimeters.
4. All tolerances are ±0.050, unless otherwise specified.
5. Typ: typical.
6. Y is coplanarity: 0.08 (max).
8
ALLIANCE SEMICONDUCTOR
10/6/00
Page 9
Ordering codes
Speed (ns)
55 AS6VA5128-BC 48-ball fine pitch BGA Commercial
55
Ordering Code Package Type
AS6VA5128-BI 48-ball fine pitch BGA
Part numbering system
AS6VA 5128 T, ST, HF, HR, B C, I
SRAM Intelliwatt™ prefix Device number
®
Package:
B: CSP BGA
AS6VA5128
Operating Range
Industrial
Temperature range:
C: Commercial: 0° C to 70° C
–4
I: Industrial:
0°C to 85° C
10/6/00
Copyright © 2000. Alliance Sem i conductor Corporation (Alli ance)'s thr ee-point logo, our name, and Intelliwatt™ are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks
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does not assume any responsibility or liability arising out of the application or use of any product described herein, and discl aims any express or implied warranties related to fitness for a particular purpose, merchantability, or
infringement of any intellectual prop erty rights, except as expressly ag reed to in Alliance 's Terms and Conditions of Sale (available from Alliance). All sales of Alliance products are made excl usively according to Alliance's
Terms and Cond ition s of Sale . The purch ase of pro ducts from A lliance do es not convey a lice nse und er any pat ent rights, copyrig hts, mask wo rk s righ ts, trade ma rk s , or any ot her inte lle ct ual pro pe rty ri gh ts of All ian ce or third
parties. Alliance does not authorize its products for use as critical components in life-supporting sy stems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of
Alliance products in such life-suppo rtin g systems im plies that the manufacturer assumes all risk of such use and agrees to indem nify Alliance against all claims arising from such use.
ALLIANCE SEMICONDUCTOR
9
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