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Austin Semiconductor, Inc.
CLOCK
SDRAM
AS4SD4M16
4 Meg x 16 SDRAM
Synchronous DRAM Memory
FEATURES
• Extended Testing Over -55°C to +125° C and
Industrial T emp -40°C to 85° C
• WRITE Recovery ( t
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can be
changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8 or full page
• Auto Precharge and Auto Refresh Modes
• Self Refresh Mode (Industrial, -40°C to 85° C only)
• 4,096-cycle refresh
• L VTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
• Longer lead TSOP for improved reliability
(OCPL*)
• Short Flow / Long Flow T est Screening Options
OPTIONS MARKING
• Configurations
4 Meg x 16 (1 Meg x 16 x 4 banks) 4M16
• Plastic Package - OCPL*
54-pin TSOP (400 mil) D G No. 901
WR
/ t
) tWR = 2 CLK
DPL
PIN ASSIGNMENT
(Top View)
54-Pin TSOP
• Timing (Cycle Time)
8ns; tAC = 6.5ns @ CL = 3 ( tRP - 24ns) -8
10ns; tAC = 9ns @ CL = 2 -10
• Operating Temperature Ranges
-Military (-55°C to +125° C) XT
-Industrial T emp (-40°C to 85° C) IT
KEY TIMING PARAMETERS
SPEED
GRADE FREQUENCY CL = 2** CL = 3** TIME TIME
-8 125 MHz – 6.5ns 2ns 1ns
-10 100 MHz – 7ns 3ns 1ns
-8 83 MHz 9ns – 2ns 1ns
-10 66 MHz 9ns – 3ns 1ns
*Off-center parting line
**CL = CAS (READ) latency
AS4SD4M16
Rev. 1.5 10/01
ACCESS TIME
SETUP HOLD
Note: “\” indicates an active low.
4 Meg x 16
Configuration 1 Meg x 16 x 4 banks
Refresh Count 4K
Row Addressing 4K (A0-A11)
Bank Addressing 4 (BA0, BA1)
Column Addressing 256 (A0-A7)
For more products and information
please visit our web site at
www.austinsemiconductor .com
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Austin Semiconductor, Inc.
GENERAL DESCRIPTION
The 64Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 67,108,864 bits. It is internally
configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock
signal, CLK). Each of the x16’s 6,777,216-bit banks is or ganized
as 4,096 rows by 256 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command,
which is then followed by a READ or WRITE command. The
address bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed (BA0, BA1
select the bank; A0-A11 select the row). The address bits
registered coincident with the READ or WRITE command are
used to select the starting column location for the burst access.
The SDRAM provides for programmable READ or WRITE
burst lengths of 1, 2, 4 or 8 locations, or the full page, with a
burst terminate option. An AUTO PRECHARGE function may
be enabled to provide a self-timed row precharge that is initi-
SDRAM
AS4SD4M16
ated at the end of the burst sequence.
The 64Mb SDRAM uses an internal pipelined architecture
to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows
the column address to be changed on every clock cycle to
achieve a high-speed, fully random access. Precharging one
bank while accessing one of the other three banks will hide the
precharge cycles and provide seamless, high-speed, randomaccess operation.
The 64Mb SDRAM is designed to operate in 3.3V, lowpower memory systems. An auto refresh mode is provided,
along with a power-saving, power-down mode. All inputs and
outputs are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM operating
performance, including the ability to synchronously burst data
at a high data rate with automatic column-address generation,
the ability to interleave between internal banks in order to hide
precharge time and the capability to randomly change column
addresses on each clock cycle during a burst access.
AS4SD4M16
Rev. 1.5 10/01
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Austin Semiconductor, Inc.
TABLE OF CONTENTS
Functional Block Diagram - 4 Meg x 16 ........................................ 4
Pin Descriptions ............................................................................. 5
Functional Description ................................................................. 6
Initialization ............................................................................. 6
Register Definition ................................................................. 6
Mode Register ................................................................ 6
Burst Length ................................................................... 6
Burst Type ....................................................................... 7
CAS Latency ................................................................... 8
Operating Mode ............................................................. 8
Write Burst Mode .......................................................... 8
Commands ....................................................................................... 9
Truth Table 1 (Commands and DQM Operation) ......................... 9
Command Inhibit .................................................................... 10
No Operation (NOP) .................................................................10
Load Mode Register ............................................................. 10
Active ....................................................................................... 10
Read .......................................................................................... 10
Write ......................................................................................... 10
Precharge ................................................................................. 10
Auto Precharge ...................................................................... 10
Burst Terminate ...................................................................... 1 1
Auto Refresh .......................................................................... 11
Self Refresh ............................................................................. 11
Operation ..................................................................................... 12
Bank/Row Activation ............................................................ 12
Reads ........................................................................................ 13
Writes ....................................................................................... 19
Precharge................................................................................... 21
Power-Down...............................................................................21
SDRAM
AS4SD4M16
Clock Suspend......................................................................... 22
Burst Read/Single Write ...........................................................22
Concurrent Auto Precharge ................................................. 23
Truth T able 2 (CKE) ......................................................................2 5
Truth Table 3 (Current State, Same Bank) ................................. 26
Truth Table 4 (Current State, Different Bank) ........................... 28
Absolute Maximum Ratings ........................................................ 30
DC Electrical Characteristics and Operating Conditions......... 30
ICC Specifications and Conditions .............................................. 30
Capacitance ..................................................................................... 31
AC Electrical Characteristics (Timing T able) ............................31
Timing W aveforms
Initialize and Load Mode Register ..................................... 34
Power-Down Mode ................................................................ 35
Clock Suspend Mode ........................................................... 36
Auto Refresh Mode .............................................................. 37
Self Refresh Mode ................................................................. 38
Reads
Read - Without Auto Precharge ................................. 39
Read - With Auto Precharge ....................................... 40
Alternating Bank Read Accesses .............................. 41
Read - Full-Page Burst ......................................................... 42
Read - DQM Operation ................................................ 43
Writes
Write - W ithout Auto Precharge ................................ 44
Write - W ith Auto Precharge ...................................... 45
Alternating Bank Write Accesses .............................. 46
Write - Full-Page Burst ................................................. 47
Write - DQM Operation ............................................... 48
AS4SD4M16
Rev. 1.5 10/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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CKE
CLK
CS\
WE\
CAS\
RAS\
A0,
A10,
BA
MODE REGISTER
ADDRESS
14
REGISTER
Austin Semiconductor, Inc.
FUNCTIONAL BLOCK DIA GRAM
4 Meg x 16 SDRAM
CONTROL
LOGIC
DECODE
COMMAND
REFRESH
12
12
2
ROW
ADDRESS
MUX
2
CONTROL
COLUMNADDRESS
COUNTER/
COUNTER
1
12
8
12
BANK
LOGIC
LATCH
BANK0
ROW-
ADDRESS
LATCH &
DECODER
8
(4,096 X 256 X 16)
4096
SENSE AMPLIFIERS
DQM MASK LOGIC
READ DATA LATCH
BANK2
BANK1
BANK 0
MEMORY
ARRAY
4096
I/O GATING
WRITE DRIVERS
256
(X16)
COLUMN
DECODER
BANK3
AS4SD4M16
2 2
DATA
OUTPUT
16
REGISTER
DATA
16
INPUT
REGISTER
SDRAM
DQML, DQMH
DQ0-DQ15
16
AS4SD4M16
Rev. 1.5 10/01
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Austin Semiconductor, Inc.
PIN DESCRIPTION
SDRAM
AS4SD4M16
TSOP
PIN NUMBERS
SYMBOL TYPE
38 CLK Input
37 CKE Input
19 CS\ Input
16, 17 WE\, CAS\ Input
18 RAS\
15, 39 DQML, Input
DQMH
DESCRIPTION
Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal burst
counter and controls the output registers.
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
Deactivating the clock provides PRECHARGE POWER-DOWN and SELF
REFRESH operations (all banks idle), ACTIVE POWER-DOWN (row ACTIVE
in either bank) or CLOCK SUSPEND operation (burst/access in progress).
CKE is synchronous except after the device enters power-down and self
refresh modes, where CKE becomes asynchronous until after exiting the
same mode. The input buffers, including CLK, are disabled during power-down
and self refresh modes, providing low standby power. CKE may be tied
HIGH.
Chip Select: CS\ enables (registered LOW) and disables (registered HIGH)
the command decoder. All commands are masked when CS\ is registered
HIGH. CS\ provides for external bank selection on systems with multiple
banks. CS\ is considered part of the command code.
Command Inputs: RAS\, CAS\, and WE\ (along with CS\) define the
command being entered.
Input/Output Mask: DQM is an input mask signal for write accesses and an
output enable signal for read accesses. Input data is masked when DQM is
sampled HIGH during a WRITE cycle. The output buffers are placed in a
High-Z state (two-clock latency) when DQM is sampled HIGH during a READ
cycle. DQML corresponds to DQ0-DQ7; DQMH corresponds to DQ8-DQ15.
DQML and DQMH are considered same state when referenced as DQM.
20, 21 BA0, BA1 Input
23-26, 29-34, A0-A11 Input
22, 35
2, 4, 5, 7, 8 DQ0- DQ15 Input/
10, 11, 13, 42 Output
44, 45, 47, 48
50, 51, 53
36, 40 NC —
3, 9, 43, 49 VDDQ Supply
6, 12, 46, 52 VSSQ Supply
1, 14, 27 VDD Supply
28, 41, 54 VSS Supply
AS4SD4M16
Rev. 1.5 10/01
Bank Address Inputs: BA0 and BA1 define to which bank the ACTIVE, READ,
WRITE or PRECHARGE command is being applied.
Address Inputs: A0-A11 are sampled during the ACTIVE command (row
address A0-A11) and READ/WRITE command (column address A0-A7, with
A10 defining AUTO PRECHARGE) to select one location out of the memory
array in the respective bank. A10 is sampled during a PRECHARGE
command to determine if all banks are to be precharged (A10 HIGH) or bank
selected by BA0,BA1 (LOW). The address inputs also provide the op-code
during a LOAD MODE REGISTER command.
Data I/O: Data bus.
No Connect: These pins should be left unconnected.
DQ Power: Provide isolated power to DQs for improved noise immunity.
DQ Ground: Provide isolated ground to DQs for improved noise immunity.
Power Supply: +3.3V ±0.3V.
Ground.
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Austin Semiconductor, Inc.
SDRAM
AS4SD4M16
FUNCTIONAL DESCRIPTION
In general, the 64Mb SDRAM is quad-bank DRAM (1
Meg x 16 x 4 banks) which operate at 3.3V and include a
synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK). Each of the x16’s
16,777,216-bit banks is organized as 4,096 rows by 256 columns
by 16 bits.
Read and write accesses to the SDRAM are burst
oriented; accesses start at a selected location and continue for
a programmed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE command
which is then followed by a READ or WRITE command. The
address bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed (BA0 and
BA1 select the bank, A0-A11 select the row). The address bits
( x16: A0-A7) registered coincident with the READ or WRITE
command are used to select the starting column location for the
burst access.
Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information
covering device initialization, register definition, command
descriptions and device operation.
Initalization
SDRAMs must be powered up and initialized in a
predefined manner. Operational procedures other than those
specified may result in undefined operation. Once power is
applied to V
stable, the SDRAM requires a 100µs delay prior to applying an
executable command. Starting at some point during this 100µs
period and continuing at least through the end of this period,
COMMAND INHIBIT or NOP commands should be applied.
one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command should be applied. All banks
must be precharged, thereby placing the device in the all banks
idle state.
must be performed. After the AUTO REFRESH cycles are
complete, the SDRAM is ready for Mode Register programming. Because the Mode Register will power up in an unknown
state, it should be loaded prior to applying any operational
command.
DD and VDDQ (simultaneously) and the clock is
Once the 100µs delay has been satisfied with at least
Once in the idle state, two AUTO REFRESH cycles
REGISTER DEFINITION
Mode Register
The Mode Register is used to define the specific mode
of operation of the SDRAM. This definition includes the
selection of a burst length, a burst type, a CAS latency, an
operating mode and a write burst mode, as shown in Figure 1.
The Mode Register is programmed via the LOAD MODE
REGISTER command and will retain the stored information until
it is programmed again or the device loses power.
Mode register bits M0-M2 specify the burst length,
M3 specifies the type of burst (sequential or interleaved), M4M6 specify the CAS latency, M7 and M8 specify the operating
mode, M9 specifies the WRITE burst mode, and M10 and M11
are reserved for future use.
The Mode Register must be loaded when all banks are
idle, and the controller must wait the specified time before
initiating the subsequent operation. Violating either of these
requirements will result in unspecified operation.
Burst Length
Read and write accesses to the SDRAM are burst
oriented, with the burst length being programmable, as shown
in Figure 1. The burst length determines the maximum number
of column locations that can be accessed for a given READ or
WRITE command. Burst lengths of 1, 2, 4, or 8 locations are
available for both the sequential and the interleaved burst types,
and a full-page burst is available for the sequential type. The
full-page burst is used in conjunction with the BURST
TERMINATE command to generate arbitrary burst lengths.
Reserved states should not be used, as unknown
operation or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block
of columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning
that the burst will wrap within the block if a boundary is reached.
The block is uniquely selected by A1-A7 (x16) when the burst
length is set to two; A2-A7 (x16) when the burst length is set to
four; and by A3-A7 (x16) when the burst length is set to eight.
The remaining (least significant) address bit(s) is (are) used to
select the starting location within the block. Full-page bursts
wrap within the page if the boundary is reached.
AS4SD4M16
Rev. 1.5 10/01
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Austin Semiconductor, Inc.
A0
A0
A0
Table 1
Burst
SDRAM
AS4SD4M16
BURST TYPE
Accesses within a given burst may be programmed to
be either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
The ordering of accesses within a burst is determined
by the burst length, the burst type and the starting column
address, as shown in Table 1.
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
11 10 9 8 7 6 5 4 3 2 1 0
Reserved* WB Op Mode CAS Latency BT Burst Length
* Should program M11,
M10=0,0 to ensure
compatibility with future
devices.
M3
0
1
M9
0
1
M8 M7
00
--
M6 - M0
Defined
-
Write Burst Mode
Programmed Burst Length
Single Location Access
Operating Mode
Standard Operation
All other states reserved
M2 M1 M0
000 1 1
001 2 2
010 4 4
011 8 8
1 0 0 Reserved Reserved
1 0 1 Reserved Reserved
1 1 0 Reserved Reserved
1 1 1 Full Page Reserved
Burst Type
Sequential
Interleave
M6 M5 M4
000
001
010
011
100
101
110
111
Mode Register(Mx)
Burst Length
M3=0 M3=1
CAS Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
FIGURE 1
MODE REGISTER DEFINITION
Length
2
4
8
Full Page
(y)
NOTE:
BURST DEFINITION
Starting Column
Address
A1
0 0 0,1,2,3 0,1,2,3
0 1 1,2,3,0 1,0,3,2
1 0 2,3,0,1 2,3,0,1
1 1 3,0,1,2 3,2,1,0
A2 A1
0 0 0 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7
0 0 1 1,2,3,4,5,6,7,0 1,0,3,2,5,4,7,6
0 1 0 2,3,4,5,6,7,0,1 2,3,0,1,6,7,4,5
0 1 1 3,4,5,6,7,0,1,2 3,2,1,0,7,6,5,4
1 0 0 4,5,6,7,0,1,2,3 4,5,6,7,0,1,2,3
1 0 1 5,6,7,0,1,2,3,4 5,4,7,6,1,0,3,2
1 1 0 6,7,0,1,2,3,4,5, 6,7,4,5,2,3,0,1
1 1 1 7,0,1,2,3,4,5,6 7,6,5,4,3,2,1,0
n = A0 - A9
location 0 - y
Order of Access Within a Burst
Type = Sequential Type = Interleaved
0 0 - 1 0 - 1
1 1-0 1-0
Cn, Cn+1, Cn+2,
Cn+3, Cn+4…
…Cn-1,
Cn…
Not Supported
1 . For full-page accesses: y = 256 (x16).
2 . For a burst length of two, A1-A7 (x16)
select the block-of-two burst; A0 selects
the starting column within the block.
3 . For a burst length of four, A2-A7 (x16)
select the block-of-four burst; A0-A1
select the starting column within the
block.
4 . For a burst length of eight, A3-A7 (x16)
select the clock-of-eight burst; A0-A2
select the starting column within the
block.
5 . For a full-page burst, the full row is
selected and A0-A7 (x16) select the
starting column.
6. Whenever a boundary of the block is
reached within a given sequence above,
the following access wraps within the
block.
7 . For a burst length of one, A0-A7 (x16)
select the unique column to be accessed,
and Mode Register bit M3 is ignored.
AS4SD4M16
Rev. 1.5 10/01
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Austin Semiconductor, Inc.
-10
3
3
3
123
123
123
123
3
3
3
3
3
3
123
123
123
SDRAM
AS4SD4M16
CAS Latency
The CAS latency is the delay, in clock cycles, between
the registration of a READ command and the availability of the
first piece of output data. The latency can be set to two or three
clocks.
If a READ command is registered at clock edge n, and
the latency is m clocks, the data will be available by clock edge
n+m. The DQs will start driving as a result of the clock edge one
cycle earlier (n + m - 1), and provided that the relevant access
times are met, the data will be valid by clock edge n + m. For
example, assuming that the clock cycle time is such that all
relevant access times are met, if a READ command is registered
at T0 and the latency is programmed to two clocks, the DQs will
start driving after T1 and the data will be valid by T2, as shown
in Figure 2. T able 2 below indicates the operating frequencies at
which each CAS latency setting can be used.
T3T2T1T0
CLK
2
COMMAMD
DQ
2
NOP
t
LZ
t
AC
NOPREAD
t
OH
2
2
D
OUT
2
Reserved states should not be used as unknown op-
eration or incompatibility with future versions may result.
Operating Mode
The normal operating mode is selected by setting
M7and M8 to zero; the other combinations of values for M7
and M8 are reserved for future use and/or test modes. The
programmed burst length applies to both READ and WRITE
bursts.
Test modes and reserved states should not be used
because unknown operation or incompatibility with future versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via M0M2 applies to both READ and WRITE bursts; when M9 = 1,
the programmed burst length applies to READ bursts, but write
accesses are single-location (nonburst) accesses.
Table 2
CAS LATENCY
ALLOWABLE OPERATING FREQUENCY
(MHz)
SPEED
CAS LATENCY = 2 CAS LATENCY = 3
-8 ≤ 83
≤ 66
≤ 125
≤ 100
CLK
COMMAMD
DQ
AS4SD4M16
Rev. 1.5 10/01
CAS Latency = 2
READ
NOP
CAS Latency = 3
Figure 2
CAS LATENCY
NOP
T3T2T1T0
T4
NOP
t
LZ
t
AC
t
OH
2
2
D
2
OUT
UNDEFINED
2
DON’T CARE
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SDRAM
WE\
AS4SD4M16
Austin Semiconductor, Inc.
COMMANDS
Truth Table 1 provides a quick reference of available commands.
This is followed by a written description of each command.
Two additional Truth Tables appear following the Operation
section; these tables provide current state/next state information.
TRUTH TABLE 1- Commands and DMQ Operation
(Note: 1)
NAME (FUNCTION) CS\ RAS\ CAS\
COMMAND INHIBIT (NOP) H X X X X X X
NO OPERATION (NOP) L H H H X X X
ACTIVE (select bank and activate row) L L H H X Bank/Row X 3
READ (select bank and column and start READ burst) L H L H X Bank/Col X 4
WRITE (select bank and column and start WRITE burst) L H L L X Bank/Col Valid 4
BURST TERMINATE L H H L X X Active
PRECHARGE (deactivate row in bank or banks) L L H L X Code X 5
AUTO REFRESH or SELF REFRESH (enter self refresh
mode)
LOAD MODE REGISTER L L L L X OpCode X 2
Write Enable/Output Enable - - - - L - Active 8
Write Inhibit/Output High-Z - - - - H - High-Z 8
LL
DQM ADDR DQs NOTES
X 6,7LHX X
NOTE:
1. CKE is HIGH for all commands shown except SELF REFRESH.
2 . A0-A11 define the op-code written to the Mode Register.
3 . A0-A11 provide row address, and BA0, BA1 determine which bank is made active.
4 . A0-A7 (x16) provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10
5 . A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are
6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW .
7 . Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8 . Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
AS4SD4M16
Rev. 1.5 10/01
LOW disables the auto precharge feature; BA0, BA1 determine which bank is being read from or written to.
“Don’t Care.”
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Austin Semiconductor, Inc.
SDRAM
AS4SD4M16
COMMAND INHIBIT
The COMMAND INHIBIT function prevents new
commands from being executed by the SDRAM, regardless of
whether the CLK signal is enabled. The SDRAM is effectively
deselected. Operations already in progress are not affected.
NO OPERA TION (NOP)
The NO OPERA TION (NOP) command is used to perform a NOP to an SDRAM which is selected (CS\ is LOW). This
prevents unwanted commands from being registered during
idle or wait states. Operations already in progress are not affected.
LOAD MODE REGISTER
The Mode Register is loaded via inputs A0-A11. See
Mode Register heading in the Register Definition section. The
LOAD MODE REGISTER command can only be issued when
all banks are idle, and a subsequent executable command cannot be issued until tMRD is met.
ACTIVE
The ACTIVE command is used to open (or activate) a
row in a particular bank for a subsequent access. The value on
the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A11 selects the row. This row remains active (or open) for accesses until a PRECHARGE command is
issued to that bank. A PRECHARGE command must be issued
before opening a different row in the same bank.
WRITE
The WRITE command is used to initiate a burst write
access to an active row. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs A0-A7
(x16) selects the starting column location. The value on input
A10 determines whether or not AUTO PRECHARGE is used. If
AUTO PRECHARGE is selected, the row being accessed will
be precharged at the end of the WRITE burst; if AUTO
PRECHARGE is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQs is written
to the memory array subject to the DQM input logic level appearing coincident with the data. If a given DQM signal is
registered LOW, the corresponding data will be written to
memory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate the
open row in a particular bank or the open row in all banks. The
bank(s) will be available for a subsequent row access a speci-
fied time (tRP) after the PRECHARGE command is issued. Input
A10 determines whether one or all banks are to be precharged,
and in the case where only one bank is to be precharged, inputs
BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as
“Don’t Care.” Once a bank has been precharged, it is in the idle
state and must be activated prior to any READ or WRITE commands being issued to that bank.
READ
The READ command is used to initiate a burst read
access to an active row. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs A0-A7
(x16) selects the starting column location. The value on input
A10 determines whether or not AUTO PRECHARGE is used. If
AUTO PRECHARGE is selected, the row being accessed will
be precharged at the end of the READ burst; if AUTO
PRECHARGE is not selected, the row will remain open for subsequent accesses. Read data appears on the DQs subject to
the logic level on the DQM inputs two clocks earlier. If a given
DQM signal was registered HIGH, the corresponding DQs will
be High-Z two clocks later; if the DQM signal was registered
LOW , the DQs will provide valid data.
AS4SD4M16
Rev. 1.5 10/01
AUT O PRECHARGE
AUTO PRECHARGE is a feature which performs the
same individual-bank PRECHARGE function described above,
without requiring an explicit command. This is accomplished
by using A10 to enable AUTO PRECHARGE in conjunction
with a specific READ or WRITE command. A precharge of the
bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ
or WRITE burst, except in the full-page burst mode, where
AUTO PRECHARGE does not apply . AUTO PRECHARGE is
nonpersistent in that it is either enabled or disabled for each
individual READ or WRITE command.
AUTO PRECHARGE ensures that the precharge is
initiated at the earliest valid stage within a burst. The user must
not issue another command to the same bank until the precharge
time (tRP) is completed. This is determined as if an explicit
PRECHARGE command was issued at the earliest possible time,
as described for each burst type in the Operation section of this
data sheet.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
10
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BURST TERMINATE
The BURST TERMINA TE command is used to truncate either fixed-length or full-page bursts. The most recently
registered READ or WRITE command prior to the BURST TERMINATE command will be truncated, as shown in the Operation section of this data sheet.
AUT O REFRESH
AUTO REFRESH is used during normal operation of
the SDRAM and is analagous to CAS\-BEFORE-RAS\ (CBR)
REFRESH in conventional DRAMs. This command is nonpersistent, so it must be issued each time a refresh is required.
The addressing is generated by the internal refresh
controller. This makes the address bits “Don’ t Care” during an
AUTO REFRESH command. The 64Mb SDRAM requires 4,096
AUTO REFRESH cycles every 64ms *(t
option. Providing a distributed AUTO REFRESH command
every 15.625µs/3.906µs will meet the refresh requirement and
ensure that each row is refreshed. Alternatively, 4,096 AUTO
REFRESH commands can be issued in a burst at the minimum
cycle rate (tRC), once every 64ms/ 16ms.
), regardless of width
REF
SDRAM
AS4SD4M16
SELF REFRESH
(Industrial -40°C to +85°C Only)
The SELF REFRESH command can be used to retain
data in the SDRAM, even if the rest of the system is powered
down. When in the self refresh mode, the SDRAM retains data
without external clocking. The SELF REFRESH command is
initiated like an AUTO REFRESH command except CKE is
disabled (LOW).
Once the SELF REFRESH command is registered, all
the inputs to the SDRAM become “Don’t Care,” with the
exception of CKE, which must remain LOW .
Once self refresh mode is engaged, the SDRAM
provides its own internal clocking, causing it to perform its own
AUTO REFRESH cycles. The SDRAM must remain in self
refresh mode for a minimum period equal to t
remain in self refresh mode for an indefinite period beyond that.
The procedure for exiting self refresh requires a
sequence of commands. First, CLK must be stable prior to CKE
going back HIGH. Once CKE is HIGH, the SDRAM must have
NOP commands issued (a minimum of two clocks) for t
because time is required for the completion of any internal
refresh in progress.
If during normal operation AUTO REFRESH cycles
are issued in bursts (as opposed to being evenly distributed),
a burst of 4,096 AUTO REFRESH cycles should be completed
just prior to entering and just after exiting the self refresh mode.
The self refresh option is not available for the -55° to
+125° screening option.
and may
RAS
XSR
,
*64ms for -40° to +85° C ( Industrial Temperatures) and 16ms for -55° to +125°C (Military Temperatures)
AS4SD4M16
Rev. 1.5 10/01
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3
OPERATION
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be issued
to a bank within the SDRAM, a row in that bank must be
“opened.” This is accomplished via the ACTIVE command,
which selects both the bank and the row to be activated.
After opening a row (issuing an ACTIVE command), a
READ or WRITE command may be issued to that row, subject
to the
t
specification. t
RCD
clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on
which a READ or WRITE command can be entered. For
t
example, a
specification of 30ns with a 90 MHz clock
RCD
(11.11ns period) results in 2.7 clocks, rounded to 3. This is
reflected in Figure 4, which covers any case where 2 <
(MIN)/ tCK ≤ 3. (The same procedure is used to convert other
specification limits from time units to clock cycles).
A subsequent ACTIVE command to a different row in
the same bank can only be issued after the previous active row
has been “closed” (precharged). The minimum time interval
between successive ACTIVE commands to the same bank is
t
defined by
RC
.
A subsequent ACTIVE command to another bank can
be issued while the first bank is being accessed, which results
in a reduction of total row-access overhead. The minimum time
interval between successive ACTIVE commands to different
banks is defined by
t
RRD
(MIN) should be divided by the
RCD
.
t
RCD
SDRAM
AS4SD4M16
CLK
HIGH
CKE
2345678901
CS\
2345678901
RAS\
2345678901234
CAS\
2345678901234
WE\
23456789012345
A0-A11
23456789012345
BA0, 1
ACTIVATING A SPECIFIC ROW IN A
SPECIFIC BANK
ROW ADDRESS
BANK ADDRESS
Figure 3
2345678901
2345678901
2345678
2345678
23456789012
23456789012
T0
T1
T2
T3
T4
CLK
COMMAND
ACTIVE
NOP
t
NOP
RCD
READ or
WRITE
23
DON’T CARE
Figure 4
EXAMPLE: MEETING t
AS4SD4M16
Rev. 1.5 10/01
12
(MIN) WHEN 2<t
RCD
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(MIN)/tCK<3
RCD
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1
0
8
3
8
3
4
1
4
1
4
1
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SDRAM
AS4SD4M16
READs
READ bursts are initiated with a READ command, as shown in
Figure 5.
The starting column and bank addresses are provided
with the READ command, and AUTO PRECHARGE is either
enabled or disabled for that burst access. If AUTO PRECHARGE
is enabled, the row being accessed is precharged at the completion of the burst. For the generic READ commands used in the
following illustrations, AUTO PRECHARGE is disabled.
During READ bursts, the valid data-out element from
the starting column address will be available following the CAS
latency after the READ command. Each subsequent data-out
element will be valid by the next positive clock edge. Figure 6
shows general timing for each possible CAS latency setting.
CLK
Upon completion of a burst, assuming no other
commands have been initiated, the DQs will go High-Z. A
full-page burst will continue until terminated. (At the end of the
page, it will wrap to column 0 and continue.)
Data from any READ burst may be truncated with a
subsequent READ command, and data from a fixed-length READ
burst may be immediately followed by data from a READ
command. In either case, a continuous flow of data can be
maintained. The first data element from the new burst follows
either the last element of a completed burst or the last desired
data element of alonger burst which is being truncated. The
new READ command should be issued x cycles before the clock
edge at which the last desired data element is valid, where x
equals the CAS latency minus one.
CLK
T0
T1
T2
T3
CKE
CS\
RAS\
CAS\
WE\
A0-A7: x16
A8, A9, A11: x16
A10
BA0, 1
HIGH
23456789012
234567890
23456789012
234567890123
234567890123
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
234567890123
Figure 5
READ COMMAND
COLUMN ADDRESS
BANK ADDRESS
234567
23456789
234567
234567890
234567890
234567890
COMMAND
CLK
COMMAND
DQ
DQ
T0
READ
READ
NOP
t
LZ
t
AC
CAS Latency = 2
T1
NOP
t
LZ
CAS Latency = 3
Figure 6
CAS LATENCY
T2
NOP
NOP
t
DOUT
t
AC
OH
T3
NOP
DOUT
T4
t
OH
2
2
DON’T CARE
23
23
UNDEFINED
AS4SD4M16
Rev. 1.5 10/01
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1234567
1234567
1234567
1234567
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1234567
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123
3
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123
SDRAM
AS4SD4M16
This is shown in Figure 7 for CAS latencies of two and three;
data element n + 3 is either the last of a burst of four or the last
desired of a longer burst. The 64Mb SDRAM uses a pipelined
architecture and therefore does not require the 2n rule
associated with a prefetch architecture. A READ command can
T0 T1 T2 T3 T4 T5
CLK
COMMAND
ADDRESS
DQ
○○○○○○○○○○○○○○○○○○○○
READ READ
BANK,
COL
n
○○○○○○○○○○○○○○○○○○
NOP NOP
2
2
2
CAS Latency = 2
○○○○○○○○○○○○○○○○○○○○
23
23
23
DOUT
n
be initiated on any clock cycle following a previous READ
command. Full-speed random read accesses can be performed
to the same bank, as shown in Figure 8, or each subsequent
READ may be performed to a different bank.
T6
○○○○○○○○○○○○○○○○○○○○
NOP
2
2
2
DOUT
n+1
○○○○○○○○○○○○○○○○○○○○
○○○○○○○○○○○○○○○○○○○○
NOP
X=1 cycle
2
BANK,
COL
DOUT
n+2
b
2
2
DOUT
n+3
○○○○○○○○○○○○○○○○○○○○
NOP
2
2
2
DOUT
b
COMMAND
ADDRESS
AS4SD4M16
Rev. 1.5 10/01
T0 T1 T2 T3 T4 T5
CLK
○○○○○○○○○○○○○○○○○○○○
READ
BANK,
COL
○○○○○○○○○○○○○○○○○○
NOP NOP
23
23
n
23
○○○○○○○○○○○○○○○○○○
23
23
23
DQ
CAS Latency = 3
NOTE: Each READ command may be to either bank. DQM is LOW.
○○○○○○○○○○○○○○○○○○○○
NOP
23
23
23
DOUT
n
Figure 7
CONSECUTIVE READ BURSTS
14
T6
○○○○○○○○○○○○○○○○○○○○
READ
BANK,
COL
b
DOUT
n+1
○○○○○○○○○○○○○○○○○○○○
NOP
X=2 cycle
23
23
23
DOUT
n+2
○○○○○○○○○○○○○○○○○○○○
NOP
2
2
2
DOUT
n+3
T7
○○○○○○○○○○○○○○○○○○○○
NOP
12
12
12
DOUT
b
23
23
DON’T CARE
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T0 T1 T2 T3 T4 T5
SDRAM
AS4SD4M16
COMMAND
ADDRESS
CLK
COMMAND
CLK
DQ
○○○○○○○○○○○○○○○○○○
READ
BANK,
COL
n
○○○○○○○○○○○○○○○○
READ
BANK,
COL
a
○○○○○○○○○○○○○○○○○○
○○○○○○○○○○○○○○○○○○
READ READ
BANK,
COL
D
OUT
n
BANK,
x
COL
D
OUT
a
m
CAS Latency = 2
T0 T1 T2 T3 T4 T5
○○○○○○○○○○○○○○○○○○
READ
○○○○○○○○○○○○○○○○
READ
○○○○○○○○○○○○○○○○
READ READ NOP
○○○○○○○○○○○○○○○○○○
NOP
○○○○○○○○○○○○○○○○○○
○○○○○○○○○○○○○○○○○○
NOP
2
2
2
D
OUT
x
○○○○○○○○○○○○○○○○○○
NOP
23
23
23
D
OUT
m
T6
○○○○○○○○○○○○○○○○○○
○○○○○○○○○○○○○○○○○○
NOP
AS4SD4M16
Rev. 1.5 10/01
ADDRESS
DQ
23
BANK,
COL
BANK,
n
COL
BANK,
a
COL
BANK,
x
COL
m
D
OUT
n
23
23
D
OUT
a
CAS Latency = 3
NOTE: Each READ command may be to either bank. DQM is LOW.
Figure 8
RANDOM READ ACCESSES
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
15
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2
2
D
OUT
x
23
23
23
D
OUT
m
23
23
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SDRAM
AS4SD4M16
Data from any READ burst may be truncated with a
subsequent WRITE command, and data from a fixed-length
READ burst may be immediately followed by data from a WRITE
command (subject to bus turnaround limitations). The WRITE
burst may be initiated on the clock edge immediately following
the last (or last desired) data element from the READ burst,
provided that I/O contention can be avoided. In a given
system design, there may be a possibility that the device
driving the input data will go Low-Z before the SDRAM DQs
go High-Z. In this case, at least a single-cycle delay should
occur between the last read data and the WRITE command.
The DQM input is used to avoid I/O contention, as shown in
Figures 9 and 10. The DQM signal must be asserted (HIGH) at
least two clocks prior to the WRITE command (DQM latency is
two clocks for output buffers) to suppress data-out from the
READ. Once the WRITE command is registered, the DQs will
go High-Z (or remain High-Z), regardless of the state of the
DQM signal. The DQM signal must be de-asserted prior to the
WRITE command (DQM latency is zero clocks for input
buffers) to ensure that the written data is not masked. Figure 9
shows the case where the clock frequency allows for bus
contention to be avoided without adding a NOP cycle, and
Figure 10 shows the case where the additional NOP is needed.
T0 T1 T2 T3 T4
CLK
○○○○○○○○○○○○○○○○○○
○○○○○○○○○○○○○○○○○○
○○○○○○○○○○○○○○○○○○
○○○○○○○○○○○○○○○○○○
○○○○○○○○○○○○○○○○○○
DQM
COMMAND
ADDRESS
READ
BANK,
COL
DQ
NOTE: A CAS latency of three is used for illustration. The READ command may be to any
bank, and the WRITE command may be to any bank. If a CAS latency of one is used, the
DQM is not required.
NOP NOP
2
2
n
NOP
2
2
D
OUT
WRITE
BANK,
COL
t
CK
t
HZ
DIN
n
t
DS
Figure 9
READ TO WRITE
b
b
T0 T1 T2 T3 T4
CLK
DQM
COMMAND
ADDRESS
DQ
NOTE: A CAS latency of three is used for illustration. The READ command may be to any bank,
and the WRITE command may be to any bank.
○○○○○○○○○○○○○○○○○○
READ
BANK,
COL
n
○○○○○○○○○○○○○○○○○○
NOP NOP
2
2
○○○○○○○○○○○○○○○○○○
2
2
○○○○○○○○○○○○○○○○○○
NOP
2
2
t
HZ
D
n
OUT
○○○○○○○○○○○○○○○○○○
NOP
T5
○○○○○○○○○○○○○○○○○○
WRITE
BANK,
COL
2
DON’T CARE
b
DIN
t
b
DS
Figure 10
READ TO WRITE WITH EXTRA
CLOCK CYCLE
AS4SD4M16
Rev. 1.5 10/01
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AS4SD4M16
A fixed-length READ burst may be followed by, or
truncated with, a PRECHARGE command to the same bank
(provided that AUTO PRECHARGE was not activated), and a
full-page burst maybe truncated with a PRECHARGE command
to the same bank. The PRECHARGE command should be issued x cycles before the clock edge at which the last desired
data element is valid, where x equals the CAS latency minus
one. This is shown in Figure 11 for each possible CAS latency;
data element n + 3 is either the last of a burst of four or the last
T0 T1 T2 T3 T4 T5
CLK
COMMAND
ADDRESS
○○○○○○○○○○○○○○○
READ
BANK a,
COL
n
○○○○○○○○○○○○○
NOP
23
23
23
○○○○○○○○○○○○○○○
NOP
23
23
23
desired of a longer burst. Following the PRECHARGE
command, a subsequent command to the same bank cannot be
issued until t
is met. Note that part of the row precharge time
RP
is hidden during the access of the last data element(s).
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the optimum
time (as described above) provides the same operation that
would result from the same fixed-length burst
○○○○○○○○○○○○○○○
NOP
2
2
○○○○○○○○○○○○○○○
PRECHARGE
X = 1 cycles
BANK
a
or all)
(
○○○○○○○○○○○○○○○
NOP
2
2
T6
t
RP
○○○○○○○○○○○○○○○
NOP
2
2
2
T7
○○○○○○○○○○○○○○○
ACTIVE
BANK a,
ROW
DQ
CLK
COMMAND
ADDRESS
DQ
D
OUT
n
D
OUT
n+1
CAS Latency = 2
T0 T1 T2 T3 T4 T5
○○○○○○○○○○○○○○○
READ
BANK a,
COL
n
○○○○○○○○○○○○○
NOP
2
2
○○○○○○○○○○○○○
NOP
23
23
○○○○○○○○○○○○○○○
NOP
2
2
D
PRECHARGE NOP
OUT
n
CAS Latency = 3
NOTE: DQM is LOW.
Figure 11
READ TO PRECHARGE
BANK
(
a
D
n+2
○○○○○○○○○○○○○○○
or all)
D
OUT
n+1
OUT
D
OUT
n+3
t
○○○○○○○○○○○○○○○
RP
X = 2 cycles
23
23
D
OUT
n+2
T6
○○○○○○○○○○○○○○○
NOP
23
23
D
OUT
n+3
T7
○○○○○○○○○○○○○○○
ACTIVE
BANK a,
23
ROW
DON’T CARE
AS4SD4M16
Rev. 1.5 10/01
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17
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AS4SD4M16
with AUTO PRECHARGE. The disadvantage of the
PRECHARGE command is that it requires that the command
and address buses be available at the appropriate time to issue
the command; the advantage of the PRECHARGE command is
that it can be used to truncate fixed-length or full-page bursts.
Full-page READ bursts can be truncated with the
BURST TERMINATE command, and fixed-length READ bursts
T0 T1 T2 T3 T4 T5
CLK
COMMAND
ADDRESS
DQ
○○○○○○○○○○○○○○
READ
BANK,
COL
n
CAS Latency = 2
○○○○○○○○○○○○○
NOP
2
2
○○○○○○○○○○○○○○
NOP
23
23
D
OUT
NOP
2
2
n
may be truncated with a BURST TERMINATE command,
provided that AUTO PRECHARGE was not activated. The
BURST TERMINATE command should be issued x cycles
before the clock edge at which the last desired data element is
valid, where x equals the CAS latency minus one. This is shown
in Figure 12 for each possible CAS latency; data element n + 3
is the last desired data element of a longer burst.
T6
○○○○○○○○○○○○○○
D
OUT
n+1
○○○○○○○○○○○○○○
BURST
TERMINATE
X = 1 cycles
2
2
D
OUT
n+2
○○○○○○○○○○○○○○
NOP
23
23
D
OUT
n+3
○○○○○○○○○○○○○○
NOP
23
23
COMMAND
ADDRESS
AS4SD4M16
Rev. 1.5 10/01
CLK
DQ
T0 T1 T2 T3 T4 T5
○○○○○○○○○○○○○○
READ
BANK,
COL
n
○○○○○○○○○○○○○
NOP
23
23
○○○○○○○○○○○○○
NOP
23
23
○○○○○○○○○○○○○○
NOP
2
2
D
OUT
n
○○○○○○○○○○○○○○
BURST
TERMINATE
2
2
D
OUT
n+1
CAS Latency = 3
NOTE: DQM is LOW.
Figure 12
TERMINATING A READ BURST
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
18
T6
○○○○○○○○○○○○○○
NOP
X = 2 cycles
2
2
D
OUT
n+2
○○○○○○○○○○○○○○
NOP
2
2
D
T7
○○○○○○○○○○○○○○
NOP
2
2
OUT
n+3
23
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AS4SD4M16
WRITEs
WRITE bursts are initiated with a WRITE command,
as shown in Figure 13.
The starting column and bank addresses are provided
with the WRITE command, and AUTO PRECHARGE is either
enabled or disabled for that access. If AUTO PRECHARGE is
enabled, the row being accessed is precharged at the completion of the burst. For the generic WRITE commands used in the
following illustrations, AUTO PRECHARGE is disabled.
During WRITE bursts, the first valid data-in element
will be registered coincident with the WRITE command. Subsequent data elements will be registered on each successive positive clock edge. Upon completion of a fixed-length burst, assuming no other commands have been initiated, the DQs will
remain High-Z and any additional input data will be ignored
(see Figure 14). A full-page burst will continue until terminated.
(At the end of the page, it will wrap to column 0 and continue.)
Data for any WRITE burst may be truncated with a
subsequent WRITE command, and data for a fixed-length
WRITE burst may be immediately followed by data for a WRITE
command. The new WRITE command can be issued on any
clock following the previous WRITE command, and the data
provided coincident with the new command applies to the new
command. An example is shown in Figure 15. Data n + 1 is either
the last of a burst of two or the last desired of a longer burst.
The 64Mb SDRAM uses a pipelined architecture and therefore
does not require the 2n rule associated with a prefetch architecture. A WRITE command can be initiated on any clock cycle
following a previous WRITE command. Full-speed random write
accesses within a page can be performed to the same bank, as
shown in Figure 16, or each subsequent WRITE may be performed to a different bank.
T0 T1 T2 T3
CLK
COMMAND
ADDRESS
DQ
○○○○○○○○○○○
WRITE
BANK,
COL
DIN
NOP
2
n
n
DIN
NOTE: Burst length = 2. DQM is LOW.
○○○○○○○○○○○
n+1
○○○○○○○○○○○
NOP
2
2
NOP
○○○○○○○○○○○
2
2
2
CLK
CKE
CS\
RAS\
CAS\
WE\
A0-A7: x16
A8, A9, A11: x16
A10
BA0,1
HIGH
234567890
234567890123
234567890
2345678901234
2345678901234
2345678901234
COLUMN ADDRESS
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
2345678901234
BANK ADDRESS
Figure 13
WRITE COMMAND
2345678
234567890
234567
23456789
2345678901
2345678901
2345678901
2345678901
CLK
COMMAND
ADDRESS
DQ
Figure 14
WRITE BURST
T0 T1 T2
○○○○○○○○○○○○
WRITE
BANK,
COL
DIN
n
n
○○○○○○○○○○○○
NOP
2
2
DIN
n+1
NOTE: DQM is LOW . Each WRITE command may be to any bank.
○○○○○○○○○○○○
WRITE
BANK,
COL
b
DIN
b
23
23
DON’T CARE
Figure 15
WRITE TO WRITE
AS4SD4M16
Rev. 1.5 10/01
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AS4SD4M16
Data for any WRITE burst may be truncated with a
subsequent READ command, and data for a fixed-length WRITE
burst may be immediately followed by a subsequent READ
command. Once the READ command is registered, the data
inputs will be ignored, and WRITEs will not be executed. An
example is shown in Figure 17. Data n+1 is either the last of a
burst of two or the last desired of a longer burst.
Data for a fixed-length WRITE burst may be followed
by, or truncated with, a PRECHARGE command to the same
bank (provided that AUTO PRECHARGE was not activated),
and a full-page WRITE burst may be truncated with a
PRECHARGE command to the same bank. The PRECHARGE
command should be issued tWR after the clock edge at which
the last desired input data element is registered. The Auto
Precharge mode requires a t
of at least one clock plus time
WR
(8ns), regardless of frequency. In addition, when truncating a
T0 T1 T2 T3
CLK
COMMAND
ADDRESS
DQ
○○○○○○○○○○○
WRITE
BANK,
COL
DIN
○○○○○○○○○○○
WRITE
BANK,
n
COL
n
D
a
IN
WRITE
BANK,
a
COL
○○○○○○○○○○○
WRITE
BANK,
COL
x
DIN
x
DIN
○○○○○○○○○○○
m
m
NOTE: Each WRITE command may be to any bank. DQM is
LOW.
Figure 16
RANDOM WRITE CYCLES
WRITE burst, the DQM signal must be used to mask input data
for the clock edge prior to, and the clock edge coincident with,
the PRECHARGE command. An example is shown in Figure 18.
Data n + 1 is either the last of a burst of two or the last desired
of a longer burst. Following the PRECHARGE command, a
subsequent command to the same bank cannot be issued until
tRP is met.
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the optimum
time (as described above) provides the same operation that
would result from the same fixed-length burst with AUTO
PRECHARGE. The disadvantage of the PRECHARGE command
is that it requires that the command and address buses be
available at the appropriate time to issue the command; the
advantage of the PRECHARGE command is that it can be used
to truncate fixed-length or full-page bursts.
T0 T1 T2 T3 T4 T5
CLK
○○○○○○○○○○○○○○○
t
WR= 2 CLK (“A2 version”)
○○○○○○○○○○○○○○○
DQM
BANK
a
,
COL
DIN
NOP
2
DIN
n+1
t
WR
n
n
COMMAND
WRITE
ADDRESS
DQ
NOTE: DQM coulc remain LOW in this example if the WRITE burst is a fixed length
of 2.
○○○○○○○○○○○○○○○
○○○○○○○○○○○○○○○
PRECHARGENOP
BANK
(a or all)
○○○○○○○○○○○○○○○
t
RP
NOP
23
T6
○○○○○○○○○○○○○○○
NOP
ACTIVE
BANK
a
,
ROW
2
○○○○○○○○○○○○○○○
DON’T CARE
T0 T1
CLK
COMMAND
ADDRESS
NOTE: The WRITE command may be to any bank, and the READ command may be to
○○○○○○○○○○○
WRITE
BANK,
COL
DQ
DIN
any bank. DQM is LO W . CAS latency = 2 for illustr ation.
NOP NOP
2
2
n
n
DIN
n+1
○○○○○○○○○○○
READ NO P
BANK,
COL
2
2
T2
T3 T4 T5
○○○○○○○○○○○
b
○○○○○○○○○○○
1
1
○○○○○○○○○○○
2
2
D
b
OUT
Figure 17
WRITE TO READ
AS4SD4M16
Rev. 1.5 10/01
○○○○○○○○○○○
NOP
D
b+1
OUT
Figure 18
WRITE TO PRECHARGE
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AS4SD4M16
Fixed-length or full-page WRITE bursts can be
truncated with the BURST TERMINATE command. When
truncating a WRITE burst, the input data applied coincident
with the BURST TERMINATE command will be ignored. The
last data written (provided that DQM is LOW at that time) will
be the input data applied one clock previous to the BURST
TERMINATE command. This is shown in Figure 19, where data
n is the last desired data element of a longer burst.
T0 T1 T2
CLK
COMMAND
ADDRESS
DQ
○○○○○○○○○○
WRITE
BANK,
COL
n
DIN
n
○○○○○○○○○○
BURST
TERMI-
NATE
2
2
○○○○○○○○○○
NEXT
COMMAND
(ADDRESS)
(DATA)
NOTE: DQMs is LOW.
Figure 19
TERMINATING A WRITE BURST
PRECHARGE
The PRECHARGE command is used to deactivate the
open row in a particular bank or the open row in all banks. The
bank(s) will be available for a subsequent row access some
specified time (t
) after the PRECHARGE command is issued.
RP
Input A10 determines whether one or all banks are to be
precharged, and in the case where only one bank is to be
precharged, inputs BA0, BA1 select the bank. When all banks
are to be precharged, inputs BA0, BA1 are treated as “Don’t
Care.” Once a bank has been precharged, it is in the idle state
and must be activated prior to any READ or WRITE commands
being issued to that bank.
POWER-DOWN
Power-down occurs if CKE is registered LOW
coincident with a NOP or COMMAND INHIBIT when no
accesses are in progress. If power-down occurs when all banks
are idle, this mode is referred to as precharge power-down; if
power-down occurs when there is a row active in either bank,
this mode is referred to as active power-down. Entering powerdown deactivates the input and output buffers, excluding CKE,
for maximum power savings while in standby. The device may
not remain in the power-down state longer than the refresh
period (64ms/16ms) since no refresh operations are performed
in this mode.
The power-down state is exited by registering a NOP
or COMMAND INHIBIT and CKE HIGH at the desired clock
edge (meeting t
CKS
).
CLK
HIGH
CKE
2345678901
CS\
RAS\
234567890123
CAS\
2345678901
WE\
A0-A9
2345678901234
A10
23456789012345
BA
AS4SD4M16
Rev. 1.5 10/01
234567890
234567
234567890
ALL BANKS
BANK SELECTED
BANK ADDRESS
2345678901
2345678901
Figure 20
PRECHARGE COMMAND
CLK
CKE
COMMAND
21
t
CKS
2345678901234567
2345678901234567
NOP
All banks idle
Enter power-down mode. Exit power-down mode.
2345678901234567
2345678901234567
Input buffers gated off
>t
CKS
NOP
ACTIVE
23
23
DON’T CARE
Figure 21
POWER-DOWN
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RCD
t
RAS
t
RC
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AS4SD4M16
CLOCK SUSPEND
The clock suspend mode occurs when a column
access/burst is in progress and CKE is registered LOW. In the
clock suspend mode, the internal clock is deactivated,
“freezing” the synchronous logic.
For each positive clock edge on which CKE is sampled
LOW, the next internal positive clock edge is suspended. Any
command or data present on the input pins at the time of a
suspended internal clock edge is ignored; any data present on
the DQ pins remains driven; and burst counters are not
incremented, as long as the clock is suspended. (See examples
in Figures 22 and 23.)
Clock suspend mode is exited by registering CKE
HIGH; the internal clock and related operation will resume on
the subsequent positive clock edge.
CLK
CKE
INTERNAL
CLOCK
T0 T1
○○○○○○○○○○○
○○○○○○○○○○○
T2
T3 T4 T5
○○○○○○○○○○○
○○○○○○○○○○○
○○○○○○○○○○○
○○○○○○○○○○○
BURST READ/SINGLE WRITE
The burst read/single write mode is entered by
programming the write burst mode bit (M9) in the Mode
Register to a logic 1. In this mode, all WRITE commands result
in the access of a single column location (burst of one), regardless of the programmed burst length. READ commands access
columns according to the programmed burst length and
sequence, just as in the normal mode of operation (M9=0).
T0 T1 T2 T3 T4 T5 T6
CLK
CKE
INTERNAL
CLOCK
○○○○○○○○○○○○○○○○
○○○○○○○○○○○○○○○○
○○○○○○○○○○○○○○○○
○○○○○○○○○○○○○○○
○○○○○○○○○○○○○○○○
○○○○○○○○○○○○○○○○
○○○○○○○○○○○○○○○○
COMMAND
ADDRESS
DQ
WRITENOP
2
BANK,
COL
2
DIN
23
2
n
2
n
2
NOTE: For this e xample, burst length = 4 or greater , and DQM is LOW .
Figure 22
CLOCK SUSPEND DURING WRITE
BURST
NOP NOP
2
DIN
n+1
DIN
n+2
COMMAND
ADDRESS
DQ
BANK,
COL
NOPREAD
NOP
n
D
n
OUT
NOP
NOP NOP
2
2
D
n+1
OUT
D
n+2
OUT
NOTE: For this e xample, CAS latency = 2, burst length = 4 or greater , and DQM is LO W .
DON’T CARE
Figure 23
CLOCK SUSPEND DURING READ
BURST
D
n+3
OUT
AS4SD4M16
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AS4SD4M16
CONCURRENT AUT O PRECHARGE
An access command (READ or WRITE) to another
bank while an access command with AUTO PRECHARGE enabled is executing is not allowed by SDRAMs, unless the
SDRAM supports CONCURRENT AUTO PRECHARGE. ASI
SDRAMs support CONCURRENT AUTO PRECHARGE. Four
cases where CONCURRENT AUTO PRECHARGE occurs are
defined below.
T0 T1 T2 T3 T4 T5
CLK
COMMAND
BANK n
○○○○○○○○○○○○○○○○○○
NOP
○○○○○○○○○○○○○○○○○○
READ-AP
BANK
n
Page Active READ with burst of 4
○○○○○○○○○○○○○○○○○
NOP
○○○○○○○○○○○○○○○○○○○○
READ-AP
BANK
Internal
States
BANK m
ADDRESS
2
2
Page Active
BANK n,
COL
a
23
23
BANK m,
COL
d
DQ
READ with AUTO PRECHARGE
1. Interrupted by a READ (with or without AUTO
PRECHARGE): A READ to bank m will interrupt a READ
on bank n, CAS latency later. The PRECHARGE to bank n
will begin when the READ to bank m is registered
(Figure 24).
2. Interrupted by a WRITE (with or without AUTO
PRECHARGE): A WRITE to bank m will interrupt a READ
on bank n when registered. DQM should be used two
clocks prir to the WRITE command to prevent bus
contention. The PRECHARGE to bank n will begin when
the WRITE to bank m is registered (Figure 25).
OUT
T7
○○○○○○○○○○○○○○○○○○
NOP
t
-BANK
RP
Precharge
23
23
D
d
OUT
d+1
m
T6
○○○○○○○○○○○○○○○○○○
m
NOP
○○○○○○○○○○○○○○○○○
NOP
○○○○○○○○○○○○○○○○○○○○
NOP
Interrupt Burst, Precharge Idle
tRP - BANK
n
READ with burst of 4
2
2
D
a
OUT
23
23
D
a+1
OUT
2
2
D
CAS Latency = 3 (BANK n)
NOTE: DQM is LOW .
READ WITH AUTO PRECHARGE INTERRUPTED BY A READ
T0 T1 T2 T3 T4 T5
CLK
COMMAND
BANK n
Internal
○○○○○○○○○○○○○○○○○○○
READ-AP
BANK
n
Page
Active
○○○○○○○○○○○○○○○○○○○
NOP
NOP
READ with burst of 4
States
BANK m
ADDRESS
DQM
BANK n,
COL
a
2
1
Page Active
2
2
23
23
DQ
CAS Latency = 3 (BANK n)
NOTE: 1. DQM is HIGH at T2 to pre vent D
READ WITH AUTO PRECHARGE INTERRUPTED BY A WRITE
CAS Latency = 3 (BANK m)
Figure 24
○○○○○○○○○○○○○○○○○○○
OUT
○○○○○○○○○○○○○○○○○○○○
NOP
○○○○○○○○○○○○○○○○○○
WRITE-AP
BANK
m
○○○○○○○○○○○○○○○○○
NOP
Interrupt Burst, Precharge
tRP - BANK
n
WRITE with burst of 4
12
12
D
OUT
BANK m,
COL
d
a
DIN
d
D
d+1
2
2
IN
-a+1 from contending with DIN-d at T4.
Figure 25
T6
○○○○○○○○○○○○○○○○○
T7
○○○○○○○○○○○○○○○○○
NOP
tWR-BANK
2
2
D
d+2
IN
D
d+3
IN
NOP
Idle
m
Write back
2
2
23
23
Don’t Care
AS4SD4M16
Rev. 1.5 10/01
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WRITE with AUT O PRECHARGE
3. Interrupted by a READ (with or without AUTO
PRECHARGE): A READ to bank m will interrupt a
WRITE on bank n when registered, with the data-out
appearing CAS latency later. The PRECHARGE to bank
will begin after
t
is met, where tWR begins when the
WR
READ to bank m is registered. The last valid WRITE to
bank n will be data-in registered one clock prior to the
READ to bank m (Figure 26).
T0 T1 T2 T3 T4 T5
CLK
○○○○○○○○○○○○○○○○
NOP
COMMAND
BANK n
○○○○○○○○○○○○○○○○
NOP
Page Active
○○○○○○○○○○○○○○○
WRITE-AP
BANK
WRITE with burst of 4
n
Internal
States
BANK m
ADDRESS
DQ
23
23
Page Active
BANK n,
COL
a
DIN
a
2
2
D
a+1
IN
4 Interrupted by a WRITE (with or without AUTO
PRECHARGE): A WRITE to bank m will interrupt a
WRITE on bank n when registered. The PRECHARGE to
t
bank n will begin after
is met, where tWR begins when
WR
the WRITE to bank m is registered. The last valid data
WRITE to bank n will be data registered one clock prior
to a WRITE to bank 1 (Figure 27).
OUT
d
T7
○○○○○○○○○○○○○○○
Precharge
○○○○○○○○○○○○○○○○○○
WRITE-AP
BANK
m
○○○○○○○○○○○○○○○○○
NOP
Interrupt Burst, Write back
tWR - BANK
READ with burst of 4
BANK m,
COL
d
23
23
CAS Latency = 3 (BANK m)
○○○○○○○○○○○○○○○○○
NOP
t
n
RP
2
2
-BANK
T6
○○○○○○○○○○○○○○○○○○
NOP
n
2
2
D
NOP
t
RP
2
2
D
OUT
-BANK
d+1
m
NOTE: DQM is LOW .
WRITE WITH AUTO PRECHARGE INTERRUPTED BY A READ
T0 T1 T2 T3 T4 T5
CLK
COMMAND
BANK n
NOP
Page Active
Internal
States
BANK m
2
ADDRESS
2
DQ
NOTE: DQM is LO W.
WRITE WITH AUTO PRECHARGE INTERRUPTED BY A WRITE
○○○○○○○○○○○○○○○○
○○○○○○○○○○○○○○○
WRITE-AP
BANK
n
WRITE with burst of 4
Page Active
BANK n,
COL
a
DIN
a
Figure 26
○○○○○○○○○○○○○○○○
NOP
2
2
D
IN
a+1
○○○○○○○○○○○○○○○
NOP
Interrupt Burst, Write back
tWR - BANK
WRITE with burst of 4
23
23
D
IN
a+2
Figure 27
○○○○○○○○○○○○○○○
WRITE-AP
BANK
m
BANK m,
COL
d
D
IN
d
○○○○○○○○○○○○○○○
NOP
n
D
IN
d+1
t
RP
2
2
-BANK
T6
n
D
d+2
○○○○○○○○○○○○○○○
NOP
2
2
IN
T7
○○○○○○○○○○○○○○○
NOP
Precharge
t
WR
Write back
2
2
D
IN
d+3
-BANK
2
2
Don’t Care
m
AS4SD4M16
Rev. 1.5 10/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
24
Page 25
Austin Semiconductor, Inc.
SDRAM
AS4SD4M16
TRUTH TABLE 2-CKE
CKE
n-1
CKE
CURRENT STATE COMMAND
n
1,2,3,4
n
ACTION
n
Power-Down X Maintain Power-Down
LL
Self Refresh X Maintain Self Refresh
Clock Suspend X Maintain Clock Suspend
Power-Down COMMAND INHIBIT or NOP Exit Power-Down 5
HL
Self Refresh COMMAND INHIBIT or NOP Exit Self Refresh 6
Clock Suspend X Exit Clock Suspend 7
All Banks Idle COMMAND INHIBIT or NOP Power-Down Entry
LH
All Banks Idle AUTO REFRESH Self Refresh Entry
Reading or Writing VALID Clock Suspend Entry
HH
See Truth Table 3
NOTE:
1 . CKE n is the logic state of CKE at clock edge n; CKE n-1 was the state of CKE at the previous clock edge.
2 . Current state is the state of the SDRAM immediately prior to clock edge n.
3 . COMMAND n is the command registered at clock edge n, and ACTION n is a result of COMMAND n .
4. All states and sequences not shown are illegal or reserved.
5 . Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1
(provided that t
6 . Exiting self refresh at clock edge n will put the device in the all banks idle state once t
INHIBIT or NOP commands should be issued on any clock edges occurring during the t
minimum of two NOP commands must be provided during t
CKS
is met).
XSR
period.
is met. COMMAND
XSR
period. A
XSR
7 . After exiting clock suspend at clock edge n, the device will resume operation and recognize the next
command at clock edge n + 1.
NOTES
AS4SD4M16
Rev. 1.5 10/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
25
Page 26
SDRAM
AS4SD4M16
Austin Semiconductor, Inc.
TRUTH TABLE 3 - CURRENT STATE BANK n - COMMAND TO BANK n
(Notes 1 to 6; notes appear below and on next page)
CURRENT STATE CS\ RAS\ CAS\ WE\ COMMAND (ACTION) NOTES
ANY
Idle
Row Active
Read ( Auto-
Precharge
Disabled)
Write ( Auto-
Precharge
Disabled)
NOTE:
1. This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Truth Table 2) and after t
state was self refresh).
2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown are those allowed
to be issued to that bank when in that state. Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and
Row Active: A row in the bank has been activated, and
Read: A READ burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been
Write: A WRITE burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been
4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or
allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the
other bank are determined by its current state and Truth Table 3, and according to Truth Table 4.
Precharge Enabled: Starts with registration of a READ command with AUTO PRECHARGE enabled and ends when
Precharge Enabled: Starts with registration of a WRITE command with AUTO PRECHARGE enabled and ends when
AS4SD4M16
Rev. 1.5 10/01
H X X X COMMAND INHIBIT (NOP/Continue previous operation)
L H H H NO OPERATION (NOP/Continue previous operation)
L L H H ACTIVE (Select and activate row)
L L L H AUTO REFRESH 7
L L L L LOAD MODE REGISTER 7
L L H L PRECHARGE 11
L H L H READ (Select column and start READ burst) 10
L H L L WRITE (Select column and start WRITE burst) 10
L L H L PRECHARGE (Deactivate row in bank or banks) 8
L H L H READ (Select column and start new READ burst) 10
L H L L WRITE (Select column and start WRITE burst) 10
L L H L PRECHARGE (Truncate READ burst, start PRECHARGE) 8
L H H L BURST TERMINATE 9
L H L H READ (Select column and start READ burst) 10
L H L L WRITE (Select column and start new WRITE burst) 10
L L H L PRECHARGE (Truncate WRITE burst, start PRECHARGE) 8
L H H L BURST TERMINATE 9
has been met (if the previous
XSR
tRP has been met.
t
has been met. No data bursts/accesses and no register accesses are
in progress.
terminated.
terminated.
Precharging: Starts with registration of a PRECHARGE command and ends when t
the bank will be in the idle state.
Row Activating: Starts with registration of an ACTIVE command and ends when t
bank will be in the row active state.
Read w/Auto-
t
has been met. Once tRP is met, the bank will be in the idle state.
Write w/Auto-
RP
t
has been met. Once tRP is met, the bank will be in the idle state.
RP
RCD
is met. Once tRP is met,
RP
is met. Once t
RCD
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
26
is met, the
RCD
Page 27
SDRAM
AS4SD4M16
Austin Semiconductor, Inc.
NOTE (continued):
5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be
applied on each positive clock edge during these states.
Refreshing: Starts with registration of an AUTO REFRESH command and ends when t
Once t
Accessing Mode
Register: Starts with registration of a LOAD MODE REGISTER command and ends when t
has been met. Once t
Precharging All: Starts with registration of a PRECHARGE ALL command and ends when t
Once t
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging.
9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank..
10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with AUTO PRECHARGE enabled and
READs or WRITEs with AUTO PRECHARGE disabled.
11. Does not affect the state of the bank and acts as a NOP to that bank.
is met, the SDRAM will be in the all banks idle state.
RC
is met, the SDRAM will be in the all banks idle state.
MRD
is met, all banks will be in the idle state.
RP
is met.
RC
RP
MRD
is met.
AS4SD4M16
Rev. 1.5 10/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
27
Page 28
SDRAM
AS4SD4M16
Austin Semiconductor, Inc.
TRUTH TABLE 4 - CURRENT STATE BANK n - COMMAND TO BANK m
(Notes: 1-6; notes appear below and on next page)
CURRENT STATE CS\ RAS\ CAS\ WE\ NOTES
Any
Idle X X X X
Row Activating,
Active or
Precharging
Read
(Auto-
Precharge Disabled)
Write
(Auto-
Precharge Disabled)
Read
(with Auto-
Precharge)
Write
(with Auto-
Precharge)
HXXX
LHHH
LLHH
LHLH 7
LHLL 7
LLHL
LLHH
L H L H 7, 10
L H L L 7, 11
L
L
L
L
L
L
L
L H L L 7, 8 15
LLHL 9
LLHH
L H L H 7, 8 16
L H L L 7, 8 17
LLHL 9
LHL 9
LHH
H L H 7, 1
H L L 7, 13
LHL 9
LHH
H L H 7, 8 ,14
COMMAND/ACTION
COMMAND INHIBIT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
Any command otherwise allowed to bank m
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
NOTE:
1. This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Truth Table 2) and after t
was self refresh).
2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the commands shown are
those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are
covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and t
Row Active: A row in the bank has been activated, and t
has been met.
RP
RCD
has been met. No data bursts/ accesses and no register
accesses are in progress.
Read: A READ burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been
terminated.
Write: A WRITE burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been
terminated.
Read w/Auto-
Precharge Enabled: Starts with registration of a READ command with AUTO PRECHARGE enabled, and ends when t
been met. Once t
is met, the bank will be in the idle state.
RP
Write w/Auto-
Precharge Enabled: Starts with registration of a WRITE command with AUTO PRECHARGE enabled, and ends when t
been met. Once t
is met, the bank will be in the idle state.
RP
4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with AUTO PRECHARGE
enabled and READs or WRITEs with AUTO PRECHARGE disabled.
has been met (if the previous state
XSR
RP
RP
has
has
AS4SD4M16
Rev. 1.5 10/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
28
Page 29
SDRAM
AS4SD4M16
Austin Semiconductor, Inc.
NOTE (continued):
8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the AUTO PRECHARGE command when its burst has been interrupted
by bank m’s burst.
9. Burst in bank n continues as initiated.
10. For a READ without AUTO PRECHARGE interrupted by a READ (with or without AUTO PRECHARGE), the READ to bank m
will interrupt the READ on bank n, CAS latency later (Figure 7).
11. For a READ without AUTO PRECHARGE interrupted by a WRITE (with or without AUTO PRECHARGE), the WRITE to bank
m will interrupt the READ on bank n when registered (Figures 9 and 10). DQM should be used one clock prior to the WRITE
command to prevent bus contention.
12. For a WRITE without AUTO PRECHARGE interrupted by a READ (with or without AUTO PRECHARGE), the READ to bank m
will interrupt the WRITE on bank n when registered (Figure 17), with the data-out appearing CAS latency later. The last valid WRITE
to bank n will be data-in registered one clock prior to the READ to bank m.
13. For a WRITE without AUTO PRECHARGE interrupted by a WRITE (with or without AUTO PRECHARGE), the WRITE to bank
m will interrupt the WRITE on bank n when registered (Figure 15). The last valid WRITE to bank n will be data-in registered one clock
prior to the READ to bank m.
14. For a READ with AUTO PRECHARGE interrupted by a READ (with or without AUTO PRECHARGE), the READ to bank m will
interrupt the READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered
(Figure 24).
15. For a READ with AUTO PRECHARGE interrupted by a WRITE (with or without AUTO PRECHARGE), the WRITE to bank m
will interrupt the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus
contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 25).
16. For a WRITE with AUTO PRECHARGE interrupted by a READ (with or without AUTO PRECHARGE), the READ to bank m
will interrupt the WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank n will
begin after t
registered one clock prior to the READ to bank m (Figure 26).
17. For a WRITE with AUTO PRECHARGE interrupted by a WRITE (with or without AUTO PRECHARGE), the WRITE to bank m
will interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after t
the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior to the WRITE to bank m
(Figure 27).
is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in
WR
is met, where tWR begins when
WR
AS4SD4M16
Rev. 1.5 10/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
29
Page 30
Austin Semiconductor, Inc.
SDRAM
AS4SD4M16
ABSOLUTE MAXIMUM RATINGS*
Voltage on VDD/VDDQ Supply
Relative to VSS ........................................ -1V to +4.6V
Voltage on Inputs, NC or I/O Pins
Relative to VSS ........................................ -1V to +4.6V
Operating Temperature, T
Storage Temperature (plastic) ................-55°C to +150°C
Power Dissipation ................................................. 1W
(ambient)........-55°C to +125°C
A
*Stresses greater than those listed as “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only, and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
≤ Τ ≤ Τ
(Notes: 1, 6) (-55°
PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES
Supply Voltage
Input High (Logic 1) Voltage, all inputs
Input Low (Logic 0) Voltage, all inputs
INPUT LEAKAGE CURRENT
Any input 0V<
(All other pins not under test = 0V)
OUTPUT LEAKAGE CURRENT (DQs are disabled; 0V<
OUTPUT LEVELS
Output High Voltage (I
Output Low Voltage (I
≤ ≤
≤ Τ
≤ +125 °C ; VDD/VDDQ =+3.3 V +0.3V)
≤ Τ ≤ Τ
≤ ≤
Α Α
Α
Α Α
VIN<V
DD
= -4mA)
OUT
= 4mA)
OUT
V
OUT<VDD
V
DD/VDD
Q) I
Q
3 3.6 V
V
IH
V
IL
I
I
OZ
V
OH
V
OL
2.2
-0.5 0.7 V 23
-5 5 µΑ
-5 5
2.4 -- V
-- 0.4 V
+0.3
V
DD
V23
µΑ
IDD SPECIFICA TIONS AND CONDITIONS
1, 6, 11, 13
+3 , <:=5 &65 1@/
0 &/ ;
( ( .&/ %
)85(<*
012 ! 3&45/%0&4( &65
)) 78(9 :6)5 "+;
( ( .&/ %
012 <:=5 &65 ",
-,
)) 78(9 8<:=5 8.5/
( ( .&/ %
5 & 8<<55 :( >/&?/5
+3 , ! 1@/ &65 &(:(@&@ 7@/
0 &/ ;
( ( .&/ %
)) 78(9 8<:=5 )85(<*
+
", -,
( ( .&/ %
µ
(-55°C<TA <+125 °C; VDD/VDDQ =+3.3 V +0.3V)
! "#
AS4SD4M16
Rev. 1.5 10/01
$ % & ' &()*
30
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Page 31
SDRAM
UNITS
NOTES
AS4SD4M16
Austin Semiconductor, Inc.
CAPACITANCE
PARAMETER
Input Capacitance: CLK
Input Capacitance: All other input-only pins
Input/Output Capacitance: DQs
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 5, 6, 8, 9, 11) (-55oC<TA<+125oC)
Access time from CLK (pos. edge)
Address hold time
Address setup time
CLK high-level width
CLK low-level width
Clock cycle time
CKE hold time
CKE setup time
CS#, RAS#, CAS#, WE#, DQM hold time
CS#, RAS#, CAS#, WE#, DQM setup time
Data-in hold time
Data-in setup time
Data-out high-impedance time
Data-out low-impedance time
Data-out hold time
ACTIVE to PRECHARGE command
AUTO REFRESH, ACTIVE command period
ACTIVE to READ or WRITE delay
Refresh period (4,096 rows)
Refresh period (4,096 rows)
-40 to +85 degrees C
-55 to +125 degrees C
PRECHARGE command period
ACTIVE bank A to ACTIVE bank B command
Transition time
WRITE recovery time
Exit SELF REFRESH to ACTIVE command
AS4SD4M16
Rev. 1.5 10/01
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
A2 version
SYMBOL MAX
C
C
C
t
t
t
t
t
CH
t
t
t
t
CKH
t
CKS
t
CMH
t
CMS
t
DH
t
t
t
t
t
OH
t
RAS
t
RC
t
RCD
t
REF
t
REF
t
t
RRD
t
WR
t
XSR
AC
AC
AH
AS
CL
CK
CK
DS
HZ
HZ
LZ
RP
t
I1
I2
IO
T
4.0 pF 2
5.0 pF 2
6.5 pF 2
-8 -10
MIN MAX MIN MAX
11ns
23ns
3 3.5 ns
3 3.5 ns
810ns24
12 15 ns 22, 24
11ns
23ns
11ns
23ns
11ns
23ns
11ns
2.5 2.5 ns
50 80,000 60 80,000 ns
80 90 ns 22
20 30 ns 22
24 30 ns 22
20 20 ns
0.3 1.2 1 1.2 ns 7
1 CLK + 1 CLK + - 25
8ns 8ns
15 15 ns 26
80 90 ns 20
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
31
UNITS
NOTESPARAMETER SYM
6.5 7 ns
99ns22
68ns10
710ns10
64 64 ms
16 16 ms
Page 32
Austin Semiconductor, Inc.
-8
SDRAM
AS4SD4M16
AC FUNCTIONAL CHARACTERISTICS
5, 6, 7, 8, 9, 11
(-55oC<TA<+125oC)
PARAMETER
READ/WRITE command to READ/WRITE command
CKE to clock disable or power-down entry mode
CKE to clock enable or power-down exit setup mode
DQM to input data delay
DQM to data mask during WRITEs
DQM to data high-impedance during READs
WRITE command to input data delay
Data-in to ACTIVE command A2 version t
Data-in to PRECHARGE command A1 version A2 version t
Last data-in to burst STOP command
Last data-in to new READ/WRITE command
Last data-in to PRECHARGE command A2 version t
LOAD MODE REGISTER command to ACTIVE or REFRESH command
Data-out to high-impedance from PRECHARGE command
CL = 3 t
CL = 2 t
SYMBOL
t
CCD
t
CKED
t
PED
t
DQD
t
DQM
t
DQZ
t
DWD
DAL
DPL
t
BDL
t
CDL
RDL
t
MRD
ROH
ROH
-10 UNITS NOTES
11
11
11
00
00
22
00
54
22
11
11
22
22
33
22
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
17
14
14
17
17
17
17
15, 21
16, 21
17
17
16, 21
27
17
17
ELECTRICAL TIMING CHARACTERISTICS for -8 SPEED
(-55oC<TA<+125oC)
-8
PARAMETER
CL = 3
Access times from CLK (pos. edge)
CL = 2
CL = 3
Clock cycle time
CL = 2
ACTIVE to READ or WRITE delay
PRECHARGE command period
AUTO REFRESH, ACTIVE command period
WRITE recovery time A2 Version
100 MHz Speed Reference (CL -t
AS4SD4M16
Rev. 1.5 10/01
RCD-tRP
)
SYM UNITS NOTES
t
AC
t
AC
t
CK
t
CK
t
RCD
t
RP
t
RCD
t
WR
32
MIN MAX
--- 6 ns 22
--- 9 ns 22
8 --- ns 22
12 --- ns 22
20 --- ns 22
24 --- ns 22
80 ---
2 --- --- ---
3-2-3
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5, 6, 7, 8, 9, 11, 24
t
CK
21
CLKs ---
Page 33
NOTES
SDRAM
AS4SD4M16
Austin Semiconductor, Inc.
1 . All voltages referenced to VSS.
2 . This parameter is sampled. VDD, VDDQ = +3.3V ; f = 1
MHz, TA = 25°C; pin under test biased at 1.4V.
3. IDD is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle time
and the outputs open.
4. Enables on-chip refresh and address counters.
5 . The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range (-55°C ≤ TA ≤ +125°C) is ensured.
6 . An initial pause of 100µs is required after power-up,
followed by two AUTO REFRESH commands, before
proper device operation is ensured. (VDD and VDDQ must
be powered up simultaneously. VSS and VSSQ must be at
same potential.) The two AUTO REFRESH command
wake-ups should be repeated any time the t
requirement is exceeded.
7 . AC characteristics assume t
8 . In addition to meeting the transition rate specification,
the clock and CKE must transit between VIH and VIL (or
between VIL and VIH) in a monotonic manner.
9 . Outputs measured at 1.5V with equivalent load:
10. tHZ defines the time at which the output achieves the
open circuit condition; it is not a reference to VOH or
VOL. The last valid data element will meet tOH before
going High-Z.
11 . AC timing and I
timing referenced to 1.5V crossover point.
tests have VIL = 0V and VIH = 3V , with
CC
= 1ns.
T
REF
refresh
Q
50pF
12. Other input signals are allowed to transition no more
than once in any 30ns period (20ns on -8) and are
otherwise at valid VIH or VIL levels.
13. IDD specifications are tested after the device is properly
initialized.
14. Timing actually specified by t
reference only at minimum cycle rate.
15. Timing actually specified by tWR plus tRP; clock(s)
specified as a reference only at minimum cycle rate.
16 . Timing actually specified by tWR.
17 . Required clocks are specified by JEDEC functionality
and are not dependent on any timing parameter.
18. The ICC current will decrease as the CAS latency is
reduced. This is due to the fact that the maximum cycle
rate is slower as the CAS latency is reduced.
19. Address transitions average one transition every 30ns
(20ns on -8).
20 . CLK must be toggled a minimum of two times during this
period.
21 . Based on tCK = 100 MHz for -8 and 66 MHz for -10.
22. These five parameters vary between speed grades and
define the differences between the -8 SDRAM speeds:
-8.
23. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse
width ≤ 10ns, and the pulse width cannot be greater than
one third of the cycle rate. VIL undershoot: VIL (MIN) =
-2V for a pulse width ≤ 10ns, and the pulse width cannot
be greater than one third of the cycle rate.
24. The clock frequency must remain constant during access
or precharge states (READ, WRITE, including tWR, and
PRECHARGE commands). CKE may be used to reduce
the data rate.
25. Auto precharge mode only. The precharge timing budget
( tRP) begins 8ns after the first clock delay , after the last
WRITE is executed.
26 . Precharge mode only.
27 . JEDEC and PC100 specify three clocks.
; clock(s) specified as a
CKS
AS4SD4M16
Rev. 1.5 10/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
33
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4
4
5
5
4
4
4
4
4
4
12
12
12
12
4
4
4
4
4
4
4
4
3
3
0
0
1
1
4
4
4
4
1
1
1
1
1
1
4
4
4
4
4
4
1234
1234
1234
1234
1234
1
1
1
12345
12345
12345
12345
12345
6
6
6
4
4
4
4
4
4
4
4
SDRAM
AS4SD4M16
CLK
CKE
COMMAND
DQM /
DQML,
DQMH
A0-A9, A11
A10
BA0, BA1
t
AH
t
AH
23
23
2
23
23
23
23
23
NOP
23
23
ACTIVE
ROW
ROW
23
23
23
23
23
23
23
INITIALIZE AND LOAD MODE REGISTER
T0 T1 Tn+1 To+1 Tp+1 Tp+2 Tp+3
t
CK
t
t
CKStCKH
NOP
t
CMS
23
23
t
CMH
PRECHARGE
ALL BANKS
t
CMS
23
23
234
234
t
CMH
2
2
2345678901234567890123456789012123456789012345678901234567890121234567890123456789
2345678901234567890123456789012123456789012345678901234567890121234567890123456789
234567890123456789012345678901212345678901234567890
234567890123456789012345678901212345678901234567890
234567890
234567890
234567890
CH
23
23
t
t
CMS
CMH
AUTO
REFRESH
2345678901234567890123456789012
2345678901234567890123456789012
2345678901234567890123456789012
NOP NOP
23
23
t
CL
AUTO
REFRESH
23
23
NOP NOP
23
23
LOAD MODE
REGISTER
t
AS
t
AS
CODE
CODE
SINGLE BANK
234567890
234567890
234567890
ALL
BANKS
2345678901234567890123456789012123456789012345
2345678901234567890123456789012123456789012345
2345678901234567890123456789012123456789012345
BANK
23
23
23
DQ
T=100s
Power-up:
VDD and
CLK stable
High-Z
t
RP
Precharge
all banks
t
RC
t
RC
AUTO REFRESH AUTO REFRESH
TIMING P ARAMETERS
-8 -10
SYMBOL* UNITS
t
AH
t
AS
t
CH
t
CL
t
CK (3)
t
CK (2)
t
CKH
MIN MAX MIN MAX
11ns
23ns
3 3.5 ns
3 3.5 ns
810ns
12 15 ns
11ns
SYMBOL* UNITS
t
CKS
t
CMH
t
CMS
t
MRD (3)
t
RC
t
RP
* CAS latency indicated in parentheses.
NOTE: 1 . The Mode Register may be loaded prior to the AUTO REFRESH cycles if desired.
2. If CS is HIGH at clock high time, all commands applied are NOP, with CKE a “Don’t Care”.
3. JEDEC and PC100 specify three clocks.
4. Outputs are guaranteed High-Z after command is issued.
AS4SD4M16
Rev. 1.5 10/01
34
MIN MAX MIN MAX
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
t
MRD
Program Mode Register
1,3,4
23
23
23
Don’t Care
Undefined
-8 -10
2 3 ns
1 1 ns
2 3 ns
2 2
t
CK
80 90 ns
24 30 ns
Page 35
Austin Semiconductor, Inc.
3
3
3
3
3
3
3
4
4
4
4
4
4
7
7
7
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901
1
1
1
1
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901
6
6
3
3
6
6
3
3
6
6
3
3
3
4
4
SDRAM
AS4SD4M16
CLK
CKE
COMMAND
DQM /
DQML,
DQMH
A0-A9, A11
A10
POWER-DOWN MODE
T0 T1 T2 Tn +1 Tn +2
t
CK
2
2
t
CKS
t
CMS
PRECHARGE
23456789012345678901234567890121234567890123456789012345678901212345678901234567890
23456789012345678901234567890121234567890123456789012345678901212345678901234567890
23456789012345678901234567890121234567890123456789012345678901212345
23456789012345678901234567890121234567890123456789012345678901212345
ALL BANKS
t
CKH
t
CMH
23
23
NOP
23456789012345678901234567890121234567890123456789012345
23456789012345678901234567890121234567890123456789012345
t
CL
t
CH
t
CK
NOP
23456789012
23456789012
23456789012
23456789012
23456789012
2345678901234567890123456
2345678901234567890123456
2345678901234567890123456
1
t
CK
23
23
23
23
NOP ACTIVE
ROW
ROW
SINGLE BANK
2
2
2
2
t
t
AS
AH
23456789012345678901234567890121234567890123456789012345
BA0, BA1
DQ
BANK(S)
High-Z
23456789012345678901234567890121234567890123456789012345
Two clock cycles
Precharge all
active banks
All banks idle, enter
power-down mode
TIMING P ARAMETERS
-8 -10
MIN MAX MIN MAX
t
AH
t
AS
t
CH
t
CL
t
CK (3)
* CAS latency indicated in parentheses.
11ns
23ns
3 3.5 ns
3 3.5 ns
810ns
Input bufferd gated off while in
power-down mode
Exit power-down mode
UNITSSYMBOL*
t
CK (2)
t
CKH
t
CKS
t
CMH
t
CMS
MIN MAX MIN MAX
12 15 ns
11ns
23ns
11ns
23ns
All banks idle
-8 -10
BANK
2
23
23
UNITSSYMBOL*
Don’t Care
Undefined
2
2
NOTE: 1 . Violating refresh requirements during power-down
may result in a loss of data.
AS4SD4M16
Rev. 1.5 10/01
35
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Page 36
Austin Semiconductor, Inc.
12
12
12
12
4
4
4
12
12
12
12
4
4
1234
1234
1234
1234
4
4
4
4
4
4
4
4
5
5
7
7
0
0
4
4
5
5
12
12
12
12
3
3
12
12
12
12
4
4
6
6
6
8
8
8
12
2
2
2
12
0
0
0
1
1
1
6
6
8
8
5
5
5
1234
1234
1234
1234
1234
4
4
7
7
4
4
4
SDRAM
AS4SD4M16
CLK
CKE
COMMAND
DQM /
DQML,
DQMH
A0-A9,
A11
A10
BA0,
BA1
DQ
CLOCK SUSPEND MODE
T0 T1 T2 T4 T6 T7 T8 T9T3 T5
t
23
23
23
t
CKS
t
CMStCMH
READ
23456789
23456789
t
AS
COLUMN m
t
AS
1
1
1
t
AS
BANK
CK
23
23
t
CKH
NOP
t
CMStCMH
t
t
t
AH
AH
AH
2345678901234567890123456789012123456789012345
2345678901234567890123456789012123456789012345
2
2345678901234567890123456789012123456789012345
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
2345678901234567890123456789012123456789012345
2345678901234567890123456789012123456789012345
23
23
t
t
CL
t
CH
CKStCKH
NOP
t
LZ
234
234
23456789012345678901234567890121234
23456789012345678901234567890121234
t
AC
234
234
234
NOP
DOUT m
t
AC
23
23
t
OH
NOP
DOUTm+1
t
HZ
23
23
1
NOP
23456
WRITE
COLUMN e
BANK
t
DS
23
23
DOUT a DOUT a-1
23456
23456789012
23456789012
2345678901234567
2345678901234567
2
2345678901234567
2345678901234567890
2345678901234567890
2345678901234567890
2345678901234567
2345678901234567
t
DH
23456
23456
23
23
23
23
23
23
23
NOP
23
23
Don’t Care
Undefined
TIMING P ARAMETERS
-8 -10
SYMBOL* UNITS
t
AC(3)
t
AC(2)
t
AH
t
AS
t
CH
t
CL
t
CK(3)
t
CK(2)
t
CKH
MIN MAX MIN MAX
6.5 7 ns
99ns
11ns
23ns
3 3.5 ns
3 3.5 ns
810ns
12 15 ns
11ns
SYMBOL* UNITS
t
CKS
t
CMH
t
CMS
t
DH
t
DS
t
HZ(3)
t
HZ(2)
t
LZ
t
OH
* CAS latency indicated in parentheses.
NOTE: 1 . For this example, the burst length = 2, the CAS latency = 3, and AUTO PRECHARGE is disabled.
2. x16: A8, A9 and A11 = “Don’t Care.”
AS4SD4M16
Rev. 1.5 10/01
36
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
-8 -10
MIN MAX MIN MAX
23ns
11ns
23ns
11ns
23ns
68ns
710ns
11ns
2.5 2.5 ns
Page 37
Austin Semiconductor, Inc.
3
3
4
4
4
4
12
12
12
12
4
4
7
7
2
2
0
0
4
4
0
0
5
5
4
4
4
4
4
4
4
4
12
12
12
12
12
4
4
3
3
5
5
SDRAM
AS4SD4M16
CLK
CKE
COMMAND
DQM /
DQML,
DQMH
A0-A9,
A11
A10
BA0, BA1
23
23
1
NOP
NOP
23
23
ACTIVE
ROW
ROW
23
23
23
23
23
23
AUTO REFRESH MODE
T0 T1 T2
t
CK
t
CH
2
2
t
CKS
t
CMS
PRECHARGE
2345678901234567890123456789012123456789012345678901234567890121234567890123456
2345678901234567890123456789012123456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456789012345678901
23456789012345678901234567890121234567890123456789012345678901
ALL BANKS
t
CKH
t
CMH
23
23
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
NOP
23
23
AUTO
REFRESH
23
23
NOP NOP
Tn +1 To +1
t
CL
23
23
AUTO
REFRESH
SINGLE BANK
t
t
AS
AH
BANK(S)
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
BANK
234
234
High-Z
DQ
t
RP
t
RC
t
RC
234
234
2
2
Don’t Care
Undefined
TIMING P ARAMETERS
-10-8
SYMBOL* UNITS
t
AH
t
AS
t
CH
t
CL
t
CK (3)
t
CK (2)
MIN MAX MIN MAX
1 1 ns
2 3 ns
3 3.5 ns
3 3.5 ns
8 10 ns
12 15 ns
* CAS latency indicated in parentheses.
SYMBOL* UNITS
t
CKH
t
CKS
t
CMH
t
CMS
t
RC
t
RP
MIN MAX MIN MAX
11ns
23ns
11ns
23ns
80 90 ns
24 30 ns
NOTE: 1. Each AUTO REFRESH command performs a refresh cycle. Back-to-back commands are not required.
AS4SD4M16
Rev. 1.5 10/01
37
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
-10-8
Page 38
Austin Semiconductor, Inc.
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3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
5
5
2
2
2
2
2
2
0
0
0
0
0
4
4
4
SDRAM
AS4SD4M16
CLK
CKE
COMMAND
DQM /
DQML,
DQMH
A0-A9, A11
A10
BA0, BA1
NOP
1
TT
23
23
23
t
CKS
23
23
23
AUTO
REFRESH
SELF REFRESH MODE
TTT
t
CK
2
2
2
t
CKS
t
CMS
PRECHARGE
234567890123456789012345678901212345678901234567890123456789012123456789012345678901
234567890123456789012345678901212345678901234567890123456789012123456789012345678901
234567890123456789012345678901212345678901234567890123456789012123456789012345678901
234567890123456789012345678901212345678901234567890123456789012123456789012345678901
234567890123456789012345678901212345678901234567890123456789012123456789012345678901
234567890123456789012345678901212345678901234567890123456789012123456789012345678901
ALL BANKS
t
CKH
t
CMH
23
23
23
NOP
234567890123456789012345678901212345678901234567890123456789012123456789
234567890123456789012345678901212345678901234567890123456789012123456789
t
CL
t
CH
t
CKS
AUTO
REFRESH
23456789012
23456789012
23456789012
23456789012
23456789012
t
RAS
2345678901234
2345678901234
T
SINGLE BANK
t
t
AS
AH
BANK(S)
234567890123456789012345678901212345678901234567890123456789012123456789
234567890123456789012345678901212345678901234567890123456789012123456789
234567890123456789012345678901212345678901234567890123456789012123456789
High-Z
DQ
Precharge all
active banks
t
RP
Enter self refresh mode
CLK stable prior to exiting
Exit self refresh mode
(Restart refresh time base)
self refresh mode
t
XSR
23
23
23
Don’t Care
Undefined
TIMING P ARAMETERS
-8 -10
SYMBOL* UNITS
t
AH
t
AS
t
CH
t
CL
t
CK(3)
t
CK(2)
t
CKH
* CAS latency indicated in parentheseses.
MIN MAX MIN MAX
11ns
23ns
34ns
34ns
810ns
12 15 ns
SYMBOL* UNITS
t
CKS
t
CMH
t
CMS
t
RAS
t
RP
t
XSR
11ns
NOTE: 1. Self Refresh Mode available on Industrial T emperature Range option only .
AS4SD4M16
Rev. 1.5 10/01
38
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
-8 -10
MIN MAX MIN MAX
23ns
11ns
23ns
50 80,000 60 80,000 ns
24 30 ns
80 90 ns
Page 39
Austin Semiconductor, Inc.
4
4
4
5
5
5
5
5
5
5
5
5
1234567890123456789
1234567890123456789
1234567890123456789
1234567890123456789
1234567890123456789
5
5
5
5
5
5
4
4
4
0
0
0
8
8
8
5
5
5
9
9
9
7
7
7
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
2
2
2
8
8
8
0
0
5
5
5
5
5
5
12345678901234567
1
7
1
7
1
7
12345678901234567
5
5
5
5
5
5
123
123
123
123
123
123
123
4
5
5
5
SDRAM
AS4SD4M16
CLK
CKE
COMMAND
DQM /
DQML, DQMH
A0-A9,
A11
A10
READ -- WITHOUT A UT O PRECHARGE
T0 T1 T2 T3 T4 T5 T6 T7 T8
t
CKH
23
23
23
CK
t
CKS
t
CMS
t
t
CMH
ACTIVE
234
234
234
234
234
234
t
t
AH
AS
234567
234567
234567
234567
234567
234567
t
AS
t
AS
ROW
ROW
t
AH
t
AH
t
CL
t
CH
23
23
23
23
23
23
NOP READ
t
t
CMS
CMH
23
23
23
COLUMN m
DISABLE AUTO PRECHARGE
234
234
234
NOP
23
23
23
234567890123456789012345678901
234567890123456789012345678901
2
234567890123456789012345678901
23456789012345678
234567890123456789
23456789012345678
234567890123456789
23456789012345678
NOP
234
234
234
23
23
23
NOP
1
23
23
23
2345678901234567890123456789
2345678901234567890123456789
2345678901234567890123456789
SINGLE BANK
PRECHARGE
ALL BANKS
23
23
23
234
234
234
NOP
23
23
23
ACTIVE
ROW
ROW
234
234
234
234
234
234
234
234
234
NOTE: 1 . For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a “manual” PRECHARGE.
2. x16: A8, A9 and A11 = “Don’t Care.”
AS4SD4M16
Rev. 1.5 10/01
BA0, BA1
DQ
23456
BANK
t
t
RAS
t
RCD
RC
23456
23456
BANK
TIMING P ARAMETERS
-8 -10
MIN MAX MIN MAX
t
AC(3)
t
AC(2)
t
AH
t
AS
t
CH
t
CL
t
CK(3)
t
CK(2)
t
CKH
t
CKS
* CAS latency indicated in parentheseses.
6.5 7 ns
99ns
11ns
23ns
3 3.5 ns
3 3.5 ns
810ns
12 15 ns
11ns
23ns
CAS Latency
UNITSSYMBOL*
234567890123456
234567890123456
234567890123456
t
t
AC
t
LZ
AC
t
OH
D
OUT
t
CMH
t
CMS
t
HZ(3)
t
HZ(2)
t
LZ
t
OH
t
RAS
t
RC
t
RCD
t
RP
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
39
234
OUT
t
AC
t
OH
m+2
t
RP
234
234
UNITSSYMBOL*
BANK
t
OH
D
m+3
OUT
t
HZ
BANK
t
AC
t
OH
m
D
OUT
-8 -10
MIN MAX MIN MAX
m+1
D
11ns
23ns
68ns
710ns
11ns
2.5 2.5 ns
50 80,000 60 80,000 ns
80 90 ns
20 30 ns
24 30 ns
23
234
234
234
234
234
234
Don’t Care
Undefined
Page 40
Austin Semiconductor, Inc.
4
4
4
4
4
4
12
12
12
12
12
4
4
4
8
8
8
8
8
6
6
6
4
4
4
123
123
123
123
123
0
0
0
8
8
5
5
8
8
5
5
5
4
4
4
4
4
4
4
4
4
5
5
5
12345678901234567890123456789012
1
2
1
2
12345678901234567890123456789012
8
8
8
5
5
5
2
2
2
5
5
5
4
4
4
6
6
6
1234
1234
1234
1234
1234
4
4
4
3
3
5
5
SDRAM
AS4SD4M16
CLK
CKE
COMMAND
DQM /
DQML, DQMH
A0-A9,
A11
A10
BA0, BA1
T0 T1 T2
t
CKH
t
AH
t
AH
t
AH
CK
23
23
23
NOP
234567
234567
ENABLE AUTO PRECHARGE
234567
234567
234567
234567
234567
t
CKS
t
CMS
ACTIVE
234567
2345
234567
234567
2345
234567
234567
2345
t
AS
t
AS
t
AS
BANK
t
ROW
ROW
t
CMH
READ -- WITH AUTO PRECHARGE
T3 T4 T5 T6 T7 T8
23
23
23
23
23
23
NOP
23
23
23
234567890123456789012345678901212345
234567890123456789012345678901212345
234567890123456789012345678901212345
23
23
23
234567890123456789012345678901
2
234567890123456789012345678901
23456789012345678901234567890121
23456789012345678901234567890121
23456789012345678901234567890121
t
AC
NOP
AC
t
OH
23
23
23
234
234
234
NOP
t
234
234
234
t
CMS
t
CL
READ
t
CH
t
CMH
COLUMN m
BANK
1
23
23
23
2345678901234567890123456789
2345678901234567890123456789
2345678901234567890123456789
NOP
23
23
23
NOP
23
23
23
ACTIVE
ROW
ROW
BANK
t
AC
OH
AC
t
OH
t
OH
234
234
234
234
234
234
234
234
DQ
TIMING P ARAMETERS
-8 -10
MIN MAX MIN MAX
UNITSSYMBOL*
t
6.5 7 ns
AC(3)
t
99ns
AC(2)
t
11ns
AH
t
23ns
AS
t
33.5ns
CH
t
33.5ns
CL
t
810ns
CK(3)
t
12 15 ns
CK(2)
t
11ns
CKH
t
23ns
CKS
NOTE: 1 . For this example, the burst length = 4, the CAS latency = 2.
2. x16: A8, A9 and A11 = “Don’t Care.”
AS4SD4M16
Rev. 1.5 10/01
t
AC(3)
t
AC(2)
t
AH
t
AS
t
CH
t
CL
t
CK(3)
t
CK(2)
t
CKH
t
CKS
* CAS latency indicated in parentheseses.
t
t
RCD
t
RAS
t
RC
-8 -10
MIN MAX MIN MAX
CAS Latency
LZ
UNITSSYMBOL*
6.5 7 ns
99ns
11ns
23ns
3 3.5 ns
3 3.5 ns
810ns
12 15 ns
11ns
23ns
40
D
m
OUT
t
CMH
t
CMS
t
HZ(3)
t
HZ(2)
t
LZ
t
OH
t
RAS
t
RC
t
RCD
t
RP
D
OUT
-8 -10
MIN MAX MIN MAX
11ns
23ns
68ns
710ns
11ns
2.5 2.5 ns
50 80,000 60 80,000 ns
80 90 ns
20 30 ns
24 30 ns
m+1
D
m+2
D
OUT
t
RP
OUT
t
m+3
HZ
UNITSSYMBOL*
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
234
234
2
2
Don’t Care
Undefined
Page 41
Austin Semiconductor, Inc.
4
4
4
4
4
4
4
4
4
5
5
5
5
5
5
4
4
4
5
5
5
5
5
5
4
4
4
12
12
12
12
12
4
4
4
12
12
12
12
12
4
4
4
4
4
4
8
8
8
5
5
5
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
5
5
5
5
7
7
7
7
7
8
8
8
4
4
4
7
7
7
7
7
7
5
5
5
4
4
4
3
3
4
4
4
SDRAM
AS4SD4M16
CLK
CKE
COMMAND
DQM /
DQML, DQMH
A0-A9,
A11
A10
BA0, BA1
READ
2
t
AC
t
OH
23
23
23
23
23
23
1
234
234
234
23
23
23
NOP
t
t
AL TERNA TING B ANK READ ACCESSES
T0 T1 T2 T3 T4 T5 T6 T7 T8
t
t
CKH
CMH
t
AH
t
AH
t
AH
23
23
23
CK
NOP
234
234
234
234567
234567
234567
23456
23456
23456
t
CKS
t
CMS
ACTIVE
234
234
234
234
234
234
t
AS
ROW
t
AS
ROW
t
AS
BANK 0
t
t
CL
t
CH
23
23
23
23
23
23
READ
t
t
CMS
CMH
23
23
23
234
234
COLUMN m
ENABLE AUTO PRECHARGE
2
234
234
234
234
BANK 0
NOP
t
AC
23
23
23
23
23
23
ACTIVE
ROW
ROW
BANK 4
t
t
AC
OH
23
23
23
23
23
23
NOP
23
23
23
234
234
234
23456
234567
23456
23456
234567
23456
23456
234567
23456
23456
23456
23
23
23
COLUMN b
ENABLE AUTO PRECHARGE
t
AC
t
OH
BANK 4
AC
OH
23
23
23
23
23
23
ROW
ROW
ACTIVE
BANK 0
t
t
234
234
234
AC
OH
23
23
23
234
234
234
234
234
234
2345
2345
2345
DQ
t
RCD - BANK 0
t
RAS - BANK 0
t
RC - BANK 0
t
RRD
t
LZ
CAS Latency - BANK 0
m
OUT
RCD - BANK 1
D
m+1
D
m+2
D
OUT
OUT
t
RP - BANK 0
OUT
m+3
CAS Latency - BANK 1
D
b
OUT
t
RCD - BANK 0
2
2
Don’t Care
23
23
Undefined
23
D
TIMING P ARAMETERS
-8 -10
t
t
t
t
t
t
t
t
t
t
AC(3)
AC(2)
AH
AS
CH
CL
CK(3)
CK(2)
CKH
CKS
MIN MAX MIN MAX
6.5 7 ns
99ns
11ns
23ns
3 3.5 ns
3 3.5 ns
810ns
12 15 ns
11ns
23ns
UNITSSYMBOL*
t
CMH
t
CMS
t
LZ
t
OH
t
RAS
t
RC
t
RCD
t
RP
t
RRD
* CAS latency indicated in parentheseses.
NOTE: 1 . For this example, the burst length = 4, the CAS latency = 2.
2. x16: A8, A9 and A11 = “Don’t Care.”
AS4SD4M16
Rev. 1.5 10/01
41
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
-8 -10
MIN MAX MIN MAX
UNITSSYMBOL*
11ns
23ns
11ns
2.5 2.5 ns
50 80,000 60 80,000 ns
80 90 ns
20 30 ns
24 30 ns
20 20 ns
Page 42
Austin Semiconductor, Inc.
3
3
4
4
4
4
123456
6
6
6
6
6
123456
5
5
5
4
4
4
3
3
7
7
7
7
7
4
4
4
4
4
4
4
4
4
4
4
4
4
1
1
1234567890123456789012345678901212345678901234567890123456789012123456
6
6
6
1234567890123456789012345678901212345678901234567890123456789012123456
1
1
1
1
1
4
4
4
4
4
4
4
12
12
12
12
12
4
4
4
4
4
4
3
5
5
SDRAM
AS4SD4M16
CLK
CKE
COMMAND
DQM /
DQML,
DQMH
A0-A9,
A11
A10
BA0, BA1
DQ
NOP
D
1
23
23
23
23
t
AC
t
OH
m+2
OUT
NOP
D
23
23
23
23
t
AC
t
OH
m-1
OUT
BURST
TERM
D
23
23
NOP NOP
23456789012
23456789012
t
AC
t
OH
m
OUT
D
t
OH
m+1
OUT
t
HZ
READ -- FULL-PAGE BURST
T0 T1 T2 T3 T4 T5 T6 Tn+1 Tn+2 Tn+3 Tn+4
t
CKS
t
CMS
ACTIVE
234
12345
12345
234
12345
234
12345
12345
t
AS
ROW
t
AS
ROW
t
AS
BANK
t
CL
t
CKH
2
2
t
CMH
NOP
t
AH
23456
23456
t
AH
123456789012345678901234567890121234567890123456789012345678901212345
123456789012345678901234567890121234567890123456789012345678901212345
123456789012345678901234567890121234567890123456789012345678901212345
t
AH
23456
23456
23456
t
CK
t
CH
23
23
t
CMS
READ
COLUMN
23
23
t
CMH
23
23
23
2
m
BANK
23
23
NOP
23
23
23
234567890123456789012345678901212345678901234567890
234567890123456789012345678901212345678901234567890
234567890123456789012345678901212345678901234567890
234567890123456789012345678901212345678901234567890
234567890123456789012345678901212345678901234567890
t
AC
t
LZ
NOP
D
t
OUT
AC
t
23
23
23
23
NOP
23
23
23
OH
m
23
23
t
AC
t
OH
D
m+1
OUT
23
23
t
RCD
CAS Latency
256 (x16) locations within same row.
Full page completed.
Full-page burst does not self-terminate. 3
Can use BURST TERMINATE command.
TIMING P ARAMETERS
-8 -10
MIN MAX MIN MAX
t
AC(3)
t
AC(2)
t
AH
t
AS
t
CH
t
CL
t
CK(3)
t
CK(2)
t
CKH
t
CKS
6.5 7 ns
99ns
11ns
23ns
3 3.5 ns
3 3.5 ns
810ns
12 15 ns
11ns
23ns
* CAS latency indicated in parentheseses.
NOTE: 1 . For this example, the CAS latency = 2.
2. x16: A8, A9 and A11 = “Don’t Care.”
3. Page left open, no tRP.
AS4SD4M16
Rev. 1.5 10/01
UNITSSYMBOL*
t
CMH
t
CMS
t
HZ(3)
t
HZ(2)
t
LZ
t
OH
t
RCD
MIN MAX MIN MAX
11ns
23ns
11ns
2.5 2.5 ns
20 30 ns
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
42
-8 -10
UNITSSYMBOL*
68ns
710ns
234
234
2
Don’t Care
Undefined
Page 43
Austin Semiconductor, Inc.
4
4
4
4
4
4
4
4
4
4
4
4
5
5
5
6
6
6
0
0
0
8
8
8
123
123
123
123
123
7
7
7
4
4
4
5
5
5
12
12
12
12
12
4
4
4
12
12
12
12
12
5
5
5
4
4
4
8
8
8
8
8
8
7
7
7
5
5
5
3
4
4
4
8
8
SDRAM
AS4SD4M16
CLK
CKE
COMMAND
DQM /
DQML,
DQMH
A0-A9,
A11
A10
BA0, BA1
READ -- DQM OPERATION
1
T0 T1 T2 T3 T4 T5 T6 T7 T8
t
CL
t
CH
23
23
23
t
CMS
READ
t
CMH
COLUMN m
234
234
234
NOP
2
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
BANK
23
23
23
234567890123456789012345678901212345678901234567
234567890123456789012345678901212345678901234567
234567890123456789012345678901212345678901234567
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
234567890123456789012345678901212345678901234567
234567890123456789012345678901212345678901234567
t
AC
NOP
23
23
23
23
23
23
t
OH
23
23
23
NOP
2345678901234567890123456789
2345678901234567890123456789
2345678901234567890123456789
t
AC
NOP
t
AC
t
OH
234
234
234
NOP
t
CKS
t
CMS
ACTIVE
234
2345
234
2345
234
2345
t
AS
ROW
t
AS
ROW
t
AS
BANK
t
t
CMH
CKH
t
AH
t
AH
t
AH
23
23
23
t
CK
NOP
234567
234567
234567
234567
234567
234567
23456
23456
23456
234
234
234
t
OH
NOP
23
23
23
DQ
t
RCD
CAS Latency
m
OUT
t
LZ
t
t
LZ
HZ
D
m+2
D
OUT
OUT
m+3
t
HZ
2
Don’t Care
23
23
Undefined
23
D
TIMING P ARAMETERS
-8 -10
MIN MAX MIN MAX
t
AC(3)
t
AC(2)
t
AH
t
AS
t
CH
t
CL
t
CK(3)
t
CK(2)
t
CKH
t
CKS
6.5 7 ns
99ns
11ns
23ns
3 3.5 ns
3 3.5 ns
810ns
12 15 ns
11ns
23ns
UNITSSYMBOL*
t
CMH
t
CMS
t
HZ(3)
t
HZ(2)
t
LZ
t
OH
t
RCD
* CAS latency indicated in parentheseses.
NOTE: 1 . For this example, the burst length = 4 , the CAS latency = 2.
2. x16: A8, A9 and A11 = “Don’t Care.”
AS4SD4M16
Rev. 1.5 10/01
43
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
-8 -10
MIN MAX MIN MAX
UNITSSYMBOL*
11ns
23ns
68ns
710ns
11ns
2.5 2.5 ns
20 30 ns
Page 44
Austin Semiconductor, Inc.
4
4
4
4
4
4
4
4
4
4
4
4
5
5
5
5
5
5
4
4
4
9
9
9
8
8
8
5
5
5
9
9
9
7
7
7
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
2
2
2
7
7
7
123456
123456
123456
123456
123456
9
9
9
5
5
5
5
5
5
7
7
7
5
5
5
5
5
5
7
7
7
7
7
7
3
3
4
4
SDRAM
AS4SD4M16
CLK
CKE
COMMAND
DQM /
DQML,
DQMH
A0-A9,
A11
A10
BA0, BA1
DQ
WRITE -- WITHOUT AUTO PRECHARGE
T0 T1 T2 T3 T4 T5 T6 T7 T8
t
CKH
CMH
t
AH
t
AH
t
AH
23
23
23
CK
NOP
234567
234567
234567
23456
23456
23456
23456
23456
23456
t
t
CKS
t
t
CMS
ACTIVE
234
234
234
234
234
234
t
AS
ROW
t
AS
ROW
t
AS
BANK
234567890123456
234567890123456
234567890123456
t
CL
t
CH
23
23
23
23
23
23
WRITE
t
t
CMS
CMH
23
23
23
COLUMN
2
m
DISABLE AUTO PRECHARGE
BANK
t
DS
DIN m
t
t
DS
DH
DIN m+1
23
23
23
NOP
23
23
23
234567890123456789012345678901
234567890123456789012345678901
234567890123456789012345678901
23456789012345678
23456789012345678
23456789012345678
23456789012345678
23456789012345678
23456789012345678
234567890123456
234567890123456
234567890123456
t
DH
NOP
t
DS
DIN m+2
23
23
23
23
23
23
NOP
23
23
23
t
t
DH
t
DS
DH
DIN m+3
1
23
23
23
PRECHARGE
234567890123456789012345678
234567890123456789012345678
234567890123456789012345678
ALL BANKS
SINGLE BANK
BANK
2345678901234567890123456
2345678901234567890123456
2345678901234567890123456
234
234
234
234
234
234
NOP
23
23
23
ACTIVE
ROW
ROW
BANK
23
23
23
234
234
234
234
234
234
234
234
234
t
RCD
t
RAS
t
RC
TIMING P ARAMETERS
-8 -10
t
AC(3)
t
AC(2)
t
AH
t
AS
t
CH
t
CL
t
CK(3)
t
CK(2)
t
CKH
t
MIN MAX MIN MAX
11ns
23ns
3 3.5 ns
3 3.5 ns
810ns
12 15 ns
11ns
CKS
23ns
6.5 7 ns
99ns
UNITSSYMBOL*
t
CMH
t
CMS
t
DH
t
DS
t
RAS
t
RC
t
RCD
t
RP
t
WR
MIN MAX MIN MAX
11ns
23ns
11ns
23ns
50 80,000 60 80,000 ns
80 90 ns
20 30 ns
24 30 ns
15 15 ns
t
WR
-8 -10
* CAS latency indicated in parentheseses.
NOTE: 1 . For this example, the burst length = 4, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 15ns are required between <DINm+3> and the PRECHARGE command, regardless of frequency.
3. x16: A8, A9 and A11 = “Don’t Care.”
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS4SD4M16
Rev. 1.5 10/01
44
2
t
RP
2
2
Don’t Care
23
23
Undefined
UNITSSYMBOL*
Page 45
Austin Semiconductor, Inc.
4
4
4
4
4
4
4
4
4
5
5
5
5
4
4
3
3
7
7
7
1
1
6
6
6
12
12
12
12
4
4
4
4
4
4
4
4
4
3
3
3
4
4
4
12
12
12
12
12
4
4
4
4
8
8
8
6
6
2
2
7
7
7
7
7
1
1
3
3
3
4
4
4
3
4
4
SDRAM
AS4SD4M16
CLK
CKE
COMMAND
DQM /
DQML,
DQMH
A0-A9,
A11
A10
BA0, BA1
DQ
WRITE -- WITH AUTO PRECHARGE
T0 T1
t
t
CKH
t
CMH
t
t
t
AH
AH
AH
CK
23
23
23
NOP
23456
23456
23456
ENABLE AUTO PRECHARGE
23456
23456
2345
2345
2345
t
CKS
t
CMS
ACTIVE
234
234
234
234
t
AS
ROW
t
AS
ROW
t
AS
BANK
23456789012345
23456789012345
23
23
23
t
CMS
t
t
T2
CL
WRITE
COLUMN
BANK
DS
DIN m
1
T3 T4
t
CH
23
23
23
t
CMH
23
23
2
m
23456789012345678901234567890121234567890
23456789012345678901234567890121234567890
23456789012345678901234567890121234567890
23456789012345678901234567890121234567890
t
DH
23
23
23
NOP
23456789012345678901234567890121234567
23456789012345678901234567890121234567
23456789012345678901234567890121234567
2345678901234567890123456789012123456
2345678901234567890123456789012123456
2345678901234567890123456789012123456
t
t
DS
DIN m+1
DH
23
23
NOP
t
DS
DIN m+2
T5
23
23
23
NOP
23
23
t
t
DS
DH
DIN m+3
T6 T7
23
23
23
2
2
2
NOP NOP
234567890123456789012345678901212
234567890123456789012345678901212
t
DH
234567890123456789012345678901
234567890123456789012345678901
23
23
23
T8
NOP
2
2
2
T9
ACTIVE
ROW
ROW
BANK
23
23
23
t
RCD
t
RAS
t
RC
TIMING P ARAMETERS
-8 -10
MIN MAX MIN MAX
t
t
t
t
t
t
t
t
t
t
AH
AS
CH
CL
CK(3)
CK(2)
CKH
CKS
CMH
CMS
11ns
23ns
3 3.5 ns
3 3.5 ns
810ns
12 15 ns
11ns
23ns
11ns
23ns
2
t
WR
-8 -10
UNITSSYMBOL*
t
DH
t
DS
t
RAS
t
RC
t
RCD
t
RP
t
WR
MIN MAX MIN MAX
11ns
23ns
50 80,000 60 80,000 ns
80 90 ns
20 30 ns
24 30 ns
1 CLK+
1 CLK+
8ns
8ns
t
RP
2
Don’t Care
23
23
Undefined
UNITSSYMBOL*
ns
* CAS latency indicated in parentheseses.
NOTE: 1 . For this example, the burst length = 4, i.e., two-clock minimum for tWR.
2. x16: A8, A9 and A11 = “Don’t Care.”
AS4SD4M16
Rev. 1.5 10/01
45
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Page 46
Austin Semiconductor, Inc.
1 CLK+
4
4
4
4
4
4
4
4
4
1234
1234
1234
1234
1234
6
6
6
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
7
7
4
4
4
4
4
4
4
4
4
12
12
12
12
12
123
123
123
123
123
4
4
4
5
5
1234
4
4
1234
4
4
4
5
5
5
5
7
7
5
5
7
7
7
7
7
7
5
5
5
7
7
7
12
12
12
12
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
5
5
SDRAM
AS4SD4M16
CLK
CKE
COMMAND
DQM /
DQML,
DQMH
A0-A9,
A11
A10
BA0, BA1
DQ
AL TERNA TING B ANK WRITE ACCESSES
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
t
t
t
CMH
t
t
CKH
AH
t
AH
AH
23
23
23
CK
NOP
23
23
23
23456
23456
23456
23456
23456
t
CKS
t
CMS
ACTIVE
2345
2345
2345
t
AS
ROW
t
AS
ROW
t
AS
BANK 0 BANK 0
234567890123456
234567890123456
234567890123456
t
CL
t
CH
23
23
23
23
23
23
WRITE
t
t
CMS
CMH
23
23
23
COLUMN
3
m
ENABLE AUTO PRECHARGE
t
DS
234
234
234
234
t
tDSt
DH
DIN m
NOP
DH
DIN m+1
23
23
23
ACTIVE
23
23
23
ROW
ROW
BANK 1
tDSt
DH
DIN m+2 DIN m+3
23
23
23
23
23
23
NOP
23
23
23
123
123
234
234
23456
23456
23456
23
23
23
COLUMN b
ENABLE AUTO PRECHARGE
23456
23456
t
t
DS
DH
WRITE
BANK 1
t
DS
DIN b
23
23
23
3
t
DH
1
23
23
23
NOP
234567890123
234567890123
234567890123
t
DS
DIN b+1
NOP
23
23
23
234
234
t
t
DH
DS DH
DIN b+2
23
23
23
23
23
23
ACTIVE
23
23
23
23
23
23
ROW
ROW
234
BANK 0
t
t
DS DH
234
234
t
DIN b+3
23
234
234
Don’t Care
Undefined
t
RCD - BANK 0
t
RAS - BANK 0
t
RC - BANK 0
t
RRD
t
RCD - BANK 1
t
WR - BANK 0
t
RP - BANK 0
t
RCD - BANK 0
t
WR - BANK 1
TIMING P ARAMETERS
-8 -10
MIN MAX MIN MAX
t
AH
t
AS
t
CH
t
CL
t
CK(3)
t
CK(2)
t
CKH
t
CKS
t
CMH
t
CMS
11ns
23ns
3 3.5 ns
3 3.5 ns
810ns
12 15 ns
11ns
23ns
11ns
23ns
UNITSSYMBOL*
t
DH
t
DS
t
RAS
t
RC
t
RCD
t
RP
t
RRD
t
WR
* CAS latency indicated in parentheseses.
NOTES: 1. For this example, the burst length = 4, i.e., two-clock minimum for tWR.
2. Requires once clock plus time (8ns) with AUTO PRECHARGE or 15ns with PRECHARGE.
3. x16: A8, A9 and A11 = “Don’t Care.”
AS4SD4M16
Rev. 1.5 10/01
46
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
-8 -10
MIN MAX MIN MAX
UNITSSYMBOL*
11ns
22ns
50 80,000 60 80,000 ns
80 90 ns
20 30 ns
24 30 ns
20 20 ns
1 CLK+
8ns
8ns
ns
Page 47
Austin Semiconductor, Inc.
4
4
4
4
12
12
12
12
12
4
4
4
4
5
5
5
5
1234567890123456789
1234567890123456789
1234567890123456789
1234567890123456789
1234567890123456789
8
8
8
8
8
6
6
6
5
5
5
8
8
8
9
9
9
9
8
8
8
4
4
4
4
5
5
5
5
4
4
4
4
4
4
4
4
5
5
5
5
12
12
12
12
12
4
4
4
4
4
4
4
123456
123456
123456
123456
123456
3
3
3
4
4
4
1234
1234
1234
1234
1234
5
5
5
4
4
4
8
8
8
8
12
12
12
12
12
12
4
4
4
4
4
WRITE -- FULL-PAGE BURST
SDRAM
AS4SD4M16
CLK
CKE
COMMAND
DQM /
DQML,
DQMH
A0-A9,
A11
A10
BA0, BA1
DQ
T0 T1 T2 T3 T4 T5 Tn+1 Tn+2 Tn+3
t
CKS
t
CMS
ACTIVE NOP WRITE NOP
234567
2345
234567
2345
234567
234567
2345
234567
t
AS
ROW
t
AS
ROW
t
AS
BANK
2345678901234567
2345678901234567
2345678901234567
2345678901234567
t
t
CMH
t
CL
t
CK
t
CH
CKH
23
23
23
23
t
AH
t
AH
23456789012345678901234567890121234567890123456789012345678901212
23456789012345678901234567890121234567890123456789012345678901212
23456789012345678901234567890121234567890123456789012345678901212
t
AH
23
23
23
23
2345678
2345678
2345678
2345678
234567
234567
234567
t
CMS
t
DS
234
234
234
234
t
CMH
234
234
234
COLUMN
1
m
BANK
t
DH
DIN m
23
23
23
23
23
23
23
23456789012345678901234567890121234567890123
23456789012345678901234567890121234567890123
23456789012345678901234567890121234567890123
23456789012345678901234567890121234567890123
23456789012345678901234567890121234567890123
23456789012345678901234567890121234567890123
23456789012345678901234567890121234567890123
t
t
DS
DH
DIN m+1
t
DS
DIN m+2
NOP
t
DH
234
234
234
234
NOP
t
DS
DIN m+3
t
DH
23
23
23
23
234
234
234
t
DS
NOP
t
DH
DIN m-1
23
23
23
23
23
23
23
t
DS
234
234
234
234
BURST
TERM
t
DH
23
23
23
NOP
234567
234567
234567
NOTES: 1 . x16: A8, A9 and A11 = “Don’t Care.”
2.tWR must be satisfied prior to PRECHARGE command.
3. Page left open, no tRP.
AS4SD4M16
Rev. 1.5 10/01
t
RCD
TIMING P ARAMETERS
-8 -10
MIN MAX MIN MAX
t
AH
t
AS
t
CH
t
CL
t
CK(3)
t
CK(2)
t
CKH
* CAS latency indicated in parentheseses.
11ns
23ns
3 3.5 ns
3 3.5 ns
810ns
12 15 ns
11ns
Full-page burst does not
self-terminate. Can use
256 (x16) locations within same row.
Full page completed.
-8 -10
UNITSSYMBOL*
t
CKS
t
CMH
t
CMS
t
DH
t
DS
t
RCD
MIN MAX MIN MAX
23ns
11ns
23ns
11ns
23ns
20 30 ns
BURST TERMINATE
2,3
command.
UNITSSYMBOL*
23
23
Don’t Care
234
234
Undefined
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
47
Page 48
Austin Semiconductor, Inc.
5
5
5
123
123
123
123
123
6
6
6
6
6
6
2
2
2
2
9
9
9
123456
123456
123456
123456
123456
8
8
8
1234
1234
1234
1234
1234
5
5
5
1234
1234
1234
1234
1234
5
5
5
1
1
1
8
8
8
2
2
2
0
0
0
5
5
5
5
5
5
9
9
9
7
7
7
5
5
5
4
4
4
5
5
5
3
4
4
SDRAM
AS4SD4M16
CLK
CKE
COMMAND
DQM /
DQML,
DQMH
A0-A9,
A11
A10
23
23
23
234
234
234
1
234
234
234
NOP
23456789012345678901
23456789012345678901
23456789012345678901
23456789012345678901
WRITE -- DQM OPERATION
T0 T1 T2 T3 T4 T5 T6 T7
t
CK
t
t
CKS
CKH
234
234
234
t
t
CMS
CMH
ACTIVE
2345
2345
2345
2345
2345
2345
t
AS
t
AS
t
AS
ROW
ROW
t
AH
t
AH
t
AH
NOP
2345678
2345678
2345678
234567
234567
234567
t
CL
t
CH
234
234
234
WRITE
t
t
CMS
CMH
COLUMN
2
m
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
234
234
234
NOP NOP NOP
23456789012345678901234567890121234567890
23456789012345678901234567890121234567890
23456789012345678901234567890121234567890
2345678901234567890123456789012123456789
2345678901234567890123456789012123456789
2345678901234567890123456789012123456789
NOP
234
234
234
BA0, BA1
DQ
BANK
23456789012345678
23456789012345678
23456789012345678
t
RCD
TIMING P ARAMETERS
-8 -10
MIN MAX MIN MAX
t
AH
t
AS
t
CH
t
CL
t
CK(3)
t
CK(2)
t
CKH
* CAS latency indicated in parentheseses.
NOTES: 1 . For this example, the burst length = 4.
AS4SD4M16
Rev. 1.5 10/01
2. x16: A8, A9 and A11 = “Don’t Care.”
11ns
23ns
3 3.5 ns
3 3.5 ns
810ns
12 15 ns
11ns
234567
234567
234567
234567890123456789012345678901212345678901
BANK
t
t
DS
DH
DIN m
234567890123456789012345678901212345678901
234567890123456789012345678901212345678901
DH
t
t
DS
DH
234567890123456
234567890123456
234567890123456
2
Don’t Care
23
23
Undefined
234
234
234
tDSt
DIN m+2 DIN m+3
-8 -10
UNITSSYMBOL*
t
CKS
t
CMH
t
CMS
t
DH
t
DS
t
RCD
MIN MAX MIN MAX
UNITSSYMBOL*
23ns
11ns
23ns
11ns
23ns
20 30 ns
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
48
Page 49
Austin Semiconductor, Inc.
MECHANICAL DEFINITIONS
ASI Case #901 (Package Designator DG)
SDRAM
AS4SD4M16
NOTE: 1. All dimensions in inches (millimeters) or typical where noted.
2. Package width and length do not include mold protrusion; allowable mold protrusion is .01” per side.
AS4SD4M16
Rev. 1.5 10/01
MAX
MIN
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
49
Page 50
Austin Semiconductor, Inc.
ORDERING INFORMATION
EXAMPLE: AS4SD4M16DG-10/IT
SDRAM
AS4SD4M16
Device Number
AS4SD4M16 DG - 8 /*
AS4SD4M16 DG -10 /*
Package
Type
Speed ns Process
*AVAILABLE PROCESSES
IT = Industrial T emperature Range -40oC to +85oC
XT = Extended T emperature Range -55oC to +125oC
AS4SD4M16
Rev. 1.5 10/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
50
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