Datasheet AS4LC4M4E1-60TI, AS4LC4M4E1-60TC, AS4LC4M4E1-60JI, AS4LC4M4E1-60JC, AS4LC4M4E1-50TI Datasheet (Alliance Semiconductor Corporation)
...Page 1
March 2001
Copyright © Alliance Semiconductor. All rights reserved.
®
AS4LC4M4E0
AS4LC4M4E1
4Mx4 CMOS DRAM (EDO) Family
4/11/01; V.1.1 Alliance Semiconductor P. 1 of 15
Features
• Organization: 4,194,304 words × 4 bits
• High speed
- 50/60 ns RAS
access time
- 25/30 ns column address access time
- 12/15 ns CAS
access time
• Low power consumption
- Active: 500 mW max
- Standby: 3.6 mW max, CMOS I/O
• Extended data out
•Refresh
- 4096 refresh cycles, 64 ms refresh interval for AS4LC4M4E0
- 2048 refresh cycles, 32 ms refresh interval for AS4LC4M4E1
-RAS
-only or CAS-before-RAS refresh or self-refresh
• TTL-compatible, three-state I/O
• JEDEC standard package
- 300 mil, 24/26-pin SOJ
• 3V power supply
• Industrial and commercial temperature available
Pin arrangement
A8
A7
A6
A5
A4
A10
A0
A1
A2
A3
V
CC
GND
GND
I/O3
I/O2
CAS
OE
V
CC
I/O0
I/O1
WE
RAS
1
2
3
4
5
24
23
22
21
20
*NC/A11 A9
619
7
8
9
10
11
18
17
16
15
14
12 13
SOJ
AS4LC4M4E0
A8
A7
A6
A5
A4
A10
A0
A1
A2
A3
V
CC
GND
GND
I/O3
I/O2
CAS
OE
V
CC
I/O0
I/O1
WE
RAS
1
2
3
4
5
24
23
22
21
20
*NC/A11 A9
619
7
8
9
10
11
18
17
16
15
14
12 13
TSOP
AS4LC4M4E0
* NC on 2K refresh version; A11 on 4K refresh version
Pin(s) Description
A0 to A11 Address inputs
RAS
Row address strobe
CAS
Column address strobe
WE
Write enable
I/O0 to I/O3 Input/output
OE
Output enable
V
CC
Power
GND Ground
Selection guide
Symbol AS4LC4M4E0/E1-50 AS4LC4M4E0/E1-60 Unit
Maximum
RAS
access time t
RAC
50 60 ns
Maximum column address access time t
CAA
25 30 ns
Maximum
CAS
access time t
CAC
12 15 ns
Maximum output enable (
OE
) access time t
OEA
13 15 ns
Minimum read or write cycle time t
RC
80 100 ns
Minimum fast page mode cycle time t
PC
25 30 ns
Maximum operating current I
CC1
120 110 mA
Maximum CMOS standby current I
CC5
1.0 1.0 mA
Pin designation
Page 2
AS4LC4M4E0
AS4LC4M4E1
®
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Functional description
The AS4LC4M4E0 and AS4LC4M4E1 are high performance 16-megabit CMOS Dynamic Random Access Memories (DRAM) organized as
4,194,304 words × 4 bits. The devices are fabricated using advanced CMOS technology and innovative design techniques resulting in high
speed, extremely low power and wide operating margins at component and system levels. The Alliance 16Mb DRAM family is optimized for
use as main memory in PC, workstation, router and switch applications.
These products feature a high speed page mode operation where read and write operations within a single row (or page) can be executed at
very high speed by toggling column addresses within that row. Row and column addresses are alternately latched into input buffers using the
falling edge of
RAS
and
CAS
inputs respectively. Also,
RAS
is used to make the column address latch transparent, enabling application of
column addresses prior to
CAS
assertion.
Extended data out (EDO) read mode enables 60MHz operation using 60ns devices. In contrast to 'fast page mode' devices, data remains active
on outputs after
CAS
is de-asserted high, giving system logic more time to latch the data. Use OE and WE to control output impedance and
prevent bus contention during read-modify-write and shared bus applications. Outputs also go to high impedance at the last occurrance of
RAS
and
CAS
going high.
Refresh on the 4096 address combinations of A0 to A11 must be performed every 64 ms using:
•
RAS
-only refresh:
RAS
is asserted while
CAS
is held high. Each of the 4096 rows must be strobed. Outputs remain high impedence.
• Hidden refresh:
CAS
is held low while
RAS
is toggled. Refresh address is generated internally. Outputs remain low impedence with
previous valid data.
•
CAS
-before-
RAS
refresh (CBR):
CAS
is asserted prior to
RAS
. Refresh address is generated internally.
Outputs are high-impedence (
OE
and WE are don't care).
• Normal read or write cycles refresh the row being accessed.
• Self-refresh cycles
Refresh on the 2048 address combinations of A0 to A10 must be performed every 32 ms using:
•
RAS
-only refresh:
RAS
is asserted while
CAS
is held high. Each of the 2048 rows must be strobed. Outputs remain high impedence.
• Hidden refresh:
CAS
is held low while
RAS
is toggled. Refresh address is generated internally. Outputs remain low impedence with
previous valid data.
•
CAS
-before-
RAS
refresh (CBR):
CAS
is asserted prior to
RAS
. Refresh address is generated internally.
Outputs are high-impedence (
OE
and WE are don't care).
• Normal read or write cycles refresh the row being accessed.
• Self-refresh cycles
The AS4LC4M4E0 and AS4LC4M4E1 are available in the standard 24/26-pin plastic SOJ and 24/26-pin plastic TSOP packages. The
AS4LC4M4E0 and AS4LC4M4E1 operate with a single power supply of 3V ± 0.3V. All provide TTL compatible inputs and outputs.
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AS4LC4M4E1
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Logic block diagram for 4K refresh
Logic block diagram for 2K refresh
Recommended operating conditions
†
VIL min -3.0V for pulse widths less than 5 ns. Recommended operating conditions apply throughout this document unlesss otherwise specified.
Absolute maximum ratings
Parameter Symbol Min Nominal Max Unit
Supply voltage
V
CC
3.0 3.3 3.6 V
GND 0.0 0.0 0.0 V
Input voltage
V
IH
2.0 – VCC+0.5V V
V
IL
–0.5
†
–0.8V
Ambient operating temperature
Commercial
T
A
0–70
°C
Industrial -40 – 85
Parameter Symbol Min Max Unit
Input voltage V
in
-1.0 4.6 V
Input voltage (DQs) V
DQ
-1.0 4.6 V
Power supply voltage V
CC
-1.0 4.6 V
Storage temperature (plastic) T
STG
-55 +150 °C
Soldering temperature × time T
SOLDER
– 260 × 10
o
C × sec
RAS
clock
generator
Refresh
controller
4096 × 1024 × 4
Array
(16,777,216)
Sense amp
A0
A1
A2
A3
A4
A5
A6
A7
V
CC
GND
Address buffers
A8
Row decoder
Column decoder
Data
I/O
buffers
OE
RAS
CAS
WE
clock
generator
WE
I/O0 to I/O3
CAS
clock
generator
A9
A10
A11
RAS
clock
generator
Refresh
controller
2048 × 2048 × 4
Array
(16,777,216)
Sense amp
A0
A1
A2
A3
A4
A5
A6
A7
V
CC
GND
Address buffers
A8
Row decoder
Column decoder
Substrate bias
generator
Data
I/O
buffers
OE
RAS
CAS
WE
clock
generator
WE
I/O0 to I/O3
CAS
clock
generator
A9
A10
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AS4LC4M4E1
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DC electrical characteristics
Power dissipation P
D
–0.5W
Short circuit output current I
out
–50mA
Parameter Symbol Test conditions
-50 -60
Unit NotesMin Max Min Max
Input leakage current I
IL
0V ≤ Vin ≤ +V
CC
(max)
Pins not under test = 0V
-5 +5 -5 +5 µA
Output leakage current I
OL
D
OUT
disabled, 0V ≤ V
out
≤ +V
CC
(max) -5 +5 -5 +5 µA
Operating power
supply current
I
CC1
CAS
, Address cycling; t
RC
= min – 120 – 110 mA 1,2
TTL standby power
supply current
I
CC2
RAS
=
CAS
≥ V
IH
– 2.0 – 2.0 mA
Ave r ag e p ower supp ly
current,
RAS
refresh
mode or CBR
I
CC3
RAS
cycling,
CAS
≥ V
IH
,
t
RC
= min of
RAS
low after
CAS
low.
–120 – 110mA 1
EDO page mode average
power supply current
I
CC4
RAS
= VIL,
CAS,
address cycling: t
HPC
= min
–90 – 80mA1, 2
CMOS standby power
supply current
I
CC5
RAS
=
CAS
= VCC - 0.2V – 1.0 – 1.0 mA
Output voltage
V
OH
I
OUT
= -2.0 mA 2.4 – 2.4 – V
V
OL
I
OUT
= 2.0 mA – 0.4 – 0.4 V
CAS
before
RAS
refresh
current
I
CC6
RAS, CAS
cycling, tRC = min – 120 – 110 mA
Self refresh current I
CC7
RAS
=
CAS
≤ 0.2V,
WE
= OE ≥ V
CC
- 0.2V,
all other inputs at 0.2V or
V
CC
- 0.2V
– 0.6 – 0.6
mA
Parameter Symbol Min Max Unit
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AC parameters common to all waveforms
Read cycle
Symbol Parameter
-50 -60
Unit NotesMin Max Min Max
t
RC
Random read or write cycle time 80 – 100 – ns
t
RP
RAS
precharge time 30 – 40 – ns
t
RAS
RAS
pulse width 50 10K 60 10K ns
t
CAS
CAS
pulse width 8 10K 10 10K ns
t
RCD
RAS
to
CAS
delay time 15 35 15 43 ns 6
t
RAD
RAS
to column address delay time 12 25 12 30 ns 7
t
RSH
CAS
to
RAS
hold time 10 – 10 – ns
t
CSH
RAS
to
CAS
hold time 40 – 50 – ns
t
CRP
CAS
to
RAS
precharge time 5 – 5 – ns
t
ASR
Row address setup time 0 – 0 – ns
t
RAH
Row address hold time 8 – 10 – ns
t
T
Transition time (rise and fall) 1 50 1 50 ns 4,5
t
REF
Refresh period – 64 – 64 ms 3
t
CP
CAS precharge time 8 – 10 – ns
t
RAL
Column address to
RAS
lead time 25 – 30 – ns
t
ASC
Column address setup time 0 – 0 – ns
t
CAH
Column address hold time 8 10 – ns
Symbol Parameter
-50 -60
Unit NotesMin Max Min Max
t
RAC
Access time from
RAS
–50–60ns6
t
CAC
Access time from
CAS
– 12 – 15 ns 6,13
t
AA
Access time from address – 25 – 30 ns 7,13
t
RCS
Read command setup time 0 – 0 – ns
t
RCH
Read command hold time to
CAS
0–0–ns9
t
RRH
Read command hold time to
RAS
0–0–ns9
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AS4LC4M4E1
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Write cycle
Read-modify-write cycle
Refresh cycle
Symbol Parameter
-50 -60
Unit NotesMin Max Min Max
t
WCS
Write command setup time 0 – 0 – ns 11
t
WCH
Write command hold time 10 – 10 – ns 11
t
WP
Write command pulse width 10 – 10 – ns
t
RW L
Write command to
RAS
lead time 10 – 10 – ns
t
CWL
Write command to
CAS
lead time 8 – 10 – ns
t
DS
Data-in setup time 0 – 0 – ns 12
t
DH
Data-in hold time 8 – 10 – ns 12
Symbol Parameter
-50 -60
Unit NotesMin Max Min Max
t
RW C
Read-write cycle time 113 – 135 – ns
t
RW D
RAS
to WE delay time 67 – 77 – ns 11
t
CWD
CAS
to WE delay time 32 – 35 – ns 11
t
AW D
Column address to WE delay time 42 – 47 – ns 11
Symbol Parameter
-50 -60
Unit NotesMin Max Min Max
t
CSR
CAS
setup time (
CAS
-before-
RAS
)5–5–ns3
t
CHR
CAS
hold time (
CAS
-before-RAS)8–10–ns3
t
RPC
RAS precharge to
CAS
hold time 0 – 0 – ns
t
CPT
CAS
precharge time
(CBR counter test)
10 10 – ns
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Hyper page mode cycle
Output enable
Self-refresh cycle
Symbol Parameter
-50 -60
Unit NotesMinMaxMinMax
t
CPWD
CAS
precharge to WE delay time 45 – 52 – ns
t
CPA
Access time from
CAS
precharge – 28 – 35 ns 13
t
RASP
RAS
pulse width 50 100K 60 100K ns
t
DOH
Previous data hold time from
CAS
5–5–ns
t
REZ
Output buffer turn off delay from
RAS
013015ns
t
WEZ
Output buffer turn off delay from
WE
013015ns
t
OEZ
Output buffer turn off delay from
OE
013015ns
t
HPC
Hyper page mode cycle time 20 – 25 – ns
t
HPRWC
Hyper page mode RMW cycle 47 – 56 – ns
t
RHCP
RAS
hold time from
CAS
30 – 35 – ns
Symbol Parameter
-50 -60
Unit NotesMinMaxMinMax
t
CLZ
CAS
to output in Low Z 0 – 0 – ns 8
t
ROH
RAS
hold time referenced to
OE
8–10–ns
t
OEA
OE
access time – 13 – 15 ns
t
OED
OE
to data delay 13 – 15 – ns
t
OEZ
Output buffer turnoff delay from
OE
013015ns8
t
OEH
OE
command hold time 10 – 10 – ns
t
OLZ
OE
to output in Low Z 0 – 0 – ns
t
OFF
Output buffer turn-off time 0 13 0 15 ns 8,10
Std
Symbol Parameter
-50 -60
Unit NotesMin Max Min Max
t
RASS
RAS
pulse width
(CBR self refresh)
100 – 100 – µs
t
RPS
RAS
precharge time
(CBR self refresh)
90 – 105 – ns
t
CHS
CAS
hold time
(CBR self refresh)
8–10– ns
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Notes
1I
CC1
, I
CC3
, I
CC4
, and I
CC6
are dependent on frequency.
2I
CC1
and I
CC4
depend on output loading. Specified values are obtained with the output open.
3 An initial pause of 200 µs is required after power-up followed by any 8 RAS
cycles before proper device operation is achieved. In the case of an internal
refresh counter, a minimum of 8 CAS
-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after
extended periods of bias without clocks (greater than 8 ms).
4 AC Characteristics assume t
T
= 2 ns. All AC parameters are as described in AC test conditions below
5V
IH
(min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL.
6 Operation within the t
RCD
(max) limit insures that t
RAC
(max) can be met. t
RCD
(max) is specified as a reference point only. If t
RCD
is greater than the
specified t
RCD
(max) limit, then access time is controlled exclusively by t
CAC
.
7 Operation within the t
RAD
(max) limit insures that t
RAC
(max) can be met. t
RAD
(max) is specified as a reference point only. If t
RAD
is greater than the
specified t
RAD
(max) limit, then access time is controlled exclusively by tAA.
8 Assumes three state test load (5 pF and a 380
Ω
Thevenin equivalent).
9Either t
RCH
or t
RRH
must be satisfied for a read cycle.
10 t
OFF
(max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. t
OFF
is referenced from
rising edge of RAS
or CAS, whichever occurs last.
11 t
WCS
, t
WCH
, t
RWD
, t
CWD
and t
AWD
are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only.
If t
WS
≥ tWS (min) and tWH ≥ tWH (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the
cycle. If t
RW D
≥ t
RWD
(min), t
CWD
≥ t
CWD
(min) and t
AW D
≥ t
AW D
(min), the cycle is a read-write cycle and the data out will contain data read from the
selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate.
12 These parameters are referenced to CAS
leading edge in early write cycles and to WE leading edge in read-write cycles.
13 Access time is determined by the longest of t
CAA
or t
CAC
or t
CPA
14 t
ASC
≥ tCP to achieve tPC (min) and t
CPA
(max) values.
15 These parameters are sampled and not 100% tested.
AC test conditions
- Access times are measured with output reference levels of VOH =
2.4V and V
OL
= 0.4V,
V
IH
= 2.0V and VIL = 0.8V
- Input rise and fall times: 2 ns
*including scope
and jig capacitance
50 pF*
R2 = 295
Ω
R1 = 828
Ω
D
out
GND
+3.3V
Figure B: Equivalent output load
(AS4LC4M4E0)
(AS4LC4M4E1)
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Read waveform
Early write waveform
t
RAS
t
RC
t
RP
t
RSH
t
RAD
t
RCH
t
ROH
t
CAC
t
OEA
t
OFF
(see note 11)
t
OEZ
RAS
CAS
Address
WE
OE
DQ
Column address
t
CRP
t
CSH
t
RCD
t
ASC
t
CAH
t
CAS
t
RAL
t
RAH
t
RCS
t
AA
t
CLZ
t
RRH
Data out
t
RAC
t
ASR
Row address
t
ROH
t
WEZ
t
OLZ
t
REZ
t
RAS
t
RC
t
RP
t
CRP
t
RSH
t
RCD
t
CSH
t
CAS
t
RAD
t
ASC
t
CAH
t
WCS
t
CWL
t
RW L
t
WCH
t
WP
t
DS
t
DH
Data in
RAS
CAS
Address
WE
OE
DQ
Row address
t
RAL
Column address
t
RAH
t
ASR
Undefined output/don’t careFalling inputRising input
Key to switching waveform
Page 10
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Write waveform
OE
controlled
Read-modify-write waveform
Row address
t
RAS
t
RC
t
RP
t
CRP
t
RSH
t
RCD
t
CSH
t
CAS
t
RAH
t
RAL
t
RAD
t
CAH
t
CWL
t
RWL
t
OEH
t
DS
t
DH
Data in
RAS
CAS
Address
WE
OE
DQ
Column address
t
WP
t
ASC
t
ASR
t
OED
t
RAS
t
RW C
t
RP
t
CRP
t
RSH
t
RCD
t
CSH
t
CAS
t
RAD
t
RAL
t
AR
t
CAH
t
CWL
t
CWD
t
RW L
t
AW D
t
WP
t
OEA
t
CLZ
t
CAC
t
AA
t
DS
t
DH
Row address Column address
Data inData out
RAS
CAS
Address
WE
OE
DQ
t
RAH
t
RWD
t
RCS
t
RAC
t
OEZ
t
OED
t
ASC
t
ASR
t
OLZ
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EDO page mode read waveform
EDO page mode early write waveform
Row
t
RASP
t
RP
t
CRP
t
RCD
t
CAS
t
CSH
t
RSH
t
HPC
t
ASR
t
RAD
t
RRH
t
OEA
t
OEA
t
AA
t
RAC
t
CAC
t
OEZ
Data out
Data out
Data out
Col address
Col address
RAS
CAS
Address
WE
OE
DQ
t
AR
t
RAH
t
ASC
t
CAH
t
RAL
t
RCS
t
CLZ
t
CP
t
OFF
t
OEZ
Col address
t
RCH
t
CPA
t
RHCP
t
CLZ
t
CLZ
t
OLZ
t
CPA
t
RAH
t
RASP
t
RW L
t
ASC
t
WCS
t
CP
t
RAL
t
WCH
t
CWL
t
WP
t
DS
t
DH
t
OED
t
CAS
Col address
Col address Col address
Data in Data In Data in
RAS
CAS
Address
WE
OE
DQ
t
PC
t
CAH
t
CSH
t
RCD
t
OEH
t
HDR
t
AR
t
RAD
t
ASR
t
CRP
t
RSH
Row address
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EDO page mode read-modify-write waveform
CAS
before
RAS
refresh waveform
WE
= VIH
RAS
only refresh waveform
WE
= OE = VIH or V
IL
t
RASP
t
RP
t
RCD
t
CSH
t
CAS
t
CP
t
CRP
t
ASR
t
CAH
t
CAH
t
RAL
t
CAH
t
CWD
t
AWD
t
CWD
t
CWL
t
CWD
t
AWD
t
RW L
t
WP
t
OEZ
t
OEA
t
RAC
t
DS
t
CLZ
t
CAC
t
CPA
Row ad Col ad Col addressCol ad
Data out
Data inData in
Data outData out
Data in
RAS
CAS
Address
WE
OE
DQ
t
RAD
t
RAH
t
RWD
t
RCS
t
CWL
t
OEA
t
AA
t
DH
t
DS
t
CLZ
t
CAC
t
CLZ
t
CAC
t
OED
t
HPRWC
t
CPWD
t
ASC
t
ASC
t
ASC
t
RP
t
RC
t
RAS
t
RPC
t
CP
t
CSR
t
CHR
RAS
CAS
DQ
OPEN
t
RAS
t
RP
t
RC
t
CRP
t
RPC
t
ASR
t
RAH
Row address
RAS
Address
CAS
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Hidden refresh waveform (read)
Hidden refresh waveform (write)
t
RAS
t
RC
t
RP
t
RAS
t
RC
t
RP
t
CRP
t
RCD
t
RSH
t
CRP
t
CHR
t
ASR
t
RAD
t
ASC
t
RRH
t
OEA
t
CLZ
t
CAC
t
OEZ
Col addressRow
Data out
RAS
CAS
Address
WE
OE
DQ
t
AR
t
RAH
t
RAC
t
AA
t
RCS
t
CAH
t
OFF
t
RAS
t
RC
t
RP
t
CRP
t
RCD
t
RSH
t
ASR
t
RAH
t
RAD
t
AR
t
CAH
t
WCS
t
WCH
t
DS
t
DH
Data in
Col addressRow address
RAS
CAS
Address
WE
DQ
OE
t
ASC
t
RWL
t
WCR
t
WP
t
DHR
t
RAL
t
CHR
Page 14
AS4LC4M4E0
AS4LC4M4E1
®
4/11/01; V.1.1 Alliance Semiconductor P. 14 of 15
CAS
before
RAS
refresh counter test waveform
t
RAS
t
RSH
t
RP
t
CSR
t
CHR
t
CPT
t
CAS
t
CAH
t
CLZ
t
CAC
t
RCH
t
RRH
t
ROH
t
OEA
t
RWL
t
CWL
t
WCS
t
WP
t
WCH
t
DS
t
DH
t
RCS
t
OEA
t
DS
t
DH
Col address
Data out
Data in
Data out Data in
RAS
CAS
Address
DQ
WE
OE
WE
DQ
OE
WE
OE
DQ
t
OED
t
AA
t
CLZ
t
CAC
t
OEZ
t
WP
t
CWL
t
RCS
t
AA
t
OEZ
t
AWD
t
CWD
t
RAL
Read cycleWrite cycleRead-Write cycle
t
ASC
t
OFF
t
RWL
Page 15
®
ASAS4LC4M4E0
ASAS4LC4M4E1
© Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or reg ister ed tr ademarks of A lliance . A ll oth er b ran d and
product names may be the trademarks of their respective companies. Alliance reserves the right to make chan ges t o this d ocu m e nt an d its p r odu cts at a ny time without notic e. A llian ce assum es no
responsibility for any errors that may app ear in th is doc um e nt. T h e d ata c ontain ed h ere in re pr esent s Allian ce ’s best data a nd /or e stim ate s at the ti me of issuan ce. Al lianc e reser ves the righ t to
change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specification s are possible . T h e in form a tion in th is
product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or
customer. A llian ce d oe s no t assum e any respo n sibility or liability arisi ng o ut o f th e ap plic ation or use o f any product described herein, and disclaims any express or implied warranties related to
the sale and/or use o f A llianc e pr o duc ts inclu din g liab ility o r w arra ntie s related to fitn ess fo r a p articu lar p urp ose, m erc han tabi lity , or infrin ge me n t of a ny int ellectua l pr op erty righ ts, ex cep t as
express agreed to in A llian ce’s T erm s an d C on ditio n s of Sale (which are av ailable from Alliance). Al l sales of Alliance produ cts are m ade ex clusive ly acc ord ing to A llian ce’s T erm s and
Conditions of Sale. The purchase of products from Alliance does n ot convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights
of Alliance o r third pa rties. A llian ce doe s no t au thoriz e its pr oducts for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result
in significant inju ry to the u ser, a nd the in clu sion o f A llia nce pro d ucts in such lif e- supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance
against all claims arising from such use.
4/11/01; V.1.1 Alliance Semiconductor P. 15 of 15
CAS
-before-
RAS
self refresh cycle
Capacitance
15
ƒ = 1 MHz, Ta = Room temperature
AS4LC4M4E0 ordering information
AS4LC4M4E1 ordering information
AS4LC4M4E0 family part numbering system
Parameter Symbol Signals Test conditions Max Unit
Input capacitance
C
IN1
A0 to A11 Vin = 0V 5 pF
C
IN2
RAS, UCAS, LCAS, WE, OE
Vin = 0V 7 pF
DQ capacitance C
DQ
DQ0 to DQ3 Vin = V
out
= 0V 7 pF
Package \
RAS
access time 50 ns 60 ns
Plastic SOJ, 300 mil, 24/26-pin
AS4LC4M4E0-50JC
AS4LC4M4E0-50JI
AS4LC4M4E0-60JC
AS4LC4M4E0-60JI
Plastic TSOP, 300 mil, 24/26-pin
AS4LC4M4E0-50TC
AS4LC4M4E0-50TI
AS4LC4M4E0-60TC
AS4LC4M4E0-60TI
Package \
RAS
access time 50 ns 60 ns
Plastic SOJ, 300 mil, 24/26-pin
AS4LC4M4E1-50JC
AS4LC4M4E1-50JI
AS4LC4M4E1-60JC
AS4LC4M4E1-60JI
Plastic TSOP, 300 mil, 24/26-pin
AS4LC4M4E1-50TC
AS4LC4M4E1-50TI
AS4LC4M4E1-60TC
AS4LC4M4E1-60TI
AS4 C 4M4
E0
–XX X X
DRAM
prefix
C = 5V CMOS
LC = 3V CMOS
4M×4
E0=4K refresh
E1=2K refresh
RAS
access
time
Package:
J = SOJ 300 mil, 24/26
T = TSOP 300 mil, 24/26
Temperature range
C=Commercial, 0°C to 70°C
I=Industrial, -40°C to 85°C
t
RP
t
RASS
t
RPC
t
CP
t
CHS
t
CEZ
RAS
CAS
DQ
CAS
t
RPS
t
CSR
t
RPC
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