Datasheet AS4LC4M4883C Datasheet (AUSTN)

AUSTIN SEMICONDUCTOR, INC.

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AS4LC4M4 883C

4 MEG x 4 DRAM

DRAM

4 MEG x 4 DRAM

3.3V, EDO PAGE MODE

AVAILABLE IN MILITARY
SPECIFICATIONS

• MIL-STD-883

• SMD Planned

FEATURES

• Industry-standard x4 pinout, timing, functions and
packages

• High-performance CMOS silicon-gate process

• Single +3.3V ±0.3V power supply

• Low power, 1mW standby; 150mW active, typical

• All inputs, outputs and clocks are TTL-compatible

• Refresh modes: ?R?A/S ONLY, ?C?A/S-BEFORE-?R?A/S (CBR)
HIDDEN

• 2,048-cycle (11 row-, 11 column-addresses)

• Extended Data-Out (EDO) PAGE access cycle

• 5V-tolerant I/Os (5.5V maximum V

IH level)

OPTIONS MARKING

• Timing
60ns access (Contact Factory) -6
70ns acess -7
80ns access -8

• Packages
Ceramic SOJ ECJ No. 505
Ceramic LCC EC No. 212
Ceramic Gull Wing ECG No. 603

KEY TIMING PARAMETERS

SPEEDtRCtRACtPC

-6 110ns 60ns 30ns 30ns 15ns 12ns

-7 130ns 70ns 35ns 35ns 18ns 15ns

-8 150ns 80ns 40ns 40ns 20ns 20ns

t

AAtCACtCAS

GENERAL DESCRIPTION

The AS4LC4M4 is a randomly accessed solid-state
memory containing 16,777,216 bits organized in a x4 con­figuration. The AS4LC4M4 ?R?A/S is used to latch the first 11
bits and ?C?A/S the latter 11 bits. READ and WRITE cycles are
selected with the ?W/E input. A logic HIGH on
?W/E dictates READ mode while a logic LOW on ?W/E dictates
WRITE mode. During a WRITE cycle, data-in (D) is latched
by the falling edge of ?W/ E or ?C?A/S, whichever occurs last. If
?W/E goes LOW prior to ?C?A/S going LOW, the output pins
remain open (High- Z) until the next ?C?A/S cycle, regardless
of ?O/E.

AS4LC4M4 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
Rev. 11/97
DS000022

LOW on ?W/E dictates WRITE mode. During a WRITE cycle,
data-in (D) is latched by the falling edge of ?W/E or /C/A/S,
whichever occurs last. An EARLY WRITE occurs when
?W/E is taken LOW prior to /C/A/S falling. A LATE WRITE or
READ-MODIFY-WRITE occurs when ?W/E falls after /C/A/S
was taken LOW. During EARLY WRITE cycles, the data­outputs (Q) will remain High-Z regardless of the state of

?O/E. During LATE WRITE or READ-MODIFY-WRITE cycles,
?O/E must be taken HIGH to disable the data-outputs prior to

applying input data. If a LATE WRITE or READ-MODIFY­WRITE is attempted while keeping ?O/E LOW, no write will
occur, and the data-outputs will drive read data from the
accessed location.

through four pins using common I/O, and pin direction is
controlled by ?W/E and ?O/E.

FAST PAGE MODE

(READ, WRITE or READ-MODIFY-WRITE) within a row­address-defined page boundary. The FAST PAGE cycle is
always initiated with a row-address strobed-in by ?R?A/S
followed by a column-address strobed-in by ?C?A/S. ?C?A/S may
be toggled-in by holding ?R?A/S LOW and strobing-in differ­ent column-addresses, thus executing faster memory cycles.
Returning R?A/S HIGH terminates the FAST PAGE MODE
of operation.

2-73

PIN ASSIGNMENT (Top View)

24/28-Pin

28

1

VCC

2

DQ1

3

DQ2

4

/W/E

5

/R/A/S

6

NC

9

A10

10

A0

11

A1

12

A2

13

A3

14

V

CC

A logic HIGH on ?W/E dictates READ mode while a logic

The four data inputs and the four data outputs are routed

FAST PAGE operations allow faster data operations

VSS

27

DQ4

26

DQ3

25

/C/A/S

24

/O/E

23

A9

20

A8

19

A7

18

A6

17

A5

16

A4

15

Vss

AUSTIN SEMICONDUCTOR, INC.

,

,,

,,

,,,

,,

EDO PAGE MODE

The AS4LC4M4E8 provides EDO PAGE MODE which is
an accelerated FAST PAGE MODE cycle. The primary
advantage of EDO is the availability of data-out even after
?C?A/S returns HIGH. EDO allows ?C?A/S precharge time (
to occur without the output data going invalid. This elimi­nation of ?C?A/S output control allows pipeline READs.

FAST-PAGE-MODE DRAMs have traditionally turned
the output buffers off (High-Z) with the rising edge of
?C?A/S. EDO-PAGE-MODE DRAMs operate similarly to
FAST-PAGE-MODE DRAMs, except data will remain valid
or become valid after ?C?A/S goes HIGH during READs,
provided ?R?A/S and ?O/E are held LOW. If ?O/E is pulsed while

V

IH

RAS

V

IL

V

CAS

IH

V

IL

V

IH

ADDR

V

ROW

IL

COLUMN (A)

t

CP)

COLUMN (B)

AS4LC4M4 883C

4 MEG x 4 DRAM

?R?A/S and ?C?A/S are LOW, data will toggle from valid data to
High-Z and back to the same valid data. If ?O/E is toggled or
pulsed after ?C?A/S goes HIGH while ?R?A/S remains LOW,
data will transition to and remain High-Z (refer to Figure 1).
?W/E can also perform the function of disabling the output
devices under certain conditions, as shown in Figure 2.

During an application, if the DQ outputs are wire OR’d,
?O/E must be used to disable idle banks of DRAMs. Alterna­tively, pulsing ?W/E to the idle banks during ?C?A/S high time
will also High-Z the outputs. Independent of ?O/E control,
the outputs will disable after
from the rising edge of ?R?A/S or ?C?A/S, whichever occurs last.

COLUMN (C)

t

OFF, which is referenced

COLUMN (D)

DQ

OE

AS4LC4M4 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
Rev. 11/97
DS000022

V

IOH

V

IOL

V

IH

V

IL

OPEN

VALID DATA (A)

t

OD

t

OES

The DQs go back to
Low-Z if

t

OE

t

OES is met.

VALID DATA (A)

VALID DATA (B)

t

OD

t

OEHC

The DQs remain High-Z
until the next CAS cycle

t

OEHC is met.

if

VALID DATA (C)

t

OEP

The DQs remain High-Z
until the next CAS cycle

t

OEP is met.

if

t

OD

VALID DATA (D)

Figure 1

OUTPUT ENABLE AND DISABLE

2-74

AUSTIN SEMICONDUCTOR, INC.

,

,

,

,,,

AS4LC4M4 883C

4 MEG x 4 DRAM

REFRESH

Preserve correct memory cell data by maintaining power and executing a ?R?A/S cycle (READ, WRITE) or ?R?A/S refresh cycle
(?R?A/S ONLY, CBR, or HIDDEN) so that all 2,048 combinations of ?R?A/S addresses are executed at least every 32ms, regardless
of sequence. The CBR REFRESH cycle will invoke the refresh counter for automatic ?R?A/S addressing.

V

IH

RAS

V

IL

V

IH

CAS

V

IL

V

ADDR

IH

V

IL

V

IOH

DQ

V

IOL

V

IH

WE

V

IL

V

IH

OE

V

IL

ROW

OPEN

COLUMN (A)

COLUMN (B)

VALID DATA (A)

t

WHZ

t

WPZ

The DQs go to High-Z if WE falls, and if tWPZ is met,
will remain High-Z until CAS goes LOW with
WE HIGH (i.e., until a READ cycle is initiated).

VALID DATA (B)

COLUMN (C)

INPUT DATA (C)

t

WHZ

WE may be used to disable the DQs to prepare
for input data in an EARLY WRITE cycle. The DQs
will remain High-Z until CAS goes LOW with
WE HIGH (i.e., until a READ cycle is initiated).

COLUMN (D)

DON’T CARE

UNDEFINED

Figure 2

??

//

?W

/E CONTROL OF DQs

??

//

AS4LC4M4 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
Rev. 11/97
DS000022

2-75

AUSTIN SEMICONDUCTOR, INC.

FUNCTIONAL BLOCK DIAGRAM

AS4LC4M4 883C

4 MEG x 4 DRAM

WE

CAS

A10

RAS

DATA-IN
BUFFER

NO. 2 CLOCK
GENERATOR

COLUMN­ADDRESS

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9

11

11

BUFFER(11)

REFRESH

CONTROLLER

REFRESH
COUNTER

11

ROW-

ADDRESS

BUFFERS (11)

NO. 1 CLOCK
GENERATOR

11

10

ROW

DECODER

1

2048

2048

2048

2048

2048

SELECT

COMPLEMENT

DATA-OUT

BUFFER

COLUMN

DECODER

1024

SENSE AMPLIFIERS

I/O GATING

1024

4096 x 1024 x 4

MEMORY

(2 of 4096)

ROW SELECT

ARRAY

4

4

4

4

(1 OF 2)

(1 OF 2)
ROW TRANSFER

ROW TRANSFER

DD

V
Vss

DQ1
DQ2
DQ3
DQ4

OE

TRUTH TABLE

ADDRESSES DATA-IN/OUT

FUNCTION ?R?A/S ?C?A/S ?W/E ?O/E

t

R

Standby H H>XXXXX High-Z
READ L L H L ROW COL Data-Out
EARLY WRITE L L L X ROW COL Data-In
READ WRITE L L H>LL>H ROW COL Data-Out, Data-In
EDO-PAGE-MODE 1st Cycle L H>L H L ROW COL Data-Out
READ 2nd Cycle L H>L H L n/a COL Data-Out
EDO-PAGE-MODE 1st Cycle L H>L L X ROW COL Data-In
EARLY-WRITE 2nd Cycle L H>L L X n/a COL Data-In

Any Cycle L L>H H L n/a n/a Data-Out
EDO-PAGE-MODE 1st Cycle L H>LH>LL>H ROW COL Data-Out, Data-In
READ-WRITE 2nd Cycle L H>LH>LL>H n/a COL Data-Out, Data-In
HIDDEN READ L>H>L L H L ROW COL Data-Out
REFRESH WRITE L>H>L L L X ROW COL Data-In
?R?A/S-ONLY REFRESH L H X X ROW n/a High-Z
CBR REFRESH H>L L H X X X High-Z

t

C DQ1-DQ4

AS4LC4M4 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
Rev. 11/97
DS000022

2-76

AUSTIN SEMICONDUCTOR, INC.

AS4LC4M4 883C

4 MEG x 4 DRAM

ABSOLUTE MAXIMUM RATINGS*

Voltage on VCC pin Relative to VSS .................-1V to +4.6V

Voltage on NC, Inputs or I/O pins
Relative to V
Operating Temperature, T

...................................................................TC (MAX) = 125°C

Storage Temperature................................... -55°C to +150°C

SS .................................................... -1V to +5.5V

(ambient) .. TA(MIN) = -55°C

A

*Stresses greater than those listed under “Absolute Maxi­mum Ratings” may cause permanent damage to the de­vice. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating condi­tions for extended periods may affect reliability.

Power Dissipation ............................................................. 1W

Short Circuit Output Current ..................................... 50mA

ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS

(Notes: 1, 6, 7) (VCC = +3.3V ±0.3V)

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

Supply Voltage VCC 3.0 3.6 V
Input High (Logic 1) Voltage, all inputs (including NC pins) VIH 2.0 VCC+1 V
Input Low (Logic 0) Voltage, all inputs (including NC pins) VIL -1.0 0.8 V
INPUT LEAKAGE CURRENT

Any input 0V ≤ V
(All other pins not under test = 0V) (NC pins not tested)

OUTPUT LEAKAGE CURRENT (Q is disabled; 0V ≤ VOUT ≤ 5.5V) Vcc=3.6V IOZ -10 10 µA
OUTPUT LEVELS V

Output High Voltage (I
Output Low Voltage (I

PARAMETER/CONDITION SYM -6 -7 -8 UNITS NOTES

STANDBY CURRENT: (TTL) I
(?R?A/S = ?C?A/S = VIH)

STANDBY CURRENT: (CMOS) I
(?R?A/S = ?C?A/S = other inputs = V

OPERATING CURRENT: Random READ/WRITE
Average power supply current I
(?R?A/S, ?C?A/S, address cycling: tRC = tRC [MIN])

OPERATING CURRENT: EDO PAGE MODE
Average power supply current ICC4 110 100 9 0 mA 3, 4, 12
(?R?A/S = VIL, ?C?A/S, address cycling: tPC = tPC [MIN])

REFRESH CURRENT: ?R?A/S ONLY
Average power supply current ICC5 120 110 100 mA 3, 12
(?R?A/S cycling, ?C?A/S = VIH: tRC = tRC [MIN])

REFRESH CURRENT: CBR
Average power supply current I
(?R?A/S, ?C?A/S, address cycling: tRC = tRC [MIN])

IN ≤ 5.5V Vcc = 3.6V II -2 2 µA

OH 2.4 V

OUT = -2mA)

OUT = 2mA) VOL 0.4 V

MAX

CC1 222mA

CC2 111mA

CC -0.2V

CC3 120 110 100 mA 3, 4, 12

CC6 120 110 100 mA 3, 5

AS4LC4M4 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
Rev. 11/97
DS000022

2-77

AUSTIN SEMICONDUCTOR, INC.

AS4LC4M4 883C

4 MEG x 4 DRAM

CAPACITANCE

PARAMETER SYMBOL MAX UNITS NOTES

Input Capacitance: Address pins CI1 7pF2
Input Capacitance: ?R?A/S, ?C?A/S, ?W/E, ?O/ECI27pF2
Input/Output Capacitance: DQ C

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (VCC = +3.3V ±0.3V)

AC CHARACTERISTICS -6 -7 -8
PARAMETER SYM MIN MAX MIN MAX MIN MAX UNITS NOTES

Access time from column-address
Column-address set-up to ?C?A/S precharge during writetACH 15 15 20 ns
Column-address hold time (referenced to ?R?A/S)
Column-address setup time
Row-address setup time
Column-address to ?W/E delay time
Access time from ?C?A/S
Column-address hold time

?C?A/S pulse width
?C?A/S hold time (CBR REFRESH)
?C?A/S to output in Low-Z
Data output hold after next ?C?A/S LOW
?C?A/S precharge time
Access time from ?C?A/S precharge
?C?A/S to ?R?A/S precharge time
?C?A/S hold time
?C?A/S setup time (CBR REFRESH)
?C?A/S to ?W/E delay time

Write command to ?C?A/S lead time
Data-in hold time
Data-in hold time (referenced to ?R?A/S)
Data-in setup time
Output disable
Output Enable

?O/E hold time from ?W/E during READ-MODIFY-WRITE cycletOEH 10 12 15 ns
?O/E HIGH hold from ?C?A/S HIGH
?O/E HIGH pulse width
?O/E LOW to ?C?A/S HIGH setup time

t

AA 30 35 40 ns

t

AR 45 55 60 ns

t

ASC 0 0 0 ns

t

ASR 0 0 0 ns

t

AWD 55 65 65 ns 20

t

CAC 15 20 20 ns 14

t

CAH 10 15 15 ns

t

CAS 12 10,000 15 10,000 20 10,000 ns

t

CHR 10 15 15 ns 5

t

CLZ 0 0 0 ns

t

COH 5 5 5 ns

t

CP 10 10 10 ns 15

t

CPA 35 40 40 ns

t

CRP 5 5 5 ns

t

CSH 50 55 60 ns

t

CSR 5 5 10 ns 5

t

CWD 35 40 45 ns 20

t

CWL 15 15 20 ns

t

DH 10 12 15 ns 21

t

DHR 40 56 55 ns

t

DS 0 0 0 ns 21

t

OD 015015 20 ns

t

OE 15 20 20 ns 22

t

OEHC 10 10 10 ns

t

OEP 10 10 10 ns

t

OES 5 5 5 ns

IO 8pF2

AS4LC4M4 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
Rev. 11/97
DS000022

2-78

AUSTIN SEMICONDUCTOR, INC.

AS4LC4M4 883C

4 MEG x 4 DRAM

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (VCC = +3.3V ±0.3V)

AC CHARACTERISTICS -6 -7 -8
PARAMETER SYM MIN MAX MIN MAX MIN MAX UNITS NOTES

Output buffer turn-off delay
?O/E setup prior to ?R?A/S during HIDDEN REFRESH cycletORD 0 0 0 ns 19
EDO-PAGE-MODE READ or WRITE cycle time
EDO-PAGE-MODE READ-WRITE cycle time
Access time from ?R?A/S
?R?A/S to column-address delay time
Row-address hold time
Column-address to ?R?A/S lead time

?R?A/S pulse width
?R?A/S pulse width (EDO PAGE MODE)

Random READ or WRITE cycle time
?R?A/S to ?C?A/S delay time
Read command hold time (referenced to ?C?A/S)
Read command setup time
Refresh period (2,048 cycles)

?R?A/S precharge time
?R?A/S to ?C?A/S precharge time
Read command hold time (referenced to ?R?A/S)
?R?A/S hold time

READ WRITE cycle time
?R?A/S to ?W/E delay time
Write command to ?R?A/S lead time
Transition time (rise or fall)
Write command hold time
Write command hold time (referenced to ?R?A/S)
?W/E command setup time
Output disable delay from ?W/E
Write command pulse width

?W/E pulse to disable at ?C?A/S HIGH
?W/E hold time (CBR REFRESH)
?W/E setup time (CBR REFRESH)

t

OFF 0 15 0 15 0 20 ns

t

PC 30 35 40 ns

t

PRWC 75 85 90 ns

t

RAC 60 70 80 ns 13

t

RAD 15 30 15 35 15 40 ns 17

t

RAH 10 10 10 ns

t

RAL 30 35 40 ns

t

RAS 60 10,000 70 10,000 80 10,000 ns

t

RASP 60 100,000 70 100,000 80 100,00 ns

t

RC 110 130 150 ns

t

RCD 16 45 16 50 20 60 ns 16

t

RCH 0 0 0 ns 18

t

RCS 0 0 0 ns

t

REF 32 32 32 ms

t

RP 40 50 60 ns

t

RPC 5 5 5 ns

t

RRH 0 0 0 ns 18

t

RSH 13 15 15 ns

t

RWC 150 180 200 ns

t

RWD 80 90 105 ns 20

t

RWL 15 15 20 ns

t

T 2 30 2 30 2 30 ns

t

WCH 10 12 15 ns

t

WCR 40 56 60 ns

t

WCS 0 0 0 ns 20

t

WHZ 0 14 0 16 0 20 ns

t

WP 10 12 15 ns

t

WPZ 10 12 15 ns

t

WRH 10 10 10 ns 24

t

WRP 10 10 10 ns 24

AS4LC4M4 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
Rev. 11/97
DS000022

2-79

AUSTIN SEMICONDUCTOR, INC.

AS4LC4M4 883C

4 MEG x 4 DRAM

NOTES

1. All voltages referenced to VSS.

2. This parameter is sampled. V

CC is dependent on cycle rates.

3. I

CC is dependent on output loading and cycle rates.

4. I
Specified values are obtained with minimum cycle
time and the outputs open.

5. Enables on-chip refresh and address counters.

6. The minimum specifications are used only to indicate
cycle time at which proper operation over the ful
temperature range is assured.

7. An initail pause of 100µs is required after power-up
followed by eight /R/A/S refresh cycles (/R/A/S ONLY or
CBR with /W/E HIGH) before proper device operation
is assured. The eight /R/A/S cycle wake-ups should be
repeated any thime the
exceeded.

8. AC characteristics assume

IH (MIN) and VIL (MAX) are reference levels for

9. V
measuring timing of input signals. Transition times
are measured between V
and VIH).

10. In addition to meeting the transition rate specifica­tion, all input signals must transit between V

IL (or between VIL and VIH) in a monotonic manner.

V

11. Column address changed once each cycle.

12. Measured with a load equivalent to two TTL gates,
100pF and V

13. Assumes that
than the maximum recommended value shown in this
table,
exceeds the value shown.

14. Assumes that

OL = 0.8V and VOH = 2.0V.

t

RCD < tRCD (MAX). If tRCD is greater

t

RAC will increase by the amount that tRCD

t

RCD≥ tRCD (MAX).

15. If ?C?A/S is LOW at the falling edge of ?R?A/S, Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the data-out buffer, ?C?A/S must be
pulsed HIGH for

16. Operation within the

t

RAC (MAX) can be met. tRCD (MAX) is specified as
a reference point only; if
specified

t

CP.

t

RCD (MAX) limit, then access time is
controlled exclusively by
exceeded.

17. Operation within the

t

RAC (MIN) and tCAC (MIN) can be met. tRAD
(MAX) is specified as a reference point only; if
is greater than the specified
access time is controlled exclusively by

t

RCD is not exceeded.

CC = +3.3V; f = 1 MHz.

t

REF refresh requirement is

t

T = 2.5ns.

IH and VIL (or between VIL

IH and

t

RCD (MAX) limit ensures that

t

RCD is greater than the

t

CAC, provided tRAD is not

t

RAD (MAX) limit ensures that

t

t

RAD (MAX) limit, then

RAD

t

AA, provided

t

18. Either

19.

RCH or tRRH must be satisfied for a READ

cycle.

t

OFF (MAX) defines the time at which the output
achieves the open circuit condition, and is not
referenced to V
rising edge of ?R?A/S or ?C?A/S, whichever occurs last.

20. t

WCS, tRWD, tAWD and tCWD are not restrictive
operating parameters.
WRITE cycles.
READ-MODIFY-WRITE cycles. If

OH or VOL. It is referenced from the

t

WCS applies to EARLY

t

RWD, tAWD and tCWD apply to

t

WCS ≥ tWCS

(MIN), the cycle is an EARLY WRITE cycle and the
data output will remain an open circuit throughout
the entire cycle. If

t

RWD (MIN), tAWD ≥ tAWD (MIN) and tCWD ≥

t

CWD (MIN), the cycle is a READ-MODIFY-WRITE

t

WCS < tWCS (MIN) and tRWD ≥

and the data output will contain data read from the
selected cell. If neither of the above conditions is met,
the state of data-out is indeterminate. ?O/E held HIGH
and ?W/E taken LOW after ?C?A/S goes LOW results in a
LATE WRITE (?O/E-controlled) cycle.

t

CWD and tAWD are not applicable in a LATE

t

WCS, tRWD,

WRITE cycle.

21. These parameters are referenced to ?C?A/S leading edge
in EARLY WRITE cycles and ?W/E leading edge in
LATE WRITE or READ-MODIFY-WRITE cycles.

22. If ?O/E is tied permanently LOW, LATE WRITE or
READ-MODIFY-WRITE operations are not permis­sible and should not be attempted. Additionally, ?W/E
must be pulsed during ?C?A/S HIGH time in order to
place I/O buffers in High-Z.

23. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, ?W/E = LOW and
?O/E = HIGH.

t

WTS and tWTH are setup and hold specifications for

24.
the /W/E pin being held LOW to enable the JEDEC test
mode (with CBR timing constraints). These two
parameters are the inverts of

t

WRP and tWRH in the

CBR REFRESH cycle.

AS4LC4M4 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
Rev. 11/97
DS000022

2-80

AUSTIN SEMICONDUCTOR, INC.

,

,,,

,,

,

,,

,,,,

,,,

,,

,,,,

,,

,

READ CYCLE

t

RC

t

RAS

V

IH

V

RAS

IL

t

RCD

t

AR

t

ASC

t

ACH

COLUMN

t

RCS

CAS

ADDRVV

WE

DQ

OEVV

t

CRP

V

IH

V

IL

t

RAD

ROW

t

WRPtWRH

NOTE 1

t

RAH

OPEN

t

ASR

IH
IL

V

IH

V

IL

V

OH

V

OL

IH
IL

t
t
t

t
t

t
t
t
t

CSH
RSH
CAS

RAL
CAH

AA
RAC
CAC
CLZ

AS4LC4M4 883C

4 MEG x 4 DRAM

t

RP

t

RRH

t

RCH

NOTE 2

t

OFF

VALID DATA

t

OE

t

OD

ROW

OPEN

DON’T CARE

UNDEFINED

NOTE: 1. Although ?W/E is a “don’t care” at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement

?W/E HIGH for

t

OFF is referenced from rising edge of ?R?A/S or ?C?A/S, whichever occurs last.

2.

TIMING PARAMETERS

-6 -7 -8

SYM MIN MAX MIN MAX MIN MAX UNITS

t

AA 30 35 40 ns

t

ACH 15 15 20 ns

t

AR 45 50 60 ns

t

ASC 0 0 0 ns

t

ASR 0 0 0 ns

t

CAC 15 20 20 ns

t

CAH 10 15 15 ns

t

CAS 12 10,000 15 10,000 20 10,000 ns

t

CLZ 0 0 0 ns

t

CRP 5 5 5 ns

t

CSH 50 55 60 ns

t

OD 0 15 0 15 20 ns

t

OE 15 20 20 ns

t

OFF015015020ns

AS4LC4M4 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
Rev. 11/97
DS000022

t

WRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.

-6 -7 -8

SYM MIN MAX MIN MAX MIN MAX UNITS

t

RAC 60 70 80 ns

t

RAD 15 30 15 35 15 40 ns

t

RAH 10 10 10 ns

t

RAL 30 35 40 ns

t

RAS 60 10,000 70 10,000 80 10,000 ns

t

RC 110 130 150 ns

t

RCD 16 45 16 50 20 60 ns

t

RCH 0 0 0 ns

t

RCS 0 0 0 ns

t

RP 40 50 60 ns

t

RRH 0 0 0 ns

t

RSH 10 12 15 ns

t

WRH 10 10 10 ns

t

WRP 10 10 10 ns

2-81

AUSTIN SEMICONDUCTOR, INC.

,,,

,,,

,,

,

,,

,,,

,,,

,,

,,,

,,,

,,,

,,,

,,,

,,,

,,

,,

,,,

,,

,,

EARLY WRITE CYCLE

V

IH

RAS

V

IL

CAS

ADDR

t

CRP

V

IH

V

IL

t

RAD

t

WRPtWRH

NOTE 1

t

RAH

t

ASR

V

IH

V

IL

WE

V

IH

V

IL

V

IOH

DQ

V

IOL

V

IH

OE

V

IL

t

WCS

t

t

RCD

t

t

DS

AR

ASC

COLUMNROW

VALID DATA

AS4LC4M4 883C

4 MEG x 4 DRAM

t

RC

t

RAS

t

CSH

t

RSH

t

CAS

t

RAL

t

CAH

t

ACH

t

CWL

t

RWL

t

WCR

t

WCH

t

WP

t

DHR

t

DH

t

RP

ROW

NOTE: 1. Although ?W/E is a “don’t care” at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement

TIMING PARAMETERS

SYM MIN MAX MIN MAX MIN MAX UNITS

t

ACH 15 15 20 ns

t

AR 45 55 60 ns

t

ASC 0 0 0 ns

t

ASR 0 0 0 ns

t

CAH 10 15 15 ns

t

CAS 12 10,000 15 10,000 20 10,000 ns

t

CRP 5 5 5 ns

t

CSH 50 55 60 ns

t

CWL 15 15 20 ns

t

DH 10 12 15 ns

t

DHR 40 50 55 ns

t

DS 0 0 0 ns

t

RAD 15 30 15 35 15 40 ns

t

RAH 10 10 10 ns

AS4LC4M4 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
Rev. 11/97
DS000022

t

?W/E HIGH for

WRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.

-6 -7 -8

2-82

DON’T CARE

UNDEFINED

-6 -7 -8

SYM MIN MAX MIN MAX M IN MAX UNITS

t

RAL 30 35 40 ns

t

RAS 60 10,000 70 10,000 80 10,000 ns

t

RC 110 130 150 ns

t

RCD 16 45 16 50 20 60 ns

t

RP 40 50 60 ns

t

RSH 13 15 0 ns

t

RWL 15 15 20 ns

t

WCH 10 12 15 ns

t

WCR 40 50 60 ns

t

WCS 0 0 0 ns

t

WP 10 12 15 ns

t

WRH 10 10 10 ns

t

WRP 10 10 10 ns

AUSTIN SEMICONDUCTOR, INC.

,,,

,

,,,

,,

,,,

,,,,

,

,,,

,,

,

READ WRITE CYCLE

(LATE WRITE and READ-MODIFY-WRITE cycles)

t

RWC

t

RAS

V

IH

RAS

V

ADDR

WE

IL

t

CRP

V

IH

CAS

V

IL

t

ASR

V

IH

V

IL

V

IH

V

IL

V

IOH

DQ

V

IOL

V

IH

OE

V

IL

ROW

t

WRPtWRH

NOTE 1

t

RCD

t

AR

t

RAD

t

RAH

t

ASC

t

RCS

t

CSH

t

RSH

t

CAS

t

RAL
t

CAH

COLUMN ROW

t

RWD

t

CWD
t

AWD

t

AA

t

RAC

t

CAC

t

CLZ

VALID D

t

OE

AS4LC4M4 883C

4 MEG x 4 DRAM

t

RP

t

ACH

t

CWL

t

RWL

t

WP

tDSt

DH

VALID D

OUT

t

OD

IN

t

OEH

OPENOPEN

DON’T CARE

UNDEFINED

NOTE: 1. Although ?W/E is a “don’t care” at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement

TIMING PARAMETERS

SYM MIN M AX MI N MAX MIN MA X UNITS

t

AA 30 35 40 ns

t

ACH 15 15 20 ns

t

AR 45 55 60 ns

t

ASC 0 0 0 ns

t

ASR 0 0 0 ns

t

AWD 55 65 65 ns

t

CAC 15 20 20 ns

t

CAH 10 15 15 ns

t

CAS 12 10,000 15 10,000 20 10,000 ns

t

CLZ 0 0 0 ns

t

CRP 5 5 5 ns

t

CSH 50 55 60 ns

t

CWD 35 40 45 ns

t

CWL 15 15 20 ns

t

DH 10 12 15 ns

t

DS 0 0 0 ns

t

OD015 015020 ns

AS4LC4M4 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
Rev. 11/97
DS000022

t

?W/E HIGH for

WRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.

-6 -7 -8
SYM MIN M AX MIN MAX MIN MAX UNITS

t

OE 15 20 20 ns

t

OEH 10 12 15 ns

t

RAC 60 70 80 ns

t

RAD 15 30 15 35 15 40 ns

t

RAH 10 10 10 ns

t

RAL 30 35 40 ns

t

RAS 60 10,000 70 10,000 80 10,000 ns

t

RCD 16 45 16 50 20 60 ns

t

RCS 0 0 0 ns

t

RP 40 50 60 ns

t

RSH 13 15 15 ns

t

RWC 150 180 200 ns

t

RWD 80 90 105 ns

t

RWL 15 15 20 ns

t

WP 10 12 15 ns

t

WRH 10 10 10 ns

t

WRP 10 10 10 ns

2-83

-6 -7 -8

AUSTIN SEMICONDUCTOR, INC.

,,,

,,,

,,

,

,

,

EDO-PAGE-MODE READ CYCLE

AS4LC4M4 883C

4 MEG x 4 DRAM

RAS

CAS

ADDR

t

RASP

V

IH

V

IL

t

CRP

V

IH

V

IL

t

ASR

V

IH

V

IL

V

WE

IH

V

IL

V

OH

DQ

V

OL

V

IH

OE

V

IL

t

WRPtWRH

NOTE 1

t
t

RAD
RAH

t

CSH

t

RCD

t

AR

t

ACH

t

ASC

t

RCS

t

CAS

t

CAH

t

AA

t

RAC

t

CAC

t

CLZ

t

OE

t

OES

t

PC

t

CP

VALID
DATA

VALID
DATA

t

CP

t

OEHC

t

t

OD

OD

t

OEP

t

CAS

t

ACH

t

t

CAH

ASC

t

AA

t

CPA

t

CAC

t

COH

t

RSH

t

CAS

t
t
t

t

ACH

ASC

CLZ

RAL

t

CAH

COLUMNCOLUMNCOLUMNROW ROW

t

AA
t

CPA
t

CAC

t

OE

t

OES

VALID
DATA

t

RP

t

CP

t

RCH

t

RRH

t

OFF

OPENOPEN

t

OD

DON’T CARE

UNDEFINED

NOTE: 1. Although ?W/E is a “don’t care” at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement

?W/E HIGH for

t

WRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.

TIMING PARAMETERS

SYM MIN MAX MIN MA X MIN MAX UNITS

-6 -7 -8

t

AA 30 35 40 ns

t

ACH 15 15 20 ns

t

AR 45 55 60 ns

t

ASC 0 0 0 ns

t

ASR 0 0 0 ns

t

CAC 15 20 20 ns

t

CAH 10 15 15 ns

t

CAS 12 10,000 15 10,000 20 10,000 ns

t

CLZ 0 0 0 ns

t

COH 5 5 5 ns

t

CP 10 10 10 ns

t

CPA 35 40 40 ns

t

CRP 5 5 5 ns

t

CSH 50 55 60 ns

t

OD015 015020ns

t

OE 15 20 20 ns

t

OEHC 10 10 10 ns

SYM MIN MAX MIN MA X MIN MAX UNITS

t

OEP 10 10 10 ns

t

OES 5 5 5 ns

t

OFF015 015020ns

t

PC 30 35 40 ns

t

RAC 60 70 80 ns

t

RAD 15 30 15 35 15 40 ns

t

RAH 10 10 10 ns

t

RAL 30 35 40 ns

t

RASP 60 100,000 70 100,000 80 100,000 ns

t

RCD 16 45 16 50 20 60 ns

t

RCH 0 0 0 ns

t

RCS 0 0 0 ns

t

RP 40 50 60 ns

t

RRH 0 0 0 ns

t

RSH 13 15 15 ns

t

WRH 10 10 10 ns

t

WRP 10 10 10 ns

-6 -7 -8

AS4LC4M4 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
Rev. 11/97
DS000022

2-84

,

,

,

,

,,,

RAS

,,,,

,,,,

,,,

,,,

,,,,

,,,

,

CAS

ADDR

WE

DQ

AUSTIN SEMICONDUCTOR, INC.

AS4LC4M4 883C

4 MEG x 4 DRAM

EDO-PAGE-MODE EARLY-WRITE CYCLE

t

RASP

V

IH

V

IL

t

CRP

V

IH

V

IL

t

ASR

V

IH

V

IL

t

WRPtWRH

V

IH

V

IL

V

IOH

V

IOL

V

IH

OE

V

IL

NOTE 1

t

RAH

t

RAD

t

CSH

t

RCD

t

AR

t

ASC

t

WCS

t

DS

t

CAS

t

ACH

t

CAH

t

CWL

t

WCH

t

WP

t

WCR

t

DHR

t

DH

VALID DATA VALID DATA VALID DATA

t

PC

t

CP

t

WCS

t

t

ASC

DS

t
t

ACH
CAH

t

t

CAS

t

CWL

t

WCH

t

WP

DH

t

CP

t

WCS

t

t

RSH

t

CAS

t

ACH

t

RAL

t

t

CAH

ASC

COLUMNCOLUMNCOLUMNROW ROW

t

CWL

t

WCH

t

WP

t

RWL

t

DS

DH

t

RP

t

CP

NOTE: 1. Although ?W/E is a “don’t care” at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement

?W/E HIGH for

TIMING PARAMETERS

SYM MIN MAX MIN M AX MIN MAX UNITS

t

ACH 15 15 20 ns

t

AR 45 55 60 ns

t

ASC 0 0 0 ns

t

ASR 0 0 0 ns

t

CAH 10 12 15 ns

t

CAS 12 10,000 15 10,000 20 10,000 ns

t

CP 10 10 10 ns

t

CRP 5 5 5 ns

t

CSH 50 55 60 ns

t

CWL 15 15 20 ns

t

DH 10 12 15 ns

t

DHR 40 50 55 ns

t

DS 0 0 0 ns

t

PC 30 35 40 ns

AS4LC4M4 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
Rev. 11/97
DS000022

-6 -7 -8

t

WRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.

-6 -7 -8

SYM MI N MAX MIN M AX MIN MAX UNITS

t

RAD 15 30 15 35 15 40 ns

t

RAH 10 10 10 ns

t

RAL 30 35 40 ns

t

RASP 60 100,000 70 100,000 80 100,00 ns

t

RCD 16 45 16 50 20 60 ns

t

RP 40 50 60 ns

t

RSH 13 15 15 ns

t

RWL 15 15 20 ns

t

WCH 10 12 15 ns

t

WCR 40 50 60 ns

t

WCS 0 0 0 ns

t

WP 10 12 15 ns

t

WRH 10 10 10 ns

t

WRP 10 10 10 ns

2-85

DON’T CARE

UNDEFINED

AUSTIN SEMICONDUCTOR, INC.

,,,

,,,,

,

,

,,

,

EDO-PAGE-MODE READ-WRITE CYCLE

(LATE WRITE and READ-MODIFY-WRITE cycles)

V

IH

RAS

V

IL

t

CRP

V

IH

CAS

V

IL

t

ASRtRAH

V

IH

ADDR

V

IL

V

IH

WE

V

IL

V

IOH

DQ

V

IOL

V

IH

V

OE

IL

ROW COLUMN COLUMN COLUMN ROW

t

WRPtWRH

NOTE 2

NOTE: 1.tPC is for LATE WRITE cycles only.

2. Although ?W/E is a “don’t care” at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement
?W/E HIGH for

t

WRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.

t

RCD

t

AR

t

RAD

t

t

RAC

OPEN

AS4LC4M4 883C

4 MEG x 4 DRAM

t

RASP

t

CSH

t

CAS

t

t

ASC

CAH

t

RCS

RWD

t

CWL
t

WP

t

AWD

t

CWD

t

AA

t

CAC

t

CLZ

t

DH

t

DS

VALID

D

OUT

t

OE

t
t

VALID

D

IN

t

OD

t

CP

t

ASCtCAH

t

AA

t

CPA

CAC
CLZ

t

OE

t

t

NOTE 1

PRWC

PC

t

CAS

t

CWL
t

WP

t

AWD
t

CWD

t

DH

t

DS

VALID
D

OUT

t

t

CAC

t

CLZ

VALID
D

IN

t

OD

CP

t

ASCtCAH

t

AA

t

CPA

t

OE

t

RSH

t

CAS

t

RAL

t

AWD

t

CWD

t

DS

VALID
D

OUT

t

RP

t

CP

t

RWL

t

CWL

t

WP

t

DH

VALID

OPEN

D

IN

t

OD

t

OEH

DON’T CARE

UNDEFINED

TIMING PARAMETERS

SYM MI N MAX MIN MAX MIN MAX UNITS

t

AA 30 35 40 ns

t

AR 45 55 60 ns

t

ASC 0 0 0 ns

t

ASR 0 0 0 ns

t

AWD 55 65 65 ns

t

CAC 15 20 20 ns

t

CAH 10 15 15 ns

t

CAS 12 10,000 15 10,000 20 10,000 ns

t

CLZ 0 0 0 ns

t

CP 10 10 10 ns

t

CPA 35 40 40 ns

t

CRP 5 5 5 ns

t

CSH 50 55 60 ns

t

CWD 35 40 45 ns

t

CWL 15 15 20 ns

t

DH 10 12 15 ns

t

DS 0 0 0 ns

t

OD 0 15 0 15 0 20 ns

AS4LC4M4 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
Rev. 11/97
DS000022

-6 -7 -8

-6 -7 -8

SYM MI N MAX MIN MAX MIN MAX UNITS

t

OE 15 20 20 ns

t

OEH 10 12 15 ns

t

PC 30 35 40 ns

t

PRWC

t
t
t
t
t
t
t
t
t
t
t
t
t
t

75 85 90 ns
RAC 60 70 80 ns
RAD 15 30 15 35 15 40 ns
RAH 10 10 10 ns
RAL 30 35 40 ns
RASP 60 100,000 70 100,000 80 100,000 ns
RCD 16 45 16 50 20 60 ns
RCS 0 0 0 ns
RP 40 50 60 ns
RSH 13 15 15 ns
RWD 80 90 105 ns
RWL 15 15 20 ns
WP 10 12 15 ns
WRH 10 10 10 ns
WRP 10 10 10 ns

2-86

AUSTIN SEMICONDUCTOR, INC.

,

,,,,

,,

,,

EDO-PAGE-MODE READ-EARLY-WRITE CYCLE

(Pseudo READ-MODIFY-WRITE)

AS4LC4M4 883C

4 MEG x 4 DRAM

t

RP

t

CP

ROW

RAS

CAS

ADDR

t

t

CP

t

ASCtCAH

COLUMN (B)

t

CPA

VALID DATA (A)

RASP

t

PC

t

WHZ

VALID

DATA (B)

t

CP

t

ASCtCAH

COLUMN (N)

t

WCS

tDSt

t

CAS

t

RCH

t

AA

t

CAC

t

COH

t

t

t

DH

VALID DATA

IN

CAS

ACH

WCH

t

RSH

t

RAL

V

IH

V

IL

t

CRP

V

IH

V

IL

t

RAD

t

ASRtRAH

V

IH

V

IL

V

IH

WE

V

IL

V

IOH

DQ

V

IOL

V

IH

OE

V

IL

ROW

t

WRPtWRH

NOTE 1

OPEN

t

CSH

t

RCD

t

AR

t

ASC

COLUMN (A)

t

RCS

t

RAC

t

PC

t

CAS

t

CAH

t

AA

t

CAC

t

OE

DON’T CARE

UNDEFINED

NOTE: 1. Although ?W/E is a “don’t care” at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement

?W/E HIGH for

t

WRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.

TIMING PARAMETERS

SYM MI N MAX MIN MA X MIN MAX UNITS

-6 -7 -8

t

AA 30 35 40 ns

t

ACH 15 15 20 ns

t

AR 45 55 60 ns

t

ASC 0 0 0 ns

t

ASR 0 0 0 ns

t

CAC 15 20 20 ns

t

CAH 10 15 15 ns

t

CAS 12 10,000 15 10,000 20 10,000 ns

t

COH 5 5 5 ns

t

CP 10 10 10 ns

t

CPA 35 40 40 ns

t

CRP 5 5 5 ns

t

CSH 50 55 60 ns

t

DH 10 12 15 ns

t

DS 0 0 0 ns

t

OE 15 20 20 ns

AS4LC4M4 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
Rev. 11/97
DS000022

-6 -7 -8

SYM MI N MAX MIN M AX MIN MAX UNITS

t

PC 30 35 40 ns

t

RAC 60 70 80 ns

t

RAD 15 30 15 35 15 40 ns

t

RAH 10 10 10 ns

t

RAL 30 35 40 ns

t

RASP 60 100,000 70 100,000 80 100,000 ns

t

RCD 16 45 16 50 20 60 ns

t

RCH 0 0 0 ns

t

RCS 0 0 0 ns

t

RP 40 50 60 ns

t

RSH 13 15 15 ns

t

WCH 10 12 15 ns

t

WCS 0 0 0 ns

t

WHZ013 015015ns

t

WRH 10 10 10 ns

t

WRP 10 10 10 ns

2-87

,

,

,,

RAS

,,,,

,,,

,,

,,,,

,

,

CAS

ADDRVV

WE

DQ

OEVV

AUSTIN SEMICONDUCTOR, INC.

READ CYCLE

(with ?W/E-controlled disable)

V

IH

V

IL

t

t

t

t

RCS

RCD

AR

ASC

COLUMN

t

CRP

V

IH

V

IL

t

RAD

ROW

t

WRPtWRH

t

RAH

OPEN

t

ASR

IH
IL

V

IH

V

IL

V

OH

V

OL

IH
IL

NOTE 1

t

t

t

t
t
t
t

CSH

CAS

CAH

AA
RAC
CAC
CLZ

AS4LC4M4 883C

4 MEG x 4 DRAM

t

CP

t

ASC

COLUMN

t

t

RCH

t

OE

VALID DATA

t

WPZ

RCS

t

WHZ

t

OD

OPEN

t

CLZ

NOTE: 1. Although ?W/E is a “don’t care” at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement

?W/E HIGH for

TIMING PARAMETERS

-6 -7 -8

SYM MI N MAX MIN M AX MI N MAX UNITS

t

AA 30 35 40 ns

t

AR 45 55 60 ns

t

ASC 0 0 0 ns

t

ASR 0 0 0 ns

t

CAC 15 20 20 ns

t

CAH 10 15 15 ns

t

CAS 12 10,000 15 10,000 20 10,000 ns

t

CLZ 0 0 0 ns

t

CP 10 10 10 ns

t

CRP 5 5 5 ns

t

CSH 50 55 60 ns

t

OD0 15 015020ns

AS4LC4M4 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
Rev. 11/97
DS000022

DON’T CARE

UNDEFINED

t

WRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.

-6 -7 -8

SYM MI N MAX MIN MAX M IN MAX UNITS

t

OE 15 20 20 ns

t

RAC 60 70 80 ns

t

RAD 15 30 15 35 15 40 ns

t

RAH 10 10 10 ns

t

RCD 16 45 16 50 20 60 ns

t

RCH 0 0 0 ns

t

RCS 0 0 0 ns

t

WHZ014016020ns

t

WPZ 10 12 15 ns

t

WRH 10 10 10 ns

t

WRP 10 10 10 ns

2-88

,,,,

,,,

,

,

RAS

,

,,,,

,,,

,,

,,

,,,

,

,,

CAS

ADDR

RAS

CAS

DQ

DQ

WE

AUSTIN SEMICONDUCTOR, INC.

??

??

//

?R

?A

/S-ONLY REFRESH CYCLE

??

??

//

t

RAS

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

V

OH

V

OL

V

IH

WE

V

IL

V

IH

V

IL

V

IH

V

IL

V

OH

V

OL

V

IH

V

IL

t

t

RPC

CP

t

CRP

t

ASR

t

t

t

RAH

ROW

t

WRH

WRP

NOTE 1

CBR REFRESH CYCLE

(Addresses and ?O/E = DON’T CARE)

t

WRPtWRH

t

t

RAS

CHR

RP

t

CSR

t

RPC

OPEN

OPEN

t

RP

t

CSR

t

RC

t

CHR

t

WRPtWRH

t

RPC

t

RAS

AS4LC4M4 883C

4 MEG x 4 DRAM

t

RP

ROW

t

t

WRH

WRP

NOTE: 1. Although ?W/E is a “don’t care” at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement

?W/E HIGH for

TIMING PARAMETERS

-6 -7 -8

SYM MI N MAX MIN MAX MIN M AX UNITS

t

ASR 0 0 0 ns

t

CHR 10 15 15 ns

t

CP 10 10 10 ns

t

CRP 5 5 5 ns

t

CSR 5 5 10 ns

t

RAH 10 10 10 ns

AS4LC4M4 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
Rev. 11/97
DS000022

DON’T CARE

UNDEFINED

t

WRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.

-6 -7 -8

SYM MI N MAX MIN MAX MIN MAX UNITS

t

RAS 60 10,000 70 10,000 80 10,000 ns

t

RC 110 130 150 ns

t

RP 40 50 60 ns

t

RPC 5 5 5 ns

t

WRH 10 10 10 ns

t

WRP 10 10 10 ns

2-89

AUSTIN SEMICONDUCTOR, INC.

,

,,,

,,,

,,,

,,

,,,,

,,,

,,

AS4LC4M4 883C

4 MEG x 4 DRAM

RAS

CAS

ADDR

HIDDEN REFRESH CYCLE

24

(?W/E = HIGH; ?O/E = LOW)

t

RAS

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

V

OH

DQ

V

OL

V

IH

OE

V

IL

t

CRP

t

ASR

t

RAH

t

RAD

t

RCD

t

AR

t

ASC

COLUMNROW

t

RAC

t

t

t

CAH

AA

t

CLZ

RAL

t

CAC

t

RSH

t

OE

t

ORD

t

RP

t

t

RAS

CHR

t

OFF

t

OPENVALID DATAOPEN

OD

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-6 -7 -8

SYM MI N MAX M IN MAX MIN MAX UNITS

t

AA 30 35 40 ns

t

AR 45 55 60 ns

t

ASC 0 0 0 ns

t

ASR 0 0 0 ns

t

CAC 15 20 20 ns

t

CAH 10 15 15 ns

t

CHR 10 15 15 ns

t

CLZ 0 0 0 ns

t

CRP 5 5 5 ns

t

OD 0 15 0 15 0 20 ns

t

OE 15 20 20 ns

AS4LC4M4 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
Rev. 11/97
DS000022

-6 -7 -8

SYM MI N MAX M IN MAX MIN MAX UNITS

t

OFF0 150150 20ns

t

ORD 0 0 0 ns

t

RAC 60 70 80 ns

t

RAD 15 30 15 35 15 40 ns

t

RAH 10 10 10 ns

t

RAL 30 35 40 ns

t

RAS 60 10,000 70 10,000 80 10,000 ns

t

RCD 16 45 16 50 20 60 ns

t

RP 40 50 60 ns

t

RSH 13 15 15 ns

2-90

AUSTIN SEMICONDUCTOR, INC.

ELECTRICAL TEST REQUIREMENTS

AS4LC4M4 883C

4 MEG x 4 DRAM

MIL-STD-883 TEST REQUIREMENTS (per Method 5005, Table I)

INTERIM ELECTRICAL (PRE-BURN-IN) TEST PARAMETERS 2, 8A, 10

(Method 5004)

FINAL ELECTRICAL TEST PARAMETERS 1*, 2, 3, 7*, 8, 9, 10, 11

(Method 5004)

GROUP A TEST REQUIREMENTS 1, 2, 3, 4**, 7, 8, 9, 10, 11

(Method 5005)

GROUP C AND D END-POINT ELECTRICAL PARAMETERS 1, 2, 3, 7, 8, 9, 10, 11

(Method 5005)

* PDA applies to subgroups 1 and 7.
** Subgroup 4 shall be measured only for initial qualification and after process or design changes, which may affect input

or output capacitance.

SUBGROUPS

AS4LC4M4 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
Rev. 11/97
DS000022

2-91

AUSTIN SEMICONDUCTOR, INC.

AS4LC4M4 883C

4 MEG x 4 DRAM

AS4LC4M4 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
Rev. 11/97
DS000022

2-92