Datasheet AS4LC256K16E0-60TC, AS4LC256K16E0-60JC, AS4LC256K16E0-45TC, AS4LC256K16E0-45JC, AS4LC256K16E0-35TC Datasheet (Alliance Semiconductor Corporation)
...Page 1
Copyright © Alliance Semiconductor. All rights reserved.
AS4LC256K16EO
4/11/01; V.1.1 Alliance Semiconductor P. 1 of 25
3.3V 256K X 16 CMOS DRAM (EDO)
®
Features
• Organization: 262,144 words × 16 bits
•High speed
- 45/60 ns RAS access time
- 10/12/15/20 ns column address access time
- 7/10/10 ns CAS
access time
• Low power consumption
- Active: 280 mW max (AS4LC256K16EO-35)
- Standby: 2.8 mW max, CMOS I/O (AS4LC256K16EO-
35)
•EDO page mode
•5V I/O tolerant
• 512 refresh cycles, 8 ms refresh interval
-RAS-only or CAS-before-RAS refresh or self refresh
• Read-modify-write
• LVTTL-compatible, three-state I/O
• JEDEC standard packages
- 400 mil, 40-pin SOJ
- 400 mil, 40/44-pin TSOP II
• 3.3V power supply
• Latch-up current > 200 mA
Pin arrangement
40
39
38
37
36
35
34
33
32
31
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
SOJ
30
29
28
27
26
25
24
23
22
21
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
GND
1
2
3
4
5
6
7
8
9
10
Vcc
I/O0
I/O1
I/O2
I/O3
Vcc
I/O4
I/O5
I/O6
I/O7
11
12
13
14
15
16
17
18
19
20
NC
NC
WE
RAS
NC
A0
A1
A2
A3
Vcc
V
CC
I/O0
I/O1
I/O2
I/O3
V
CC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
A0
A1
A2
A3
V
CC
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
GND
44
43
42
41
40
39
38
37
36
35
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
13
14
15
16
17
18
19
20
21
22
TSOP II
AS4LC256K16EO
AS4LC256K16EO
Pin designation
Pin(s) Description
A0 to A8 Address inputs
RAS
Row address strobe
I/O0 to I/O15 Input/output
OE
Output enable
UCAS
Column address strobe, upper byte
LCAS
Column address strobe, lower byte
WE
Read/write control
V
CC
Power (3.3V ± 0.3V)
GND Ground
Selection guide
Symbol AS4LC256K16EO-35 AS4LC256K16EO-45 AS4LC256K16EO-60 Unit
Maximum
RAS
access time t
RAC
35 45 60 ns
Maximum column address access time t
CAA
17 20 25 ns
Maximum
CAS
access time t
CAC
71010ns
Maximum output enable (
OE
) access time t
OEA
71010ns
Minimum read or write cycle time t
RC
50 80 100 ns
Minimum EDO page mode cycle time t
PC
15 17 30 ns
Maximum operating current I
CC1
70 60 50 mA
Maximum CMOS standby current I
CC2
200 200 200 µA
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Functional description
The AS4LC256K16EO is a high-performance 4 megabit CMOS Dynamic Random Access Memory (DRAM) organized as
262,144 words by 16 bits. The AS4LC256K16EO is fabricated with advanced CMOS technology and designed with innovative
design techniques resulting in high speed, extremely low power and wide operating margins at component and system levels.
The AS4LC256K16EO features a high speed page mode operation in which high speed read, write and read-write are
performed on any of the 512 × 16 bits defined by the column address. The asynchronous column address uses an extremely
short row address capture time to ease the system level timing constraints associated with multiplexed addressing. Very fast
CAS
to output access time eases system design.
Refresh on the 512 address combinations of A0 to A8 during an 8 ms period is accomplished by performing any of the
following:
•RAS-only refresh cycles
• Hidden refresh cycles
•CAS
-before-RAS refresh cycles
• Normal read or write cycles
• Self refresh cycles
The AS4LC256K16EO is available in standard 40-pin plastic SOJ and 40/44-pin TSOP II packages compatible with widely
available automated testing and insertion equipment. System level features include single power supply of 3.3V ± 0.3V
tolerance and direct interface with TTL logic families.
Logic block diagram
Recommended operating conditions
(Ta = 0°C to +70°C)
Parameter Symbol Min Typ Max Unit
Supply voltage
V
CC
3.03.33.6V
GND 0.0 0.0 0.0 V
Input voltage
V
IH
2.0 – VCC + 1 V
V
IL
–1.0 – 0.8 V
REFRESH
CONTROLLER
512×512×16
ARRAY
(4,194,304)
SENSE AMP
A0
A1
A2
A3
A4
A5
A6
A7
V
CC
GND
ADDRESS BUFFERS
A8
ROW DEC ODE R
COLUMN DECODER
RAS CLOCK
GENERATOR
SUBSTRATE
BIAS
GENERATOR
DATA
I/O
BUFFER
OE
RAS
UCAS
WE CLOCK
GENERATOR
WE
LCAS
I/O0 to I/O15
CAS CLOCK
GENERATOR
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Absolute maximum ratings
NOTE:
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC electrical characteristics
Parameter Symbol Min Max Unit
Input voltage V
in
-1.0 +7.0 V
Output voltage V
out
-1.0 +7.0 V
Power supply voltage V
CC
-1.0 +7.0 V
Operating temperature T
OPR
0+70°C
Storage temperature (plastic) T
STG
-55 +150 °C
Soldering temperature × time T
SOLDER
–260 × 10
o
C × sec
Power dissipation P
D
–1W
Short circuit output current I
out
–50mA
Latch-up current 200 – mA
Parameter Symbol Test conditions
-35 -45 -60
Unit NoteMinMaxMinMaxMinMax
Input leakage
current
I
IL
0V ≤ Vin ≤ +5.5V
pins not under test = 0V
-1010-1010-1010µA
Output leakage
current
I
OL
D
OUT
disabled,
0V ≤ V
out
≤ +5.5V
-1010-1010-1010µA
Operating power
supply current
I
CC1
RAS, UCAS, LCAS
, address cycling;
t
RC
=min
–70–60–50mA1,2
TTL standby power
supply current
I
CC2
RAS
=
UCAS
=
LCAS
= V
IH
–200–200–200µA
Ave r age power
supply current,
RAS
refresh mode
I
CC3
RAS
cycling,
UCAS
=
LCAS
= VIH,
t
RC
= min
–50–45–40mA1
EDO page mode
average power
supply current
I
CC4
RAS=UCAS=LCAS
=VIL,
address cycling: t
SC
= min
–40–35–35mA1,2
CMOS standby
power supply
current
I
CC5
RAS=UCAS=LCAS
= V
CC
- 0.2V – 400 – 400 – 400 µA
CAS
-before-
RAS
refresh power
supply current
I
CC6
RAS, UCAS, LCAS
, cycling;
t
RC
= min
–50–50–50mA1
Output Voltage
V
OH
I
OUT
= -2 mA 2.4 – 2.4 – 2.4 – V
V
OL
I
OUT
= 2 mA –0.4–0.4–0.4V
Self refresh current
I
CC7
RAS = UCAS = LCAS=VIL,
WE
= OE = A0-A8 = VCC-0.2V,
DQ0-DQ15 = V
CC
-0.2V,
0.2V are open
- 400 - 400 - 400 µA
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AC parameters common to all waveforms
Read cycle
Std Symbol Parameter
-35 -45 -60
Unit NotesMin Max Min Max Min Max
t
RC
Random read or write cycle time 50 – 80 – 100 – ns
t
RP
RAS
precharge time 15 – 20 – 20 – ns
t
RAS
RAS
pulse width 35 75K 45 75K 60 75K ns
t
CAS
CAS
pulse width 6 – 10 – 10 – ns
t
RCD
RAS
to
CAS
delay time 12 18 18 32 15 45 ns 6
t
RAD
RAS
to column address delay time 8 14 13 23 15 30 ns 7
t
RSH(R)
CAS
to
RAS
hold time (read cycle) 10 – 10 – 12 – ns
t
CSH
RAS
to
CAS
hold time 35 – 45 – 60 – ns
t
CRP
CAS
to
RAS
precharge time 5 – 5 – 5 – ns
t
ASR
Row address setup time 0 – 0 – 0 – ns
t
RAH
Row address hold time 6 – 8 – 9 – ns
t
T
Transition time (rise and fall) 1.5 50 1.5 50 1.5 50 ns 4,5
t
REF
Refresh period – 8 – 8 – 8 ms 3
t
CLZ
CAS
to output in low Z 0 – 3 – 3 – ns 8
Std Symbol Parameter
-35 -45 -60
Unit NotesMin Max Min Max Min Max
t
RAC
Access time from
RAS
–35–45–60ns 6
t
CAC
Access time from
CAS
– 7 – 10 – 10 ns 6,13
t
AA
Access time from address – 17 – 22 – 30 ns 7,13
t
AR(R)
Column add hold from
RAS
28 – 35 – 40 – ns
t
RCS
Read command setup time 0 – 0 – 0 – ns
t
RCH
Read command hold time to
CAS
0–0–0–ns9
tRRH
Read command hold time to
RAS
0–0–0–ns9
t
RAL
Column address to
RAS
Lead time 18 – 25 – 30 – ns
t
CPN
CAS
precharge time 4 – 5 – 5 – ns
t
OFF
Output buffer turn-off time 0 8 0 10 0 10 ns 8,10
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Write cycle
Read-modify-write cycle
Std Symbol Parameter
-35 -45 -60
Unit NotesMinMaxMinMaxMinMax
t
ASC
Column address setup time 0 – 0 – 0 – ns
t
CAH
Column address hold time 5 – 6 – 10 – ns
t
AW R
Column address hold time to
RAS
28 – 35 – 40 – ns
t
WCS
Write command setup time 0 – 0 – 0 – ns 11
t
WCH
Write command hold time 0 – 0 – 0 – ns 11
t
WCR
Write command hold time to
RAS
28 – 35 – 40 – ns
t
WP
Write command pulse width 5 – 6 – 10 – ns
t
RW L
Write command to
RAS
lead time 11 – 12 – 12 – ns
t
CWL
Write command to
CAS
lead time 11 – 12 – 12 – ns
t
DS
Data-in setup time 0 – 0 – 0 – ns 12
t
DH
Data-in hold time 5 – 6 – 10 – ns 12
t
DHR
Data-in hold time to
RAS
28 – 35 – 45 – ns
Std Symbol Parameter
-35 -45 -60
Unit NotesMin Max Min Max Min Max
t
RW C
Read-write cycle time 105 – 115 – 120 – ns
t
RW D
RAS
to WE delay time 54 – 58 – 60 – ns 11
t
CWD
CAS
to WE delay time 28 – 30 – 30 – ns 11
t
AW D
Column address to WE delay time 35 – 38 – 40 – ns 11
t
RSH(W)
CAS
to
RAS
hold time (write) 10 – 10 – 12 – ns
t
CAS(W)
CAS
pulse width (write) 15 – 15 – 15 – ns
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EDO page mode cycle
Refresh cycle
Output enable
Self refresh cycle
Std
Symbol Parameter
-35 -45 -60
Unit NotesMin Max Min Max Min Max
t
PC
Read or write cycle time (fast page) 15 – 17 – 25 – ns 14
t
CAP
Access time from
CAS
precharge – 19 – 21 – 23 ns 13
t
CP
CAS
precharge time (fast page) 4 – 5 – 6 – ns
t
PCM
EDO page mode RMW cycle 56 – 58 – 60 – ns
t
CRW
Page mode
CAS
pulse width (RMW) 44 – 46 – 50 – ns
t
RASP
RAS
pulse width 35 75K 45 75K 60 75K ns
Std
Symbol Parameter
-35 -45 -60
Unit NotesMin Max Min Max Min Max
t
CSR
CAS
setup time (
CAS
-before-
RAS
) 10 – 10 – 10 – ns 3
t
CHR
CAS
hold time (
CAS
-before-RAS)8–8–10–ns3
t
RPC
RAS precharge to
CAS
hold time 0 – 0 – 0 – ns
t
CPT
CAS
precharge time
(
CAS
-before-RAS counter test)
8–8–8–ns
Std
Symbol Parameter
-35 -45 -60
Unit NotesMin Max Min Max Min Max
t
ROH
RAS
hold time referenced to
OE
5–5–5–ns
t
OEA
OE
access time – 10 – 10 – 10 ns
t
OED
OE
to data delay 5 – 5 – 8 – ns
t
OEZ
Output buffer turnoff delay from
OE
–8–8–8ns8
t
OEH
OE
command hold time 8 – 8 – 8 – ns
Std Symbol Parameter
-35 -45 -60
Unit NotesMin Max Min Max Min Max
t
RASS
RAS
pulse width
(CBR self refresh)
100K – 100K – 100K – ns
t
RPS
RAS
precharge time
(CBR self refresh)
85 – 85 – 85 – ns
t
CHS
CAS
hold time
(CBR self refresh)
30 – 30 – 30 – ns
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Notes
1I
CC1
, I
CC3
, I
CC4
, and I
CC6
depend on cycle rate.
2I
CC1
and I
CC4
depend on output loading. Specified values are obtained with the output open.
3 An initial pause of 200 µs is required after power-up followed by any 8 RAS
cycles before proper device operation is achieved. In the case of an internal
refresh counter, a minimum of 8 CAS
-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after
extended periods of bias without clocks (greater than 8 ms).
4 AC Characteristics assume t
T
= 5 ns. All AC parameters are measured with a load equivalent to two TTL loads and 60 pF, VIL(min) ≥ GND and VIH (max)
≤
VCC.
5V
IH
(min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL.
6 Operation within the t
RCD
(max) limit insures that t
RAC
(max) can be met. t
RCD
(max) is specified as a reference point only. If t
RCD
is greater than the
specified t
RCD
(max) limit, then access time is controlled exclusively by t
CAC
.
7 Operation within the t
RAD
(max) limit insures that t
RAC
(max) can be met. t
RAD
(max) is specified as a reference point only. If t
RAD
is greater than the
specified t
RAD
(max) limit, then access time is controlled exclusively by tAA.
8 Assumes three state test load (5 pF and a 380 Ω Thevenin equivalent).
9Either t
RCH
or t
RRH
must be satisfied for a read cycle.
10 t
OFF
(max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels.
11 t
WCS
, t
WCH
, t
RW D
, t
CWD
and t
AW D
are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only. If tWS ≥ tWS
(min) and t
WH
≥ tWH (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the cycle. If t
RW D
≥
t
RWD
(min), t
CWD
≥ t
CWD
(min) and t
AW D
≥ t
AW D
(min), the cycle is a read-write cycle and the data out will contain data read from the selected cell.
If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate.
12 These parameters are referenced to CAS
leading edge in early write cycles and to WE leading edge in read-write cycles.
13 Access time is determined by the longest of t
CAA
or t
CAC
or t
CAP
.
14 t
ASC
≥ tCP to achieve tPC (min) and t
CAP
(max) values.
15 These parameters are sampled and not 100% tested.
Key to switching waveform
Read cycle waveform
Undefined/don’t care Falling inputRising input
t
RAS
t
RC
t
RP
t
RSH
t
RAD
t
RCH
t
OFF
RAS
UCAS
,
Address
WE
OE
I/O
Col Address
Row Address
t
CRP
t
CSH
t
RCD
t
ASC
t
CAH
t
CAS
t
AR
t
RAL
t
RAH
t
RCS
t
AA
t
CLZ
t
RRH
Data Out
t
ASR
t
RAC
t
ROH
t
OEA
t
CAC
t
OEZ
LCAS
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Upper byte read cycle waveform
Lower byte read cycle waveform
t
RAS
t
RC
t
RP
t
CRP
t
RCD
t
RSH
t
CSH
t
CRP
t
CRP
t
ASR
t
RAH
t
RAD
t
RAL
t
CAH
t
RCS
t
RRH
t
RCH
t
CLZ
t
CAC
t
OEZ
t
OFF
Row Column
Data Out
RAS
UCAS
LCAS
Address
WE
OE
Upper I/O
Lower I/O
t
ROH
t
ASC
t
RAC
t
OEA
t
AA
t
CAS
t
RAS
t
RC
t
RP
t
CRP
t
RCD
t
RSH
t
CRP
t
CRP
t
ASR
t
RAH
t
RAD
t
RAL
t
CAH
t
RRH
t
RCH
t
CLZ
t
CAC
t
RAC
t
OEZ
t
OFF
Row Column
Data Out
RAS
LCAS
UCAS
Address
WE
OE
Upper I/O
Lower I/O
t
CSH
t
ASC
t
RCS
t
ROH
t
OEA
t
AA
t
CAS
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Early write cycle waveform
Upper byte early write cycle waveform
t
RAS
t
RC
t
RP
t
CRP
t
RSH
t
RCD
t
CSH
t
CAS
t
RAH
t
RAD
t
ASC
t
AWR
t
CAH
t
WCS
t
CWL
t
RWL
t
WCH
t
WP
t
DS
t
DH
t
DHR
Col Address
Data In
RAS
UCAS
,
Address
WE
OE
I/O
Row Address
t
WCR
t
RAL
t
ASR
LCAS
t
RAS
t
RC
t
RP
t
RAH
t
RAD
t
AWR
t
CRP
t
ASC
t
CAH
t
RSH
t
RCD
t
CSH
t
CRP
t
CRP
t
RPC
t
RWL
t
WCS
t
WP
t
DS
t
DH
t
DHR
Row Address Column Address
Data In
RAS
Address
UCAS
LCAS
WE
OE
Upper I/O
Lower I/O
t
ASR
t
RAL
t
CAS
t
CWL
t
WCH
t
WCR
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Lower byte early write cycle waveform
Write cycle waveform
(OE controlled)
t
RC
t
RAS
t
RP
t
RAD
t
AWR
t
CRP
t
RPC
t
CRP
t
ASC
t
CAH
t
RSH
t
RCD
t
CSH
t
CRP
t
RWL
t
WP
t
WCS
t
WCR
t
WCH
t
DS
t
DH
t
DHR
Row Address Column Address
Data In
RAS
Address
UCAS
LCAS
WE
OE
Upper I/O
Lower I/O
t
CWL
t
RAH
t
CAS
t
RAL
t
ASR
Row Address
t
RAS
t
RC
t
RP
t
CRP
t
RSH
t
RCD
t
CSH
t
CAS
t
RAH
t
RAL
t
RAD
t
CAH
t
CWL
t
RWL
t
WCR
t
OEH
t
OED
t
DS
t
DH
Data In
RAS
UCAS
,
Address
WE
OE
I/O
Col Address
t
DHR
t
WP
t
ASC
t
AWR
t
ASR
LCAS
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Upper byte write cycle waveform
(OE controlled)
Lower byte write cycle waveform
(OE controlled)
t
RAS
t
RC
t
RP
t
RAL
t
RAD
t
ASC
t
CAH
t
CSH
t
CRP
t
CRP
t
RPC
t
RWL
t
WP
t
OEH
t
DS
t
DH
t
OED
Row Address Column Address
Data In
RAS
Address
UCAS
LCAS
WE
OE
Upper I/O
Lower I/O
t
CRP
t
AWR
t
RAH
t
RCD
t
RSH
t
CWL
t
ASR
t
CAS
t
RC
t
RAS
t
RP
t
RAH
t
RAD
t
ACS
t
CAH
t
RSH
t
CSH
t
CRP
t
CRP
t
RPC
t
RWL
t
WP
t
OEH
t
DS
t
DH
Row Address Column Address
Data In
RAS
Address
LCAS
UCAS
WE
OE
Upper I/O
Lower I/O
t
CRP
t
RCD
t
CAS
t
CWL
t
AWR
t
RAL
t
ASR
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Read-modify-write cycle waveform
t
RAS
t
RWC
t
RP
t
CRP
t
RSH
t
RCD
t
CSH
t
CAS
t
RAD
t
RAL
t
AR
t
CAH
t
CWL
t
CWD
t
RWL
t
AWD
t
WP
t
OEA
t
CLZ
t
CAC
t
AA
t
DS
tDH
Row Address Col Address
Data InData Out
RAS
UCAS
,
Address
WE
OE
I/O
t
RAH
t
RWD
t
RCS
t
RAC
t
OEZ
t
OED
t
ASC
t
ASR
LCAS
Page 14
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Upper byte read-modify-write cycle waveform
t
RWC
t
RAS
t
RP
t
CRP
t
RSH
t
RCD
t
CSH
t
CAS
t
CRP
t
CRP
t
RPC
t
RAL
t
CAH
t
RWL
t
AWD
t
WP
t
CWD
t
OEA
t
DS
t
CLZ
t
AA
t
RAC
t
CAC
t
OEZ
t
OED
Row
Column Address
Data In
Data Out
Data Out
RAS
UCAS
LCAS
Address
WE
OE
Upper Input
Upper Output
Lower Input
Lower Output
t
RWD
t
CWL
t
OED
t
RCS
t
RAH
t
ASR
t
ACS
t
RAD
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Lower byte read-modify-write cycle waveform
t
WP
t
RWC
t
RAS
t
RP
t
CRP
t
RPC
t
CRP
t
RSH
t
RCD
t
CSH
t
CAS
t
CRP
t
RAL
t
RAD
t
ACS
t
CAH
t
RCS
t
RWL
t
OEA
t
OED
t
DS
t
CLZ
t
OEZ
Row Colu mn Address
Data In
Data Out
RAS
UCAS
LCAS
Address
WE
OE
Upper Input
Upper Output
Lower Input
Lower Output
t
RAH
t
AWD
t
CWL
t
CWD
t
CAC
t
RWD
t
ASR
t
AA
t
RAC
Data Out
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EDO page mode read cycle waveform
EDO page mode byte read cycle waveform
Row
t
RASP
t
RP
t
CRP
t
RCD
t
CAS
t
CSH
t
RSH
t
PC
t
ASR
t
RAD
t
RCH
t
RCS
t
RRH
t
RCH
t
OEA
t
OEA
t
AA
t
RAC
t
CAC
t
CAP
Data Out Data Out
Col Address
Col Address
Col Address
RAS
UCAS
,
Address
WE
OE
I/O
t
AR
t
RAH
t
ASC
t
RAL
t
RCS
t
CLZ
t
CP
LCAS
t
CAC
t
CAH
t
RASP
t
RP
t
CAS
t
CSH
t
RSH
t
CAS
t
CRP
t
CRP
t
CP
t
CAS
t
CP
t
RPC
t
RAH
t
RAD
t
ASC
t
CAH
t
ASC
t
RCS
t
OEA
t
OEZ
t
OFF
t
CAC
t
RAC
t
OFF
t
OEZ
t
CLZ
t
AA
t
CAC
t
CAP
t
OFF
t
OEZ
Row Column 1 Column 2 C ol umn n
Data Out 1
Data Out n
Data Out 2
RAS
UCAS
LCAS
Address
WE
OE
Lower I/O
Upper I/O
t
CLZ
t
CAP
t
AA
t
CLZ
t
CAC
t
OEA
t
RCS
t
RCH
t
OEA
t
CAH
t
RAL
t
PC
t
PC
t
CAH
t
ASC
t
RCD
t
RCH
t
RCS
t
ASR
t
CRP
t
AA
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EDO page mode early write cycle waveform
EDO page mode byte early write cycle waveform
t
RAH
t
RASP
t
RWL
t
ASC
t
WCS
t
CP
t
RAL
t
WCH
t
CWL
t
WP
t
DS
t
DH
t
OED
t
CAS
Row address
Col address Col Addre ss Col Address
Data In Data In Data In
RAS
UCAS
,
Address
WE
OE
I/O
t
PC
t
CAH
t
CSH
t
RCD
t
OEH
t
HDR
t
AR
t
RAD
t
ASR
t
CRP
LCAS
t
RSH
t
RASP
t
RP
t
CAS
t
CSH
t
RSH
t
CAS
t
CRP
t
CRP
t
CP
t
CP
t
RPC
t
RAD
t
ASC
t
RAL
t
WCS
t
CWL
t
WCS
t
WCS
t
CWL
t
RWL
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
Row Column 1 Column 2 Colum n n
Data In 1
Data In n
Data In 2
RAS
UCAS
LCAS
Address
WE
OE
Lower I/O
Upper I/O
t
PC
t
RAH
t
WCH
t
WP
t
WP
t
CWL
t
WP
t
WCH
t
CAH
t
RCD
t
PC
t
CAH
t
CAH
t
ASR
t
CRP
t
ASC
t
ASC
t
CAS
t
WCH
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EDO page mode read-modify-write cycle waveform
CAS
-before-
RAS
refresh cycle waveform
(WE = VIH)
RAS
only refresh cycle waveform
(WE = OE =VIH or VIL)
t
RASP
t
RP
t
RCD
t
CSH
t
CAS
t
CP
t
CRP
t
ASR
t
CAH
t
CAH
t
RAL
t
CAH
t
CWD
t
AWD
t
CWD
t
CWL
t
CWD
t
AWD
t
RWL
t
WP
t
OEZ
t
OEA
t
RAC
t
DS
t
CLZ
t
CAC
t
CAP
Row Ad Col Ad Col AddressCol Ad
Data Out
Data InData In
Data OutData Out
Data In
RAS
UCAS
,
Address
WE
OE
I/O
t
RAD
t
RAH
t
RWD
t
RCS
t
CWL
t
OEA
t
AA
t
DH
t
DS
t
CLZ
t
CAC
t
CLZ
t
CAC
t
OED
t
PCM
LCAS
t
RP
t
RC
t
RAS
t
RPC
t
CPN
t
CSR
t
CHR
t
OFF
RAS
UCAS
,
I/O
LCAS
t
RAS
t
RP
t
RC
t
CRP
t
RPC
t
ARS
t
RAH
Row Address
RAS
UCAS
,
Address
LCAS
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EDO page mode byte read-modify-write cycle
t
RASP
t
RP
t
RCD
t
CAS
t
CSH
t
CRP
t
CP
t
CP
t
CAH
t
ASC
t
CAH
t
ASC
t
RAL
t
CWD
t
CWL
t
CWL
t
CWD
t
WP
t
RWL
t
OEA
t
DH
t
OEZ
t
DH
t
CLZ
t
CAC
t
AA
t
OEZ
Data Out 1
Data In n
Data Out n
Data Out 2
Data In 2
RC 1 C 2
C n
RAS
UCAS
LCAS
Address
WE
OE
Upper Input
Upper Output
Lower Input
Lower Output
t
PCM
t
CAS
t
RSH
t
CAS
t
AWD
t
ASC
t
WP
t
CWL
t
WP
t
OEA
t
OEA
t
OED
t
DS
t
CAP
t
DS
t
OED
t
OEZ
t
CLZ
t
DS
t
AA
t
CAC
t
CLZ
t
CRP
t
RAD
t
RAH
t
ASR
t
RCS
t
RWD
t
RAC
Data In 1
t
CAC
t
CAH
t
AWD
t
AWD
t
CWD
t
DH
t
AA
t
OED
Page 20
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Hidden refresh cycle (read) waveform
Hidden refresh cycle (write) waveform
t
RAS
t
RC
t
PR
t
RAS
t
RC
t
PR
t
CRP
t
RCD
t
RSH
t
CRP
t
CHR
t
ASR
t
RAD
t
ASC
t
RRH
t
OEA
t
CLZ
t
CAC
t
OEZ
t
OFF
Col AddressRow
Data Out
RAS
CAS
Address
WE
OE
I/O
t
AR
t
RAH
t
RAC
t
AA
t
RCS
t
RAS
t
RC
t
RP
t
CRP
t
RCD
t
RSH
t
ASR
t
RAH
t
RAD
t
AR
t
CAH
t
WCS
t
WCH
t
DS
t
DH
Data In
Col AddressRow Address
RAS
UCAS
,
Address
WE
I/O
OE
t
ASC
t
RWL
t
WCR
t
WP
t
DHR
t
RAL
LCAS
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CAS
-before-
RAS
refresh counter test cycle waveform
t
RAS
t
RSH
t
RP
t
CSR
t
CHR
t
CPT
t
CAS
t
CAH
t
CLZ
t
CAC
t
RCH
t
RRH
t
ROH
t
RWL
t
CWL
t
WCS
t
WP
t
WCH
t
DS
t
DH
t
RCS
t
OEA
t
DS
t
DH
Col Address
Data Out
Data In
Data Out Data In
RAS
UCAS
,
Address
I/O
WE
OE
WE
I/O
OE
WE
OE
I/O
t
OED
t
AA
t
CLZ
t
CAC
t
OEZ
t
WP
t
CWL
t
RCS
t
AA
t
OFF
t
AWD
t
CWD
t
RAL
Read CycleWrite CycleRead-Write Cycle
LCAS
t
OEA
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CAS
-before-
RAS
self refresh cycle
Typical DC and AC characteristics
t
RP
t
RASS
t
RPC
t
CP
t
CHS
t
CEZ
RAS
UCAS
,
DQ
LCAS
t
RPS
t
CSR
t
RPC
Supply voltage (V)
2.7 3.6
3.9
3.33.0
0.8
0.9
1.1
1.2
1.0
1.3
1.4
1.5
Normalized access time
Normalized access time t
RAC
Ambient temperature (°C)
–55 80
125
35–10
0.8
0.9
1.1
1.2
1.0
1.3
1.4
1.5
Normalized access time
Normalized access time t
RAC
Load capacitance (pF)
50 200 250150100
30
40
60
70
50
80
90
100
Typical access time
Typical access time t
RAC
vs. ambient temperature T
a
vs. load capacitance C
L
vs. supply voltage V
CC
Ta = 25°C
Supply voltage (V)
2.7 3.6
3.9
3.33.0
0.0
10
30
40
20
50
60
70
Supply current (mA)
Ty p i c a l su pp ly c u r r en t I
CC
Ambient temperature (°C)
–55 80
125
35–10
0.0
10
30
40
20
50
60
70
Supply current (mA)
Typical supply current I
CC
Cycle rate (MHz)
28
10
64
0.0
5
15
20
10
25
30
35
Power-on current (mA)
Typical power-on current I
PO
vs. ambient temperature T
a
vs. cycle rate 1/t
RC
vs. supply voltage V
CC
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Supply voltage (V)
2.7 3.6
3.9
3.33.0
0
5
15
20
10
25
30
35
Refresh current (mA)
Typical refresh current I
CC3
Ambient temperature (°C)
0.0 60
80
4020
Refresh current (mA)
Typical refresh current I
CC3
Supply voltage (V)
2.7 3.6 3.93.33.0
0
0.5
1.5
2.0
1.0
2.5
3.0
3.5
Stand-by current (mA)
Typical TTL stand-by current I
CC2
vs. Ambient temperature Ta vs. supply voltage V
CC
vs. supply voltage V
CC
0
5
15
20
10
25
30
35
Ambient temperature (°C)
060
80
4020
0.0
0.5
1.5
2.0
1.0
2.5
3.0
3.5
Stand-by current (mA)
Typical TTL stand-by current I
CC2
Output voltage (V)
0.0 1.5
2.0
1.00.5
0.0
10
30
40
20
50
60
70
Output sink current (mA)
Typical output sink current I
OL
Output voltage (V)
0.0 3.0
4.0
2.01.0
0.0
10
30
40
20
50
60
70
Output source current (mA)
Typical output source current I
O
H
vs. output voltage V
OL
vs. output voltage V
OH
vs. ambient temperature T
a
EDO page mode current (mA)
Ambient temperature (°C)
060
80
4020
0.0
5
15
20
10
25
30
35
EDO page mode current (mA)
Typical EDO page mode current I
CC4
Supply voltage (V)
2.7 3.6 3.93.33.0
0.0
5
15
20
10
25
30
35
Typical EDO page mode current I
CC4
vs. supply voltage V
CC
vs. ambient temperature T
a
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Package dimensions
Capacitance
ƒ = 1 MHz, Ta = room temperature, VCC = 3.3V ± 0.3V)
Parameter Symbol Signals Test conditions Max Unit
Input capacitance
C
IN1
A0 to A8 Vin = 0V 5 pF
C
IN2
RAS, UCAS, LCAS, WE, OE
Vin = 0V 7 pF
I/O capacitance C
I/O
I/O0 to I/O15 Vin = V
out
= 0V 7 pF
44-pin TSOP II
Min
(mm)
Max
(mm)
A
1.2
A
1
0.05
A
2
0.95 1.05
b0.30
0.45
c 0.127 (typical)
D 18.28
18.54
E 10.03 10.29
H
e
11.56 11.96
e 0.80 (typical)
l
0.40
0.60
D
H
e
12345678910 1314
44 43 42 41 40 39 38 37 36 35 32 31
15 16
30 29
17 18 19 20
28 27 26 25
c
l
A
1
A
2
e
44-pin TSOP II
0–5°
212422
23
E
A
b
40-pin SOJ
400 mil
Min Max
A
0.128 0.148
A1
0.026 -
A2
1.105 1.115
B
0.026 0.032
b
0.015 0.020
c
0.007 0.013
D
1.020 1.035
E
0.370 (typical)
E1
0.395 0.405
E2
0.435 0.445
e
D
E1
Pin 1
b
B
A1
A2
c
E
Seating
Plane
E2
A
40-pin SOJ
Page 25
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Ordering codes
Part numbering system
Package \ Access time 35 ns 45 ns 60 ns
Plastic SOJ, 400 mil, 40-pin AS4LC256K16E0-35JC AS4LC256K16E0-45JC AS4LC256K16EO-60JC
TSOP II, 400 mil, 40/44-pin AS4LC256K16EO-35TC AS4LC256K16EO-45TC AS4LC256K16EO-60TC
AS4LC 256K16E0 –XX X C
3.3V DRAM prefix Device number
RAS
access time
Package: J = SOJ
T = TSOP II
Commercial temperature range,
0°C to 70 °C
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