Datasheet AS4C4M4F1-60TC, AS4C4M4F1-60JI, AS4C4M4F1-60JC, AS4C4M4F1-50TI, AS4C4M4F1-50TC Datasheet (Alliance Semiconductor Corporation)
...Page 1
5V 4M×4 CMOS DRAM (Fast Page mode)
Features
• Organization: 4,194,304 words × 4 bits
• High speed
- 50/60 ns RAS access time
- 25/30 ns column address access time
- 12/15 ns CAS
• Low power consumption
- Active: 908 mW max
- Standby: 5.5 mW max, CMOS I/O
•Fast page mode
•Refresh
- 4096 refresh cycles, 64 ms refresh interval for
AS4C4M4F0
- 2048 refresh cycles, 32 ms refresh interval for
AS4C4M4F1
-RAS
-only or CAS-before-RAS refresh or self-refresh
access time
AS4C4M4F0
AS4C4M4F1
®
• TTL-compatible, three-state I/O
• JEDEC standard package
- 300 mil, 24/26-pin SOJ
- 300 mil, 24/26-pin TSOP
• Latch-up current ≥ 200 mA
• ESD protection ≥ 2000 mV
• Industrial and commercial temperature available
Pin arrangement
SOJ
V
CC
1
I/O0
2
I/O1
3
WE
4
RAS
*NC/A11 A9
5
621
A10
8
AS4C4M4F0
9
A0
10
A1
11
A2
12
A3
13
V
CC
*NC on 2K refresh version; A11 on 4K refresh version
GND
26
I/O3
25
I/O2
24
CAS
23
OE
22
A8
19
A7
18
A6
17
A5
16
15
A4
14
GND
V
I/O0
I/O1
WE
RAS
*NC/A11 A9
A10
V
A0
A1
A2
A3
CC
TSOP
CC
1
2
3
4
5
6
8
AS4C4M4F0
9
10
11
12
13
Selection guide
Maximum RAS
Maximum column address access time t
Maximum CAS
Maximum output enable (OE
Minimum read or write cycle time t
Minimum fast page mode cycle time t
Maximum operating current I
Maximum CMOS standby current I
access time t
access time t
) access time t
26
25
24
23
22
21
19
18
17
16
15
14
Symbol
RAC
CAA
CAC
OEA
RC
PC
CC1
CC5
GND
I/O3
I/O2
CAS
OE
A8
A7
A6
A5
A4
GND
Pin designation
Pin(s) Description
A0 to A11 Address inputs
RAS
CAS
WE
I/O0 to I/O3 Input/output
OE
V
CC
GND Ground
AS4C4M4F0-50
AS4C4M4F1-50
50 60 ns
25 30 ns
12 15 ns
13 15 ns
85 100 ns
25 30 ns
135 120 mA
1.0 1.0 mA
Row address strobe
Column address strobe
Write enable
Output enable
Power
AS4C4M4F0-60
AS4C4M4F1-60 Unit
4/11/01; v.0.9 Alliance Semiconductor
Copyright © Alliance Semiconductor. All rights reserved.
P. 1 of 18
Page 2
AS4C4M4F0
AS4C4M4F1
®
Functional description
The AS4C4M4F0 and AS4C4M4F1 are high performance 16-megabit CMOS Dynamic Random Access Memory (DRAM) devices organized as
4,194,304 words × 4 bits. The devices are fabricated using advanced CMOS technology and innovative design techniques resulting in high
speed, extremely low power and wide operating margins at component and system levels. The Alliance 16Mb DRAM family is optimized for
use as main memory in PC, workstation, router and switch applications.
These devices feature a high speed page mode operation where read and write operations within a single row (or page) can be executed at
very high speed by toggling column addresses within that row. Row and column addresses are alternately latched into input buffers using the
falling edge of RAS
column addresses prior to CAS
Refresh on the 4096 address combinations of A0 to A11 must be performed every 64 ms using:
-only refresh: RAS is asserted while CAS is held high. Each of the 4096 rows must be strobed. Outputs remain high impedence.
•RAS
• Hidden refresh: CAS
previous valid data.
-before-RAS refresh (CBR): CAS is asserted prior to RAS. Refresh address is generated internally.
•CAS
Outputs are high-impedence (OE
• Normal read or write cycles refresh the row being accessed.
• Self-refresh cycles
Refresh on the 2048 address combinations of A0 to A10 must be performed every 32 ms using:
-only refresh: RAS is asserted while CAS is held high. Each of the 2048 rows must be strobed. Outputs remain high impedence.
•RAS
• Hidden refresh: CAS
previous valid data.
-before-RAS refresh (CBR): CAS is asserted prior to RAS. Refresh address is generated internally.
•CAS
Outputs are high-impedence (OE
• Normal read or write cycles refresh the row being accessed.
• Self-refresh cycles
The AS4C4M4F0 and AS4C4M4F1 are available in the standard 24/26-pin plastic SOJ and 24/26-pin plastic TSOP packages. The
AS4C4M4F0 and AS4C4M4F1 operate with a single power supply of 5V ± 0.5V and provide TTL compatible inputs and outputs.
and CAS inputs respectively. Also, RAS is used to make the column address latch transparent, enabling application of
assertion.
is held low while RAS is toggled. Refresh address is generated internally. Outputs remain low impedence with
and WE are don't care).
is held low while RAS is toggled. Refresh address is generated internally. Outputs remain low impedence with
and WE are don't care).
Logic block diagram for 4K refresh
V
CC
GND
RAS
CAS
WE
RAS clock generator
CAS clock
generator
WE clock
generator
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
4/11/01; v.0.9 Alliance Semiconductor
Refresh
controller
Address buffers
Row decoder
Column decoder
Sense amp
4096 × 1024 × 4
Array
(16,777,216)
Data
I/O
buffers
I/O0 to I/O3
OE
P. 2 of 18
Page 3
Logic block diagram for 2K refresh
AS4C4M4F0
AS4C4M4F1
®
Data
I/O
buffers
I/O0 to I/O3
OE
Substrate bias
generator
RAS
CAS
WE
RAS clock generator
CAS clock
generator
WE clock
generator
V
GND
CC
Refresh
controller
A0
A1
A2
A3
A4
A5
A6
A10
A7
A8
A9
Address buffers
Row decoder
Column decoder
Sense amp
2048 × 2048 × 4
Array
(16,777,216)
Recommended operating conditions
Parameter Symbol Min Nominal Max Unit
V
Supply voltage
CC
GND 0.0 0.0 0.0 V
V
Input voltage
IH
V
IL
Commercial
Ambient operating temperature
Industrial -40 – 85
†
VIL min -3.0V for pulse widths less than 5 ns. Recommended operating conditions apply throughout this document unlesss otherwise specified.
T
A
4.5 5.0 5.5 V
2.4 – V
†
–0.5
–0.8V
CC
V
0–70
°C
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P. 3 of 18
Page 4
AS4C4M4F0
AS4C4M4F1
®
Absolute maximum ratings
Parameter Symbol Min Max Unit
Input voltage V
Input voltage (DQs) V
Power supply voltage V
Storage temperature (plastic) T
Soldering temperature × time T
Power dissipation P
Short circuit output current I
in
DQ
CC
STG
SOLDER
D
out
-1.0 +7.0 V
-1.0 VCC + 0.5 V
-1.0 +7.0 V
-55 +150 °C
–260 × 10
o
–1W
–50mA
DC electrical characteristics
-50 -60
Parameter Symbol Test conditions
Input leakage current I
Output leakage current I
Operating power
supply current
TTL standby power
supply current
Average power supply
current, RAS
refresh
mode or CBR
Fast page mode average
power supply current
CMOS standby power
supply current
Output voltage
CAS
before RAS refresh
current
I
I
I
I
I
V
V
I
IL
OL
CC1
CC2
CC3
CC4
CC5
OH
OL
CC6
0V ≤ Vin ≤ +5.5V,
Pins not under test = 0V
D
disabled, 0V ≤ V
OUT
RAS, CAS Address cycling; tRC=min – 135 – 120 mA 1,2
RAS = CAS ≥ V
RAS cycling, CAS ≥ V
t
= min of RAS low after XCAS low.
RC
RAS = VIL, CAS,
address cycling: t
RAS = CAS = VCC - 0.2V – 1.0 – 1.0 mA
I
= -5.0 mA 2.4 – 2.4 – V
OUT
I
= 4.2 mA – 0.4 – 0.4 V
OUT
RAS, CAS cycling, tRC = min – 120 – 110 mA
RAS = UCAS = LCAS ≤ 0.2V,
WE
Self refresh current I
CC7
= OE ≥ V
all other inputs at 0.2V or
V
- 0.2V
CC
IH
- 0.2V,
CC
HPC
-5 +5 -5 +5 µA
≤ +5.5V -5 +5 -5 +5 µA
out
–2.0 – 2.0mA
,
IH
= min
–120 –110mA 1
– 130 – 120 mA 1, 2
–0.6 – 0.6
Unit NotesMin Max Min Max
mA
C × sec
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P. 4 of 18
Page 5
®
AC parameters common to all waveforms
-50 -60
Symbol Parameter
t
RC
t
RP
t
RAS
t
CAS
t
RCD
t
RAD
t
RSH
t
CSH
t
CRP
t
ASR
t
RAH
t
T
t
REF
t
CP
t
RAL
t
ASC
t
CAH
Random read or write cycle time 80 – 100 – ns
RAS precharge time 30 – 40 – ns
RAS pulse width 50 10K 60 10K ns
CAS pulse width 8 10K 10 10K ns
RAS to CAS delay time 15 35 15 43 ns 6
RAS to column address delay time 12 25 12 30 ns 7
CAS to RAS hold time 10 – 10 – ns
RAS to CAS hold time 40 – 50 – ns
CAS to RAS precharge time 5 – 5 – ns
Row address setup time 0 – 0 – ns
Row address hold time 8 – 10 – ns
Transition time (rise and fall) 1 50 1 50 ns 4,5
Refresh period – 64 – 64 ms 3
CAS precharge time 8 – 10 – ns
Column address to RAS lead time 25 – 30 – ns
Column address setup time 0 – 0 – ns
Column address hold time 8 10 – ns
AS4C4M4F0
AS4C4M4F1
Unit NotesMinMaxMinMax
Read cycle
Symbol Parameter
t
RAC
t
CAC
t
AA
t
RCS
t
RCH
t
RRH
Access time from RAS – 50 – 60 ns 6
Access time from CAS – 12 – 15 ns 6,13
Access time from address – 25 – 30 ns 7,13
Read command setup time 0 – 0 – ns
Read command hold time to CAS 0–0–ns9
Read command hold time to RAS 0–0–ns9
-50 -60
Unit NotesMin Max Min Max
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P. 5 of 18
Page 6
®
Write cycle
-50 -60
Symbol Parameter
t
Write command setup time 0 – 0 – ns 11
WCS
t
Write command hold time 10 – 10 – ns 11
WCH
t
Write command pulse width 10 – 10 – ns
WP
t
Write command to RAS lead time 10 – 10 – ns
RW L
t
Write command to CAS lead time 8 – 10 – ns
CWL
Data-in setup time 0 – 0 – ns 12
t
DS
t
Data-in hold time 8 – 10 – ns 12
DH
Unit NotesMin Max Min Max
Read-modify-write cycle
-50 -60
Symbol Parameter
Read-write cycle time 113 – 135 – ns
t
RW C
RAS to WE delay time 67 – 77 – ns 11
t
RW D
CAS to WE delay time 32 – 35 – ns 11
t
CWD
t
Column address to WE delay time 42 – 47 – ns 11
AW D
Unit NotesMin Max Min Max
AS4C4M4F0
AS4C4M4F1
Refresh cycle
-50 -60
Symbol Parameter
CAS setup time (CAS-before-RAS)5–5–ns3
t
CSR
t
CAS hold time (CAS-before-RAS)8–10–ns3
CHR
RAS precharge to CAS hold time 0 – 0 – ns
t
RPC
precharge time
t
CPT
CAS
(CBR counter test)
10 10 – ns
Unit NotesMin Max Min Max
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P. 6 of 18
Page 7
Fast page mode cycle
Symbol Parameter
t
CPA
t
RASP
t
PC
t
CP
t
PCM
t
CRW
Access time from
pulse width 50 100K 60 100K
RAS
Read-write cycle time 30 – 35 –
precharge time (fast page) 10 – 10 –
CAS
Fast page mode RMW cycle 80 – 85 –
Page mode
CAS
Output enable
Symbol Parameter
t
CLZ
t
ROH
t
OEA
t
OED
t
OEZ
t
OEH
t
OLZ
t
OFF
CAS to output in Low Z 0 – 0 – ns 8
RAS hold time referenced to OE 8–10–ns
OE access time – 13 – 15 ns
OE to data delay 13 – 15 – ns
Output buffer turnoff delay from OE 013015ns8
OE command hold time 10 – 10 – ns
OE to output in Low Z 0 – 0 – ns
Output buffer turn-off time 0 13 0 15 ns 8,10
®
-50 -60
precharge – 28 – 35 13
CAS
pulse width (RMW) 12 – 15 –
-50 -60
AS4C4M4F0
AS4C4M4F1
Unit NotesMin Max Min Max
Unit NotesMin Max Min Max
Self refresh cycle
Std
Symbol Parameter
t
RASS
t
RPS
t
CHS
RAS pulse width
(CBR self refresh)
RAS precharge time
(CBR self refresh)
hold time
CAS
(CBR self refresh)
-50 -60
Unit NotesMinMaxMinMax
100–100– µs
90 – 105 – ns
8–10–ns
4/11/01; v.0.9 Alliance Semiconductor
P. 7 of 18
Page 8
®
Notes
1I
, I
, I
CC1
2I
CC1
and I
, and I
CC3
CC4
depend on output loading. Specified values are obtained with the output open.
CC4
3 An initial pause of 200 µs is required after power-up followed by any 8 RAS
refresh counter, a minimum of 8 CAS
extended periods of bias without clocks (greater than 8 ms).
4 AC Characteristics assume t
VCC.
(max)
≤
5V
(min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL.
IH
6 Operation within the t
specified t
(max) limit, then access time is controlled exclusively by t
RCD
7 Operation within the t
specified t
(max) limit, then access time is controlled exclusively by tAA.
RAD
8 Assumes three state test load (5 pF and a 380
9Either t
10 t
OFF
rising edge of RAS
11 t
WCS
If t
cycle. If t
or t
RCH
RRH
(max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. t
, t
, t
WCH
RW D
≥ tWS (min) and tWH ≥ tWH (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the
WS
RW D
≥ t
selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate.
12 These parameters are referenced to CAS
13 Access time is determined by the longest of t
14 t
≥ tCP to achieve tPC (min) and t
ASC
15 These parameters are sampled and not 100% tested.
16 These characteristics apply to AS4C4M4F0 5V devices.
are dependent on frequency.
CC6
-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after
= 2 ns. All AC parameters are measured with a load equivalent to two TTL loads and 100 pF, VIL(min) ≥ GND and VIH
T
(max) limit insures that t
RCD
(max) limit insures that t
RAD
Ω
must be satisfied for a read cycle.
or CAS, whichever occurs last.
, t
RW D
and t
CWD
(min), t
are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only.
AWD
≥ t
CWD
(min) and t
CWD
leading edge in early write cycles and to WE leading edge in read-write cycles.
CAA
(max) values.
CPA
(max) can be met. t
RAC
(max) can be met. t
RAC
Thevenin equivalent).
≥ t
(min), the cycle is a read-write cycle and the data out will contain data read from the
AW D
CPA
or t
CAC
AW D
or t
cycles before proper device operation is achieved. In the case of an internal
(max) is specified as a reference point only. If t
RCD
.
CAC
(max) is specified as a reference point only. If t
RAD
AS4C4M4F0
AS4C4M4F1
is greater than the
RCD
is greater than the
RAD
is referenced from
OFF
AC test conditions
- Access times are measured with output reference levels of VOH =
2.4V and V
= 2.4V and VIL = 0.8V
V
IH
- Input rise and fall times: 2 ns
= 0.4V,
OL
+5V
R1 = 828
D
out
100 pF* R2 = 295
GND
Figure A: Equivalent output load
Key to switching waveforms
Ω
Ω
*including scope
and jig capacitance
+3.3V
R1 = 828
D
out
50 pF* R2 = 295
GND
Figure B: Equivalent output load
(AS4LC4M4E0)(AS4C4M4E0)
Undefined output/don’t careFalling inputRising input
Ω
Ω
*including scope
and jig capacitance
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P. 8 of 18
Page 9
Read waveform
RAS
CAS
AS4C4M4F0
AS4C4M4F1
®
t
t
RAS
t
RCD
t
t
CRP
t
ASC
CSH
t
RCS
RC
t
RSH
t
CAH
t
CAS
t
RP
t
ASR
Address
Row address
WE
OE
DQ
Early write waveform
RAS
t
CRP
CAS
t
ASR
Address
WE
Row address
t
t
RAH
RAH
t
RAD
t
RAL
Column address
t
RRH
t
ROH
t
RAC
t
RCD
t
RAD
t
AA
t
OEA
t
t
CLZ
t
RAS
t
CSH
CAC
t
OLZ
t
RC
t
RSH
t
CAS
t
RAL
t
ASC
t
CAH
t
ROH
t
Data out
REZ
t
RCH
t
WEZ
t
OEZ
t
(see note 11)
OFF
t
RP
Column address
t
CWL
t
RW L
t
t
WCS
WP
t
WCH
OE
DQ
t
DS
Data in
t
DH
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Page 10
AS4C4M4F0
AS4C4M4F1
®
Write waveform
RAS
t
CRP
CAS
t
ASR
Address
Row address
WE
OE
DQ
Read-modify-write waveform
RAS
t
CRP
CAS
t
ASR
Address
WE
OE
DQ
Row address Column address
OE controlled
t
t
CAH
t
t
RAL
t
RC
CAS
DS
t
t
t
RSH
CWL
DH
t
RWL
t
OEH
t
WP
t
RP
Data in
t
RW C
t
CAS
t
RSH
t
RAL
t
CAH
t
AW D
t
CWD
t
t
OEZ
t
CAC
t
CLZ
OED
t
t
CWL
t
DS
t
DH
t
RP
t
RW L
WP
Data inData out
t
RAS
t
CSH
t
RCD
t
RAD
t
RAH
t
ASC
Column address
t
OED
t
RAS
t
RCD
t
AR
t
RAD
t
RAH
t
RCS
t
RAC
t
t
CSH
t
ASC
t
RWD
t
OEA
AA
t
OLZ
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P. 10 of 18
Page 11
Fast page mode read waveform
RAS
t
RASP
AS4C4M4F0
AS4C4M4F1
®
t
RP
t
CRP
t
RCD
CAS
t
AR
t
t
Row
RAD
RAH
Address
t
ASR
WE
OE
t
RAC
I/O
Fast page mode byte write waveform
RAS
t
t
OEA
t
RWD
CSH
t
AWD
t
CWD
t
AA
t
CLZ
t
CAC
Data out
CAS
Address
WE
OE
I/O
t
ASR
t
RCD
t
RAD
t
RAH
Row Column ColumnColumn
t
RCS
t
RAC
t
CSH
t
CAS
Column Column
t
RCS
t
RCH
t
OEA
t
CLZ
t
AA
Data out Data out Data out
t
t
PCM
t
t
CAH
CAS
t
OEZ
t
DS
t
CWL
t
DH
t
CP
RASP
t
CP
t
CWD
t
CLZ
t
CAC
Data out
t
RSH
t
PC
t
t
ASC
t
RAL
CAH
Column
t
Data in
t
WP
RRH
t
CWL
t
RWL
t
CRP
t
RP
t
RCS
t
OEZ
t
OFF
t
CAH
t
OED
t
DS
t
CAP
t
t
t
CLZ
t
t
OEA
CAP
CAC
CAH
t
t
AWD
CWD
t
RAL
t
RCH
t
OEA
t
CAC
Data inData in
Data out
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Page 12
Fast page mode early write waveform
t
RAH
RAS
CAS
Address
WE
OE
I/O
t
CRP
t
ASR
t
RCD
t
CSH
t
t
RAD
AR
Row Column Column Column
t
HDR
t
DS
Data In Data in Data in
AS4C4M4F0
AS4C4M4F1
®
t
RASP
t
t
WCH
t
PC
OED
t
t
CAS
t
DH
ASC
t
WCS
t
RWL
t
OEH
t
CAH
RSH
t
CP
t
RAL
t
CWL
t
WP
t
CAS before RAS refresh waveform
t
RP
RAS
t
RPC
t
CP
CAS
DQ
RAS only refresh waveform
RAS
CAS
t
ASR
Address
t
CSR
Row address
t
CRP
WE = VIH
t
RC
t
CHR
OPEN
t
RAS
t
RAH
t
RAS
WE = OE = VIH or V
t
RC
t
RPC
t
RP
IL
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Page 13
Hidden refresh waveform (read)
AS4C4M4F0
AS4C4M4F1
®
t
RAS
RAS
t
CRP
t
RCD
CAS
t
AR
t
ASR
t
RAD
t
RAH
Address
t
RCS
WE
OE
t
RAC
t
AA
DQ
Hidden refresh waveform (write)
RAS
CAS
Address
WE
DQ
t
CRP
t
ASR
t
RAH
t
RAD
t
WCS
t
t
ASC
t
DS
RCD
t
t
AR
WCR
t
Col addressRow
t
DHR
ASC
t
t
CLZ
RC
t
RSH
t
t
CAC
OEA
t
CAH
t
RRH
t
RP
t
CHR
t
RAS
t
t
OFF
OEZ
t
RC
t
CRP
t
RP
Data out
t
t
RAL
t
RC
t
CAH
RSH
t
RP
t
CHR
t
RAS
Col addressRow address
t
RWL
t
WP
t
WCH
t
DH
Data in
OE
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Page 14
CAS before RAS refresh counter test waveform
RAS
t
CSR
t
CAS
Address
DQ
WE
Read cycleWrite cycleRead-Write cycle
OE
WE
DQ
CHR
t
RCS
t
ASC
t
CPT
t
RAS
Col address
t
AA
t
WCS
t
DS
Data in
AS4C4M4F0
AS4C4M4F1
®
t
t
t
CAH
t
CLZ
t
WP
t
CAC
OEA
DH
t
t
WCH
CWL
t
CAS
t
RWL
t
t
RSH
RAL
Data out
t
ROH
t
OEZ
t
OFF
t
t
RRH
RCH
t
RP
OE
WE
OE
DQ
t
t
CLZ
CAC
t
RCS
t
CWD
t
AWD
t
OEA
t
AA
t
OEZ
t
OED
Data out Data in
t
RWL
t
WP
t
CWL
t
DH
t
DS
4/11/01; v.0.9 Alliance Semiconductor
P. 14 of 18
Page 15
CAS-before-RAS self refresh cycle
AS4C4M4F0
AS4C4M4F1
®
t
RP
RAS
t
RPC
t
CP
UCAS,
LCAS
t
CEZ
DQ
Typical DC and AC characteristics
Normalized access time t
vs. supply voltage V
1.5
1.4
Ta = 25°C
1.3
1.2
1.1
1.0
Normalized access time
0.9
RAC
CC
t
CSR
Normalized access time t
vs. ambient temperature T
1.5
1.4
1.3
t
RASS
RAC
t
CHS
a
100
90
80
t
RPS
t
RPC
Typical access time t
vs. load capacitance C
RAC
L
-70
1.2
1.1
1.0
Normalized access time
0.9
70
60
50
Typical access time
-60
-50
40
0.8
4.0 5.5
Supply voltage (V)
Typical supply current I
vs. supply voltage V
170
160
150
-50
-60
-70
Supply current (mA)
140
130
120
110
100
4.0 5.5
Supply voltage (V)
5.04.5
6.0
–55 80
35–10
125
Ambient temperature (°C)
0.8
Typical supply current I
vs. ambient temperature T
CC
a
CC
CC
170
160
150
140
130
120
Supply current (mA)
-50
-60
-70
110
100
5.04.5
6.0
–55 80
35–10
125
Ambient temperature (°C)
30
50 200 250150100
Load capacitance (pF)
Typical power-on current I
vs. cycle rate 1/t
35
PO
RC
30
25
20
15
10
Power-on current (mA)
5
0.0
28
64
10
Cycle rate (MHz)
4/11/01; v.0.9 Alliance Semiconductor
P. 15 of 18
Page 16
AS4C4M4F0
AS4C4M4F1
®
Typical refresh current I
vs. supply voltage V
160
140
120
100
-50
-60
-70
80
60
Refresh current (mA)
40
20
4.0 5.5
Supply voltage (V)
Typical TTL stand-by current I
vs. ambient temperature T
3.5
3.0
2.5
2.0
1.5
CC
CC3
Typical refresh current I
vs. Ambient temperature Ta vs. supply voltage V
CC3
160
140
120
-50
-60
Typical TTL stand-by current I
3.5
3.0
2.5
CC2
CC
-70
100
80
60
Refresh current (mA)
40
20
5.04.5
6.0
0.0 60
4020
Ambient temperature (°C)
CC2
a
Typical output sink current I
vs. output voltage V
70
OL
OL
60
50
40
30
80
2.0
1.5
1.0
Stand-by current (mA)
0.5
0
4.0 5.5 6.05.04.5
Supply voltage (V)
Typical output source current I
vs. output voltage V
70
60
50
40
30
OH
OH
1.0
Stand-by current (mA)
0.5
0.0
060
4020
80
Ambient temperature (°C)
Typical fast page mode current I
vs. ambient temperature T
140
CC4
a
120
100
80
60
-50
-60
-70
40
20
Hyper page mode current (mA)
0.0
060
4020
80
Ambient temperature (°C)
20
Output sink current (mA)
10
0.0
0.0 1.5
1.00.5
Output voltage (V)
Typical fast page mode current I
vs. supply voltage V
140
120
100
80
-50
-60
-70
60
40
20
Hyper page mode current (mA)
0.0
4.0 5.5 6.05.04.5
Supply voltage (V)
CC
2.0
CC4
20
10
Output source current (mA)
0.0
0.0 3.0
Output voltage (V)
2.01.0
4.0
4/11/01; v.0.9 Alliance Semiconductor
P. 16 of 18
Page 17
AS4C4M4F0
AS4C4M4F1
®
Capacitance
15
ƒ = 1 MHz, Ta = Room temperature
Parameter Symbol Signals Test conditions Max Unit
Input capacitance
DQ capacitance C
C
IN1
C
RAS, UCAS, LCAS, WE, OE Vin = 0V 7 pF
IN2
DQ
A0 to A9 Vin = 0V 5 pF
DQ0 to DQ15 Vin = V
= 0V 7 pF
out
AS4C4M4F0 ordering information
Package \ RAS access time 50 ns 60 ns
Plastic SOJ, 300 mil, 24/26-pin 5V
Plastic TSOP, 300 mil, 24/26-pin 5V
AS4C4M4F0-50JC
AS4C4M4F0-50JI
AS4C4M4F0-50TC
AS4C4M4F0-50TI
AS4C4M4F0-60JC
AS4C4M4F0-60JI
AS4C4M4F0-60TC
AS4C4M4F0-60TI
AS4C4M4F1 ordering information
Package \ RAS
Plastic SOJ, 300 mil, 24/26-pin 5V
Plastic TSOP, 300 mil, 24/26-pin 5V
access time 50 ns 60 ns
AS4C4M4F1-50JC
AS4C4M4F1-50JI
AS4C4M4F1-50TC
AS4C4M4F1-50TI
AS4C4M4F1-60JC
AS4C4M4F1-60JI
AS4C4M4F1-60TC
AS4C4M4F1-60TI
AS4C4M4F0/F1 family part numbering system
AS4 C 4M4 F0/F1 –XX X X
DRAM
prefix
C = 5V CMOS 4M×4
F0=4K refresh
F1=2K refresh
RAS
time
access
Package:
J = SOJ 300 mil, 24/26
T = TSOP 300 mil, 24/26
Temperature range
C=Commercial, 0°C to 70 °C
I=Industrial, -40°C to 85°C
4/11/01; v.0.9 Alliance Semiconductor
© Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and p roduct names may be the
trademarks of their respective companies. Alliance reser ves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in
this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product
described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and
users, and is not intended to o perate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsi bility or liability ar ising out of the applicati on or use of any product
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P. 17 of 18
Page 18
AS4C4M4F0
AS4C4M4F1
®
4/11/01; v.0.9 Alliance Semiconductor
P. 18 of 18
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