Datasheet AS4C256K16E0-35JC, AS4C256K16E0-50TC, AS4C256K16E0-50JC Datasheet (Alliance Semiconductor Corporation)

5V 256K×16 CMOS DRAM (EDO)

Features

• Organization: 262,144 words × 16 bits

•High speed

- 30/35/50 ns RAS

- 16/18/25 ns column address access time

- 7/10/10/10 ns CAS

• Low power consumption

- Active: 500 mW max (AS4C256K16E0-25)

- Standby: 3.6 mW max, CMOS I/O (AS4C256K16E0-25)

•EDO page mode

access time

AS4C256K16E0

®

• Refresh

- 512 refresh cycles, 8 ms refresh interval

-RAS

-only or CAS-before-RAS refresh or self-refresh

- Self-refresh option is available for new generation device only. Contact Alliance for more information.

• Read-modify-write

• TTL-compatible, three-state I/O

• JEDEC standard packages

- 400 mil, 40-pin SOJ

- 400 mil, 40/44-pin TSOP II

• 5V power supply

• Latch-up current > 200 mA

Pin arrangement

SOJ

V

Vcc I/O0 I/O1 I/O2 I/O3

Vcc I/O4 I/O5 I/O6 I/O7

NC NC

WE

RAS

NC

A0 A1 A2 A3

Vcc

40

1 2 3 4 5 6 7 8

9 10 11 12 13

AS4C256K16E0

14 15 16 17 18 19 20

GND

39

I/O15

38

I/O14

37

I/O13

36

I/O12

35

GND

34

I/O11

33

I/O10

32

I/O9

31

I/O8

30

NC

29

LCAS UCAS

28 27

OE

26

A8

25

A7

24

A6

23

A5

22

A4

21

GND

I/O0 I/O1

I/O2 I/O3

V I/O4

I/O5 I/O6

I/O7

NC NC

WE

RAS

NC

A0 A1 A2 A3

V

CC

Selection guide

Maximum

Maximum column address access time

Maximum

Maximum output enable (OE) access time

Minimum read or write cycle time

Minimum EDO page mode cycle time

Maximum operating current

Maximum CMOS standby current

Shaded areas contain advance information.

access time

RAS

access time

CAS

Pin designation

TSOP II

GND

1 2 3 4 5 6 7 8 9 10

13 14 15 16 17 18 19 20 21 22

44 43

I/O15 I/O14

42

I/O13

41

I/O12

40

GND

39

I/O11

38

I/O10

37

I/O9

36

I/O8

35

NC

32

AS4C256K16E0

LCAS

31

UCAS

30

OE

29

A8

28

A7

27

A6

26

A5

25

A4

24

GND

23

Symbol AS4C256K16E0-30 AS4C256K16E0-35 AS4C256K16E0-50 Unit

t

RAC

t

CAA

t

CAC

t

OEA

t

RC

t

PC

I

CC1

I

CC2

Pin(s) Description

A0 to A8 Address inputs

RAS

Row address strobe

I/O0 to I/O15 Input/output

OE

UCAS

LCAS

WE

V

CC

Output enable

Column address strobe, upper byte

Column address strobe, lower byte

Read/write control

Power (5V ± 0.5V)

GND Ground

30 35 50 ns 16 18 25 ns 10 10 10 ns 10 10 10 ns 65 70 85 ns 12 14 25 ns

180 160 140 mA

2.0 2.0 2.0 mA

4/11/01; v.1.1

Alliance Semiconductor

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AS4C256K16E0

®

Functional description

The AS4C256K16E0 is a high performance 4 megabit CMOS Dynamic Random Access Memory (DRAM) organized as 262,144 words by 16 bits. The AS4C256K16E0 is fabricated with advanced CMOS technology and designed with innovative design techniques resulting in high speed, extremely low power and wide operating margins at component and system levels.

The AS4C256K16E0 features a high speed page mode operation in which high speed read, write and read-write are performed on any of the

×

16 bits defined by the column address. The asynchronous column address uses an extremely short row address capture time to ease

512 the system level timing constraints associated with multiplexed addressing. Very fast CAS

to output access time eases system design.

Refresh on the 512 address combinations of A0 to A8 during an 8 ms period is accomplished by performing any of the following:

•RAS-only refresh cycles

• Hidden refresh cycles

•CAS

-before-RAS refresh cycles

• Normal read or write cycles

• Self-refresh cycles*

The AS4C256K16E0 is available in standard 40-pin plastic SOJ and 40/44-pin TSOP II packages compatible with widely available automated

±

testing and insertion equipment. System level features include single power supply of 5V

0.5V tolerance and direct interface with TTL logic

families.

Logic block diagram

V

CC

GND

A0 A1

RAS

UCAS

LCAS

WE

RAS CLOCK GENERATOR

CAS CLOCK GENERATOR

WE CLOCK GENERATOR

A2 A3 A4 A5 A6 A7 A8

Recommended operating conditions

COLUMN DECODER

REFRESH

CONTROLLER

ADDRESS BUFFERS

ROW DECODER

SENSE AMP

512×512×16

ARRAY

(4,194,304)

DATA

I/O

BUFFER

I/O0 to I/O15

OE

SUBSTRATE

BIAS

GENERATOR

(Ta = 0°C to +70°C)

Parameter Symbol Min Typ Max Unit

Supply voltage

V

CC

4.5 5.0 5.5 V

GND 0.0 0.0 0.0 V

Input voltage

V

IH

V

IL

2.4 – VCC + 1 V

–1.0 – 0.8 V

*Self-refresh option is available for new generation device only. Contact Alliance for more information.

4/11/01; v.1.1

Alliance Semiconductor

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AS4C256K16E0

®

Absolute maximum ratings

Parameter Symbol Min Max Unit

Input voltage V

Output voltage V

Power supply voltage V

Operating temperature T

Storage temperature (plastic) T

Soldering temperature × time T

Power dissipation P

Short circuit output current I

in

out

CC

OPR

STG

SOLDER

D

out

-1.0 +7.0 V

0+70°C

-55 +150 °C

–260 × 10

o

C × sec

–1W

–50mA

Latch-up current 200 – mA

NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC electrical characteristics

-30 -35 -50

Parameter Symbol Test conditions

Input leakage current

Output leakage current

Operating power supply current

TTL standby power supply current

I

IL

OL

CC1

CC2

Average power supply current, RAS

refresh mode

I

CC3

EDO page mode average power

I

CC4

supply current

CMOS standby power supply

I

CC5

current

-before-RAS

CAS refresh power

I

CC6

supply current

V

Output Voltage

Self refresh current

Shaded areas contain advance information.

V

I

OH

OL

CC7

0V ≤ Vin ≤ +5.5V

pins not under test = 0V

D

disabled,

OUT

0V ≤ V

≤ +5.5V

out

RAS, UCAS, LCAS, address cycling;

=min

t

RC

RAS = UCAS = LCAS = V

RAS cycling, UCAS

= LCAS = VIH,

= min

t

RC

RAS=UCAS=LCAS=VIL, address cycling: t

RAS=UCAS=LCAS= VCC - 0.2V – 1.0 – 1.0 – 1.0 mA

RAS, UCAS, LCAS, cycling;

= min

t

RC

I

= -5.0 mA 2.4 –2.4–2.4–V

OUT

I

= 4.2 mA – 0.4 – 0.4 – 0.4 V

OUT

RAS = UCAS = LCAS=VIL,

= OE = A0-A8 = VCC-0.2V,

WE DQ0-DQ15 = V

0.2V are open

SC

CC

= min

-0.2V,

Min Max Min Max Min Max

-10 10 -10 10 -10 10 µA

– 180 – 160 – 140 mA 1,2

IH

– 2.0 – 2.0 – 2.0 mA

– 200 – 190 – 140 mA 1

– 190 – 180 – 70 mA 1,2

– 200 – 190 – 140 mA 1

– 2.0 – 2.0 – 2.0 mA

Unit Note

4/11/01; v.1.1

Alliance Semiconductor

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AC parameters common to all waveforms

Std Symbol Parameter

t

RC

t

RP

t

RAS

t

CAS

t

RCD

t

RAD

t

RSH(R)

t

CSH

t

CRP

t

ASR

t

RAH

t

T

t

REF

t

CLZ

Shaded areas contain advance information.

Random read or write cycle time 65 –70–85–ns

precharge time 25 –25–25–ns

RAS

pulse width 30 75K 35 75K 50 75K ns

RAS

pulse width 5 –6–10–ns

CAS

to

RAS

CAS

RAS

CAS

delay time 15 20 16 24 15 35 ns 6

CAS

to column address delay time 10 14 11 17 15 25 ns 7

to

hold time (read cycle) 10 –10–10–ns

RAS

to

hold time 30 –35–50–ns

CAS

to

precharge time 5 –5–5–ns

RAS

Row address setup time 0 –0–0–ns

Row address hold time 5 –6–9–ns

Transition time (rise and fall) 1.5 50 1.5 50 3 50 ns 4,5

Refresh period – 8–8–8ms3

to output in low Z 0 –0–3–ns8

CAS

®

-30 -35 -50

Min Max Min Max Min Max

AS4C256K16E0

Unit Notes

Read cycle

Std Symbol Parameter

t

RAC

t

CAC

t

AA

t

AR(R)

t

RCS

t

RCH

tRRH

t

RAL

t

CPN

t

OFF

Shaded areas contain advance information.

Access time from

RAS

CAS

Access time from address – 16 – 18 – 25 ns 7,13

Column add hold from

Read command setup time 0 –0–0–ns

Read command hold time to

Column address to

precharge time 3 –4–5–ns

CAS

Output buffer turn-off time 0 80808ns8,10

-30 -35 -50

Min Max Min Max Min Max

– 30 – 35 – 50 ns 6

– 10 – 10 – 10 ns 6,13

RAS

CAS

RAS

Lead time 16 –18–25–ns

RAS

26 –28–30–ns

0 –0–0–ns9

Unit Notes

4/11/01; v.1.1

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AS4C256K16E0

®

Write cycle

Std Symbol Parameter

t

ASC

t

CAH

t

AW R

t

WCS

t

WCH

t

WCR

t

Write command pulse width 5 –5–9–ns

WP

t

RW L

t

CWL

Data-in setup time 0 –0–0–ns 12

t

DS

t

Data-in hold time 5 –5–9–ns 12

DH

t

DHR

Shaded areas contain advance information.

Column address setup time

Column address hold time 5 –5–9–ns

Column address hold time to

RAS

Write command setup time 0 –0–0–ns 11

Write command hold time 5 –5–9–ns 11

Write command hold time to

Write command to

Data-in hold time to

RAS

CAS

RAS

lead time 10 –11–12–ns

-30 -35 -50

Min Max Min Max Min Max

Unit Notes

0 –0–0–ns

26 –28–30–ns

Read-modify-write cycle

Std Symbol Parameter

t

RW C

t

RW D

t

CWD

Column address to WE delay time 32 –35–40–ns 11

t

AW D

t

RSH(W)

t

CAS(W)

Shaded areas contain advance information.

Read-write cycle time

RAS

CAS

to WE delay time 50 –54–60–ns 11

to WE delay time 26 –28–30–ns 11

to

hold time (write) 10 –10–12–ns

RAS

pulse width (write) 15 –15–15–ns

-30 -35 -50

Min Max Min Max Min Max

100 – 105 – 120 – ns

Unit Notes

4/11/01; v.1.1

Alliance Semiconductor

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®

EDO page mode cycle

Std Symbol Parameter

t

PC

t

Access time from

CAP

t

CP

t

EDO page mode RMW cycle 56 –58–60–ns

PCM

t

CRW

t

RASP

Shaded areas contain advance information.

Read or write cycle time

precharge – 19 – 21 – 23 ns 13

CAS

precharge time 3 –4–5–ns

CAS

Page mode

pulse width 30 75K 35 75K 50 75K ns

RAS

pulse width (RMW) 44 –46–50–ns

CAS

-30 -35 -50

Min Max Min Max Min Max

12 –14–25–ns 14

Refresh cycle

Std Symbol

t

CSR

t

CHR

t

RAS precharge to

RPC

t

CPT

Shaded areas contain advance information.

Parameter

CAS setup time (CAS-before-RAS)

hold time (

CAS

precharge time

CAS

(

-before-RAS counter test)

CAS

-before-RAS) 7 – 8 – 10 – ns 3

hold time 0 – 0 – 0 – ns

-30 -35 -50

10 – 10 – 10 – ns 3

8 – 8 – 8 – ns

AS4C256K16E0

Unit Notes

Unit NotesMin Max Min Max Min Max

Output enable

Std Symbol Parameter

t

ROH

t

OEA

t

OED

t

OEZ

t

OEH

Shaded areas contain advance information.

RAS hold time referenced to OE

access time – 10 – 10 – 10 ns

OE

to data delay 5 –5–8–ns

OE

Output buffer turnoff delay from

command hold time 8 –8–8–ns

OE

Self refresh cycle

Std Symbol Parameter

t

RASS

t

RPS

t

CHS

Shaded areas contain advance information.

RAS pulse width (CBR self refresh)

RAS precharge time (CBR self refresh)

hold time

CAS

(CBR self refresh)

OE

-30 -35 -50

Min Max Min Max Min Max

Unit Notes

5 –5–5–ns

– 8–8–8ns 8

-30 -35 -50

Min Max Min Max Min Max

Unit Notes

100K – 100K – 100K – ns

85 –85 –85–ns

30 –30 –30–ns

4/11/01; v.1.1

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®

Notes

1I

, I

CC1

2I

CC1

and I

, and I

CC3

CC4

depend on output loading. Specified values are obtained with the output open.

CC4

3 An initial pause of 200 µs is required after power-up followed by any 8 RAS

refresh counter, a minimum of 8 CAS extended periods of bias without clocks (greater than 8 ms).

4 AC Characteristics assume t

≤

VCC.

5V

(min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL.

IH

6 Operation within the t

specified t

(max) limit, then access time is controlled exclusively by t

RCD

7 Operation within the t

specified t

(max) limit, then access time is controlled exclusively by tAA.

RAD

8 Assumes three state test load (5 pF and a 380 Ω Thevenin equivalent).

9Either t

10 t

OFF

11 t

WCS

(min) and t

≥

or t

RCH

RRH

(max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels.

, t

WCH

RW D

≥ tWH (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the cycle. If t

RW D

WH

(min), t

t

If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate.

12 These parameters are referenced to CAS

13 Access time is determined by the longest of t

14 t

≥ tCP to achieve tPC (min) and t

ASC

15 These parameters are sampled and not 100% tested.

depend on cycle rate.

CC6

-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after

= 5 ns. All AC parameters are measured with a load equivalent to two TTL loads and 60 pF, VIL(min) ≥ GND and VIH (max)

T

(max) limit insures that t

RCD

(max) limit insures that t

RAD

must be satisfied for a read cycle.

, t

CWD

≥ t

and t

are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only. If tWS ≥ tWS

AW D

(min) and t

CWD

AW D

leading edge in early write cycles and to WE leading edge in read-write cycles.

(max) values.

CAP

cycles before proper device operation is achieved. In the case of an internal

(max) can be met. t

RAC

(max) can be met. t

RAC

≥ t

(min), the cycle is a read-write cycle and the data out will contain data read from the selected cell.

AW D

or t

CAA

CAC

CAP

.

(max) is specified as a reference point only. If t

RCD

.

CAC

(max) is specified as a reference point only. If t

RAD

AS4C256K16E0

is greater than the

RCD

is greater than the

RAD

RW D

Key to switching waveform

Undefined/don’t care Falling inputRising input

Read cycle waveform

RAS

t

CRP

UCAS, LCAS

t

ASR

Address

WE

OE

I/O

Row Address

t

RAH

t

RAD

t

RCD

t

AR

RAC

t

RAS

t

CSH

t

ASC

t

RCS

Col Address

t

CLZ

t

RAL

t

RC

t

RRH

t

OEZ

t

RP

t

RCH

t

OFF

t

RSH

t

CAH

t

CAS

t

ROH

t

AA

t

OEA

t

CAC

Data Out

4/11/01; v.1.1

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Upper byte read cycle waveform

RAS

t

CRP

UCAS

t

CRP

LCAS

t

RAH

t

ASR

Address

WE

OE

Upper I/O

Lower I/O

Row Column

t

RAD

t

ASC

t

RCD

t

RCS

t

RAC

AS4C256K16E0

®

t

RAL

t

CAC

t

CAS

t

RC

t

CAH

RSH

t

ROH

t

OEA

Data Out

t

OEZ

RRH

t

RP

t

CRP

t

RCH

t

OFF

t

RAS

t

CSH

t

AA

t

CLZ

Lower byte read cycle waveform

RAS

t

CRP

LCAS

UCAS

Address

WE

OE

Upper I/O

Lower I/O

t

ASR

t

CRP

t

RAH

Row Column

t

RAD

t

RCD

t

RCS

t

CSH

RAC

t

CLZ

t

ASC

t

RAS

t

RAL

t

CAC

t

CAS

t

RC

CAH

t

RSH

t

ROH

t

OEA

t

OEZ

RRH

t

RP

t

CRP

t

RCH

t

OFF

t

AA

Data Out

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Early write cycle waveform

RAS

t

CRP

UCAS, LCAS

t

ASR

Address

WE

Row Address

t

RAD

t

RAH

t

RCD

t

WCS

t

AWR

t

CSH

ASC

t

RAS

®

t

CAH

Col Address

t

WCR

t

CWL

AS4C256K16E0

t

RC

t

RAL

RWL

t

CAS

t

RSH

t

WP

t

WCH

t

RP

OE

I/O

Upper byte early write cycle waveform

RAS

Address

UCAS

LCAS

WE

OE

Upper I/O

Lower I/O

t

ASR

t

RAH

Row Address Column Address

t

CRP

t

RAD

t

ASC

t

RCD

t

AWR

t

WCS

t

DHR

t

CSH

t

DS

t

DHR

t

DS

WCR

t

RAS

t

RAL

t

CWL

Data In

t

RC

t

RWL

t

WP

t

DH

t

DH

t

CAH

CAS

t

RSH

t

WCH

t

RPC

t

RP

t

CRP

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Lower byte early write cycle waveform

RAS

t

RAD

RAH

Address

UCAS

LCAS

WE

OE

Upper I/O

Lower I/O

t

ASR

Row Address Column Address

t

CRP

t

CRP

t

RCD

t

AWR

t

WCS

t

DHR

t

ASC

DS

t

CSH

t

WCR

t

RAS

t

RAL

t

Data In

®

CWL

t

DH

t

WP

AS4C256K16E0

RC

t

RWL

t

CAH

t

WCH

RSH

t

CAS

t

RPC

t

RP

t

CRP

Write cycle waveform

RAS

UCAS, LCAS

Address

WE

OE

I/O

t

CRP

t

ASR

Row Address

t

RAH

t

RAD

t

RCD

t

DHR

t

OED

t

AWR

t

CSH

t

ASC

Col Address

RAS

t

WCR

t

CAH

t

RC

t

CAS

t

RAL

t

OEH

t

DS

Data In

t

RSH

CWL

DH

t

RWL

(OE controlled)

t

RP

t

WP

4/11/01; v.1.1

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AS4C256K16E0

®

Upper byte write cycle waveform

RAS

Address

UCAS

LCAS

WE

OE

Upper I/O

Lower I/O

t

ASR

Row Address Column Address

t

CRP

t

CRP

t

RAH

t

RAD

t

RCD

t

AWR

t

CSH

ASC

t

RAS

(OE controlled)

t

RC

t

RAL

t

RSH

t

CAH

t

CAS

t

CWL

t

DS

t

DH

t

RWL

OEH

t

WP

Data In

t

OED

t

RPC

RP

t

CRP

Lower byte write cycle waveform

RAS

t

Address

LCAS

UCAS

WE

OE

Upper I/O

Lower I/O

ASR

Row Address Column A ddre s s

t

CRP

t

CRP

t

RAH

t

RAD

t

RCD

t

AWR

t

ACS

CSH

t

RAS

(OE controlled)

t

RC

t

RAL

t

CAH

t

CAS

t

RSH

t

CWL

t

RWL

t

WP

t

OEH

t

DS

t

DH

Data In

t

RP

RPC

t

CRP

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Read-modify-write cycle waveform

RAS

t

CRP

UCAS,

LCAS

t

RAD

t

RAH

Address

WE

OE

I/O

t

ASR

Row Address Col A ddre s s

t

RCD

t

RCS

RAC

AS4C256K16E0

®

t

CAC

t

OEZ

t

RAL

RWC

t

CWD

t

CAS

t

OED

RSH

t

DS

Data InData Out

t

RWL

CWL

t

WP

tDH

t

RP

t

RAS

t

CSH

t

AR

t

ASC

t

CAH

t

RWD

t

AWD

t

OEA

t

AA

t

CLZ

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Upper byte read-modify-write cycle waveform

RAS

t

RCD

t

UCAS

CRP

t

CSH

t

RAS

t

®

CAS

t

RSH

t

RWC

AS4C256K16E0

t

RP

t

CRP

LCAS

Address

WE

OE

Upper Input

Upper Output

Lower Input

Lower Output

t

ASR

Row

t

CRP

t

RAD

t

RAH

t

ACS

Column Address

t

RWD

t

RCS

t

CLZ

t

CAC

t

AA

t

RAC

Data Out

t

AWD

t

OED

t

RAL

CAH

t

CWD

OEA

Data In

t

OEZ

t

OED

t

CWL

t

DS

t

RWL

WP

t

RPC

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Lower byte read-modify-write cycle waveform

RAS

t

CRP

UCAS

t

RAD

t

RCS

t

RAH

ACS

RCD

t

RAC

t

RWD

Data Out

t

AA

t

CAC

t

CLZ

LCAS

Address

WE

OE

Upper Input

Upper Output

Lower Input

Lower Output

t

ASR

t

CRP

Row Column Address

t

CSH

t

RAS

t

AWD

t

OED

t

RAL

CAH

t

CWD

OEA

®

t

RWC

t

CAS

t

RSH

t

OEZ

Data Out

t

CWL

t

RWL

t

WP

t

DS

Data In

t

RPC

AS4C256K16E0

t

RP

t

CRP

4/11/01; v.1.1

Alliance Semiconductor

14 of 24

EDO page mode read cycle waveform

RAS

t

RASP

AS4C256K16E0

®

t

RP

t

CRP

t

RCD

CSH

UCAS,

LCAS

Address

t

ASR

t

RAH

Row

t

RAD

t

AR

Col Address

t

RCS

WE

OE

t

RAC

I/O

EDO page mode byte read cycle waveform

RAS

UCAS

LCAS

Address

WE

OE

Lower I/O

Upper I/O

t

CRP

t

CRP

t

ASR

Row Colum n 1 Column 2 Column n

t

RAH

t

RCD

t

RAD

t

RCS

t

RAC

t

CLZ

t

CSH

t

CAC

t

CAS

t

ASC

t

RCH

t

OEA

AA

t

PC

t

CAH

Data Out 1

t

CAS

t

CP

t

ASC

Col Address

t

RCH

t

OEA

t

CLZ

t

CAC

t

AA

RCS

t

CAC

RSH

t

PC

t

CAH

t

RAL

Col Address

t

CAP

t

RCH

OEA

t

RRH

Data Out Data Out

t

RASP

t

RSH

t

CAS

t

CP

t

ASC

t

CAH

t

RCS

t

CAC

t

CLZ

t

AA

t

CAP

t

OFF

t

OEZ

t

CAS

t

OEA

Data Out 2

t

CAP

PC

AA

t

CLZ

t

CAC

t

RCH

t t

t

OFF OEZ

CP

ASC

t

RAL

t

RCS

t

OEA

t

CAH

RP

t

CRP

t

RPC

t

OFF

t

OEZ

Data Out n

4/11/01; v.1.1

Alliance Semiconductor

15 of 24

EDO page mode early write cycle waveform

t

RAH

RAS

UCAS,

LCAS

Address

WE

OE

I/O

t

ASR

t

CRP

Row address

t

RAD

t

RCD

t

CSH

t

AR

Col address Col Address Col Address

t

HDR

t

DS

Data In Data In Data In

AS4C256K16E0

®

t

RASP

t

WCH

PC

t

CAS

t

DH

t

ASC WCS

t

RWL

t

OEH

t

RAL

CAH

t

RSH

t

CWL

t

WP

t

CP

EDO page mode byte early write cycle waveform

RAS

t

RCD

RAD

DS

t

ASC

CSH

t

CWL

t

WP

t

CAS

t

CAH

t

WCH

t

DH

Data In 1

t

PC

UCAS

LCAS

Address

WE

OE

Lower I/O

Upper I/O

t

CRP

t

CRP

t

ASR

RAH

Row Column 1 Column 2 Column n

t

WCS

t

RASP

t

RSH

t

CAS

t

CP

t

DS

ASC

t

WCS

t

CWL

WP

t

WCH

t

DH

CAS

t

CAH

t

PC

t

CP

ASC

t

RAL

t

CAH

t

WCS

t

CWL

t

WCH

t

WP

t

RPC

RWL

t

RP

CRP

Data In 2

t

DS

DH

Data In n

4/11/01; v.1.1

Alliance Semiconductor

16 of 24

EDO page mode read-modify-write cycle waveform

AS4C256K16E0

®

RAS

t

PCM

t

RCD

CSH

t

CAS

UCAS,

t

RCS

t

RAH

RAD

t

RWD

t

AWD

t

CAH

t

CWD

LCAS

Address

t

ASR

Row Ad Col Ad Col AddressCol Ad

t

WE

t

OEA

t

OEZ

OE

t

RAC

t

CLZ

t

CAC

AA

I/O

Data Out

CAS-before-RAS refresh cycle waveform

t

RP

RAS

t

RASP

t

CP

t

CLZ

t

AWD

OEA

CAP

CAC

t

CAH

t

CWD

RAL

Data In

t

CAH

t

CWL

t

CWD

t

OED

t

DH

t

DS

t

CLZ

t

CAC

t

DS

Data InData In

t

RP

t

CRP

t

RWL

t

CWL

t

WP

Data OutData Out

(WE = VIH )

t

RC

t

RAS

t

RPC

t

CPN

UCAS,

LCAS

t

OFF

I/O

RAS only refresh cycle waveform

RAS

UCAS,

LCAS

Address

t

CSR

t

CRP

t

ARS

Row Address

t

RAH

t

CHR

t

RAS

(WE = OE = VIH or VIL)

t

RC

t

RPC

t

RP

4/11/01; v.1.1

Alliance Semiconductor

17 of 24

EDO page mode byte read-modify-write cycle

RAS

t

CSH

t

RCD

ASC

t

CAH

CAS

UCAS

LCAS

Address

t

CRP

t

RAD

t

RAH

ASR

RC 1 C 2

AS4C256K16E0

®

t

RASP

t

RSH

t

CAS

t

ASC

t

CAH

t

PCM

CAS

t

CP

t

CAH

ASC

t

AWD

t

RAL

t

CP

t

AWD

t

C n

t

RP

t

CRP

WE

OE

Upper Input

Upper Output

Lower Input

Lower Output

t

RCS

t

RWD

t

OED

Data In 1

t

RAC

t

AA

t

CAC

Data Out 1

t

AWD

t

CWD

t

CLZ

OEA

t

OEZ

t

OED

CWD

t

CLZ

DS

t

CAP

OEA

t

AA

t

OEZ

CAC

t

WP

t

CWL

t

WP

t

DH

DS

t

AA

t

CAC

t

CWL

t

OED

t

CLZ

t

DH

Data In 2

CWD

t

OEA

DS

RWL

t

CWL

t

DH

Data In n

t

OEZ

Data Out n

t

WP

Data Out 2

4/11/01; v.1.1

Alliance Semiconductor

18 of 24

Hidden refresh cycle (read) waveform

AS4C256K16E0

®

t

RAS

t

CRP

t

RCD

CAS

t

RCS

AR

t

ASC

Col AddressRow

Address

t

ASR

t

RAD

t

RAH

WE

OE

t

RAC

t

AA

I/O

Hidden refresh cycle (write) waveform

RAS

UCAS,

LCAS

Address

WE

I/O

t

CRP

t

ASR

t

RAH

t

RAD

t

WCS

t

RCD

ASC

t

AR

t

WCR

t

DS

t

DHR

Data In

Col AddressRow Address

t t

t

RC

CAC CLZ

t

WP

RSH

OEA

RAS

t

RWL

t

DH

RAL

Data Out

t

RC

t

RSH

t

CAH

t

WCH

t

RRH

t

OFF

RC

t

CRP

t

PR

t

PR

t

CHR

t

RAS

t

OEZ

t

RP

OE

4/11/01; v.1.1

Alliance Semiconductor

19 of 24

CAS-before-RAS refresh counter test cycle waveform

RAS

t

CPT

t

RCS

Read CycleWrite CycleRead-Write Cycle

UCAS,

LCAS

Address

I/O

WE

OE

WE

I/O

t

CSR

t

CHR

®

t

RAS

t

CAH

Col Address

t

AA

t

CLZ

t

WP

t

WCS

t

DS

Data In

CAC

t

DH

OEA

t

WCH

t

CWL

t

CAS

t

RAL

Data Out

t

RWL

t

RSH

ROH

AS4C256K16E0

t

RP

t

OFF

t

RRH

t

RCH

OE

WE

OE

I/O

t

CLZ

t

RCS

t

CWD

t

AWD

t

OEA

t

AA

t

CAC

t

OEZ

t

OED

t

WP

t

CWL

t

DH

t

DS

Data Out Data In

4/11/01; v.1.1

Alliance Semiconductor

20 of 24

CAS-before-RAS self refresh cycle

AS4C256K16E0

®

t

RP

RAS

t

RPC

t

CP

UCAS,

LCAS

t

CEZ

DQ

Typical DC and AC characteristics

Normalized access time t

vs. supply voltage V

1.5

1.4 Ta = 25°C

1.3

1.2

1.1

1.0

Normalized access time

0.9

RAC

CC

t

CSR

Normaliz ed access tim e t

vs. ambient temperature T

1.5

1.4

1.3

1.2

1.1

1.0

Normalized access time

0.9

t

RASS

RAC

t

RPS

t

RPC

t

CHS

Typical access time t

a

100

vs. load capacitance C

RAC

L

90 80 70 60 50

Typical access time

40

0.8

4.0 5.5 Supply voltage (V)

Typical supply current I

vs. supply voltage V

70 60 50 40 30 20

Supply current (mA)

10

0.0

4.0 5.5 Supply voltage (V)

5.04.5

6.0

–55 80

35–10

125

Ambient temperature (°C)

0.8

CC

Typical supply current I

vs. ambient temper a t ure T

70

CC

a

60 50 40 30 20

Supply current (mA)

10

0.0

5.04.5

6.0

–55 80

35–10

125

Ambient temperature (°C)

30

50 200 250150100

Load capacitance (pF)

Typical power-on current I

vs. cycle rate 1/t

35

PO

RC

30 25 20 15 10

Power-on current (mA)

5

0.0 28

64

10

Cycle rate (MHz)

4/11/01; v.1.1

Alliance Semiconductor

21 of 24

AS4C256K16E0

®

Typical refresh current I

vs. supply voltage V

35

30

25

20

15

10

Refresh current (mA)

5

0

4.0 5.5

5.04.5

Supply voltage (V)

Typical TTL stand-by current I

vs. ambient temperature T

3.5

3.0

2.5

2.0

1.5

CC

CC3

a

6.0

CC2

Typical refresh current I vs. Ambient temperature Ta vs. supply voltage V

35

30

25

20

15

10

Refresh current (mA)

5

0

0.0 60

Ambient temperature (°C)

Typical output sink current I

vs. output volt a ge V

70 60 50 40 30

CC3

Typical TTL stand-by current I

3.5

CC2

CC

3.0

2.5

2.0

1.5

1.0

Stand-by current (mA)

0.5

0

4020

80

4.0 5.5 6.05.04.5

Supply voltage (V)

OL

Typical output source current I

vs. output voltage V

70

OH

60 50 40 30

1.0

Stand-by current (mA)

0.5

0.0 060

4020

80

Ambient temperature (°C)

Typical EDO page mode current I

vs. ambient temperature T

35

CC4

a

30 25 20 15 10

5

EDO page mode cur r e nt (mA )

0.0 060

4020

80

Ambient temperature (°C)

20

Output sink current (mA)

10

0.0

0.0 1.5

1.00.5

Output voltage (V)

Typical EDO page mode current I

vs. supply voltage V

35 30 25 20 15 10

5

EDO page mode current (mA)

0.0

4.0 5.5 6.05.04.5 Supply voltage (V)

CC

2.0

CC4

20 10

Output source current (mA)

0.0

0.0 3.0 Output voltage (V)

2.01.0

4.0

4/11/01; v.1.1

Alliance Semiconductor

22 of 24

Package dimensions

44 43 42 41 40 39 38 37 36 35 32 31

44-pin TSOP II

12345678910 1314

A

1

b

e

40-pin SOJ

Pin 1

A1

B

b

AS4C256K16E0

®

1

2

e

44-pin TSOP II

Min

(mm)

Max

(mm)

0.05

0.95 1.05

11.56 11.96

40-pin SOJ

400 mil

Min Max

30 29

28 27 26 25

23

c

A1.2

H

E

e

A

b0.300.45

c 0.127 (typical)

17 18 19 20

212422

d 18.28 18.54

E 10.03 10.29

15 16

d

H

A

2

0–5°

l

e 0.80 (typical)

l0.400.60

e

D

A 0.128 0.148

E1

E2

A1 0.025 A2 1.105 1.115

B 0.026 0.032 b 0.015 0.020

c 0.007 0.013

D 1.020 1.035

E 0.370 (typical) E1 0.390 0.410 E2 0.435 0.445

Seating

Plane

c

A2

A

E

e 0.050 (typical)

Capacitance

ƒ = 1 MHz, Ta = room temperature, VCC = 5V ± 0.5V

Parameter Symbol Signals Test conditions Max Unit

Input capacitance

I/O capacitance C

C

IN1

C

IN2

I/O

A0 to A8 Vin = 0V 5 pF

RAS, UCAS, LCAS, WE, OE

I/O0 to I/O15 Vin = V

Vin = 0V 7 pF

= 0V 7 pF

out

Ordering codes

Package \ Access time

Plastic SOJ, 400 mil, 40-pin

TSOP II, 400 mil, 40/44-pin

Shaded areas contain advance information.

30 ns 35 ns 50 ns

AS4C256K16E0-30JC AS4C256K16E0-35JC AS4C256K16E0-50JC

AS4C256K16E0-50TC

Part numbering system

AS4C 256K16E0 –XX X C

DRAM prefix Device number

4/11/01; v.1.1

access time

RAS

Package: J = SOJ

Alliance Semiconductor

T = TSOP II

Commercial temperature range, 0°C to 70 °C

23 of 24

AS4C256K16E0

®

4/11/01; v.1.1

© Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered tradem arks of Alliance. All othe r brand and product names may be the trademar ks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represe nts Allianc e's best dat a and/or es timates at the time of is suance. Allian ce reserves t he right to change o r correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or war rantee to any user or customer. Alliance does not a ssume any responsibility or liability arising out of the application or use of any product described herein, a nd disclaims any express o r implied warranties related to the sale and/or use of Allian ce products including liability or war ranties related to fitness for a particular pur pose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Term s and Conditions of Sale. The purch ase of products from Alliance does not convey a license under any patent rights, copyrights, mask works ri ghts, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems wh ere a malfunc tion or failure may reas onably be expected to result in s ignificant in jury to the us er, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.

Alliance Semiconductor

24 of 24