Datasheet AS4C1M16F5-60TI, AS4C1M16F5-60TC, AS4C1M16F5-60JI, AS4C1M16F5-60JC, AS4C1M16F5-50TI Datasheet (Alliance Semiconductor Corporation)

5V 1M×16 CMOS DRAM (fast-page mode)

Features

• Organization: 1,048,576 words × 16 bits

• High speed

- 50/60 ns

- 20/25 ns fast page cycle time

- 13/17 ns

• Low power consumption

- Active: 880 mW max (AS4C1M16E0-60)

- Standby: 11 mW max, CMOS DQ

• Fast page mode

RAS

access time

CAS

access time

AS4C1M16F5

®

• 1024 refresh cycles, 16 ms refresh interval

-

RAS

-only or

• Read-modify-write

• TTL-compatible, three-state DQ

• JEDEC standard package and pinout

- 400 mil, 42-pin SOJ

- 400 mil, 44/50-pin TSOP II

• 5V power supply

• Industrial and commercial temperature available

CAS

-before-

RAS

refresh

Pin arrangement

TSOP II

1 2 3 4

3

5 6 7 8 9 10 11

15 16 17 18 19 20 21 22

23 24 25

50 49 48 47 46 45 44 43 42 41 40

36 35 34 33 32 31 30 29 28 27 26

Vcc DQ1 DQ2 DQ3

DQ4

Vcc DQ5 DQ6

DQ7

DQ8

NC NC

WE

RAS

NC NC

A2

SOJ

V

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

A0

18

A1

19 20

A3

SS

41

DQ16

40

DQ15

39

DQ14

38

DQ13

37

V

SS

36

DQ12

35

DQ11

34

DQ10

33

DQ9

32

NC

31

LCAS

30

UCAS

29

OE

28

A9

27

A8

26

A7

25

A6

24

A5

23

A4

2221Vcc

V

SS

V

42

DQ1 DQ2

DQ

DQ4

V

DQ5 DQ6

DQ7 DQ8

NC

NC NC

WE

RAS

NC NC

A0 A1 A2 A3

V

CC

Selection guide

Maximum

Maximum column address access time t

Maximum

Maximum output enable (

Minimum read or write cycle time t

Minimum fast page mode cycle time t

Maximum operating current I

Maximum CMOS standby current I

access time t

RAS

access time t

CAS

) access time t

OE

Pin designation

Pin(s) Description

V

SS

DQ16 DQ15 DQ14 DQ13 V

SS

DQ12 DQ11 DQ10 DQ9 NC

NC

LCAS UCAS OE

A9 A8 A7 A6 A5 A4 V

SS

Symbol AS4C1M16F5-50 AS4C1M16F5-60 Unit

RAC

AA

CAC

OEA

RC

PC

CC1

CC5

A0 to A9 Address inputs

RAS

Row address strobe

DQ1 to DQ16 Input/output

OE

WE

UCAS

LCAS

V

CC

V

SS

Output enable

Write enable

Column address strobe, upper byte

Column address strobe, lower byte

Power

Ground

50 60 ns

25 30 ns

13 17 ns

13 15 ns

84 104 ns

20 25 ns

170 160 mA

2.0 2.0 mA

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P. 1 of 21

AS4C1M16F5

®

Functional description

The AS4C1M16F5 is a high performance 16-megabit CMOS Dynamic Random Access Memory (DRAM) organized as 1,048,576 words × 16 bits. The AS4C1M16F5 is fabricated using advanced CMOS technology and innovative design techniques resulting in high speed, extremely low power and wide operating margins at component and system levels. The Alliance 16Mb DRAM family is optimized for use as main memory in personal and portable PCs, workstations, and multimedia and router switch applications.

The AS4C1M16F5 features high speed page mode operation where read and write operations within a single row (or page) can be executed at very high speed (15 ns from addresses are alternately latched into input buffers using the falling edge of to make the column address latch transparent, enabling application of column addresses prior to AS4C1M16F5 provides dual

UCAS

and

for independent byte control of read and write access.

LCAS

Refresh on the 1024 address combinations of A0 to A9 must be performed every 16 ms using:

•

-only refresh:

RAS

• Hidden refresh:

•

-before-

CAS

Outputs are high-impedence (

• Normal read or write cycles refresh the row being accessed.

RAS

is asserted while

RAS

is held low while

xCAS

refresh (CBR): At least one

OE

xCAS

RAS

and WE are don't care).

is held high. Each of the 1024 rows must be strobed. Outputs remain high impedence.

is toggled. Outputs remain low impedence with previous valid data.

is asserted prior to

xCAS

The AS4C1M16F5 is available in the standard 42-pin plastic SOJ and the 44/50-pin TSOP II packages, respectively. It operates with a single power supply of 5V ± 0.5V. The device provides TTL compatible inputs and outputs.

)by toggling column addresses within that row. Row and column

XCAS

and

RAS

. Refresh address is generated internally.

RAS

inputs respectively. Also,

xCAS

assertion. The

xCAS

RAS

is used

Logic block diagram

Data

DQ

buffers

Substrate bias

DQ1 to DQ16

OE

generator

RAS

UCAS

LCAS

WE

RAS clock generator

CAS clock generator

WE clock generator

V

GND

CC

Refresh

controller

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9

Address buffers

Row decoder

Column decoder

Sense amp

1024 × 1024 × 16

Array

(16,777,216)

Recommended operating conditions

Parameter Symbol Min Nominal Max Unit

Supply voltage

AS4C1M16F5 V

CC

GND 0.0 0.0 0.0 V

Input voltage

AS4C1M16F5 V

Ambient operating temperature

Commercial

Industrial -40 – 85

†

VIL min -3.0V for pulse widths less than 5 ns.

Recommended operating conditions apply throughout this document unlesss otherwise specified.

IH

V

IL

T

A

4.5 5.0 5.5 V

2.4 – V

†

–0.5

–0.8V

CC

0–70

V

°C

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P. 2 of 21

AS4C1M16F5

®

Absolute maximum ratings

Parameter Symbol Min Max Unit

Input voltage V

Input voltage (DQs) V

Power supply voltage V

Storage temperature (plastic) T

Soldering temperature × time T

Power dissipation P

Short circuit output current I

DC electrical characteristics

Parameter Symbol Test conditions

Input leakage current I

Output leakage current I

Operating power supply current

TTL standby power supply current

Ave r age p ower sup p ly current,

refresh mode

RAS

or CBR

Fast page mode average power supply current

CMOS standby power supply current

Output voltage

CAS

before

RAS

refresh

current

IL

OL

I

CC1

I

CC2

I

CC3

I

CC4

I

CC5

V

OH

V

OL

ICC6

0V ≤ Vin ≤ +5.5V,

Pins not under test = 0V

D

disabled, 0V ≤ V

OUT

RAS, UCAS, LCAS

t

=min

RC

=

RAS

UCAS

cycling,

RAS

t

= min of

RC

= VIL,

RAS

address cycling: t

=

RAS

UCAS

I

= -5.0 mA 2.4 – 2.4 – V

OUT

I

= 4.2 mA – 0.4 – 0.4 V

OUT

RAS, UCAS

, Address cycling;

=

≥ V

LCAS

=

UCAS

low after

RAS

or

UCAS

=

or

LCAS,

= min

PC

= VCC - 0.2V – 2.0 – 2.0 mA

LCAS

cycling, tRC = min – 170 – 160 mA

LCAS

in

DQ

CC

STG

SOLDER

D

out

≤ +5.5V -5+5-5+5µA

out

IH

≥ V

IH

XCAS

-1.0 +7.0 V

-1.0 VCC + 0.5 V

-1.0 +7.0 V

-55 +150 °C

–260 × 10

o

C × sec

–1W

–50mA

-50 -60

Unit NotesMinMaxMinMax

-5 +5 -5 +5 µA

– 170 – 160 mA 1,2

– 2.5 – 2.5 mA

,

low.

– 170 – 160 mA 1

– 120 – 110 mA 1, 2

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P. 3 of 21

AS4C1M16F5

®

AC parameters common to all waveforms

-50 -60

Symbol Parameter

t

RC

t

RP

t

RAS

t

CAS

t

RCD

t

RAD

t

RSH

t

CSH

t

CRP

t

ASR

t

RAH

t

T

t

REF

t

CP

t

RAL

Column address setup time 0 – 0 – ns

t

ASC

Column address hold time 8 10 – ns

t

CAH

Random read or write cycle time 84 – 104 – ns

precharge time 30 – 40 – ns

RAS

pulse width 50 10K 60 10K ns

RAS

pulse width 8 10K 10 10K ns

CAS

to

RAS

CAS

RAS

CAS

delay time 15 35 15 43 ns 6

CAS

to column address delay time 12 25 12 30 ns 7

to

hold time 10 – 10 – ns

RAS

to

hold time 40 – 50 – ns

CAS

to

precharge time 5 – 5 – ns

RAS

Row address setup time 0 – 0 – ns

Row address hold time 8 – 10 – ns

Transition time (rise and fall) 1 50 1 50 ns 4,5

Refresh period – 16 – 16 ms 3

CAS precharge time 8 – 10 – ns

Column address to

lead time 25 – 30 – ns

RAS

Unit NotesMin Max Min Max

Read cycle

Symbol Parameter

t

RAC

t

CAC

t

AA

t

RCS

t

RCH

tRRH

Access time from

Access time from address – 25 – 30 ns 7,13

Read command setup time 0 – 0 – ns

Read command hold time to

RAS

CAS

RAS

-50 -60

Unit NotesMin Max Min Max

– 50 – 60 ns 6

– 13 – 17 ns 6,13

0–0–ns9

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P. 4 of 21

AS4C1M16F5

®

Write cycle

-50 -60

Symbol Parameter

t

Write command setup time 0 – 0 – ns 11

WCS

Write command hold time 10 – 10 – ns 11

t

WCH

Write command pulse width 10 – 10 – ns

t

WP

t

Write command to

RW L

Write command to

t

CWL

Data-in setup time 0 – 0 – ns 12

t

DS

t

Data-in hold time 8 – 10 – ns 12

DH

lead time 10 – 10 – ns

RAS

lead time 8 – 10 – ns

CAS

Read-modify-write cycle

-50 -60

Symbol Parameter

Read-write cycle time 113 – 135 – ns

t

RW C

t

RW D

t

CWD

Column address to WE delay time 42 – 47 – ns 11

t

AW D

to WE delay time 67 – 77 – ns 11

RAS

to WE delay time 32 – 35 – ns 11

CAS

Unit NotesMin Max Min Max

Refresh cycle

Symbol Parameter

t

CSR

t

CHR

RAS precharge to

t

RPC

t

CPT

setup time (

CAS

hold time (

CAS

precharge time

CAS

(CBR counter test)

-50 -60

Unit NotesMin Max Min Max

-before-

CAS

-before-RAS)8–10–ns3

CAS

hold time 0–0–ns

CAS

)5–5–ns3

RAS

10 10 – ns

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P. 5 of 21

AS4C1M16F5

Fast page mode cycle

Symbol Parameter

t

CPA

t

RASP

t

PC

t

CP

t

PCM

t

CRW

Output enable

Symbol Parameter

t

CLZ

t

ROH

t

OEA

t

OED

t

OEZ

t

OEH

t

OLZ

t

OFF

Access time from

pulse width 50 100K 60 100K ns

RAS

Read-write cycle time 30 – 35 – ns

precharge time (fast page) 10 – 10 – ns

CAS

Fast page mode RMW cycle 80 – 85 – ns

Page mode

to output in Low Z 0 – 0 – ns 8

CAS

hold time referenced to

RAS

access time – 13 – 15 ns

OE

to data delay 13 – 15 – ns

OE

Output buffer turnoff delay from

command hold time 10 – 10 – ns

OE

to output in Low Z 0 – 0 – ns

OE

Output buffer turn-off time 0 13 0 15 ns 8,10

®

-50 -60

precharge – 28 – 35 ns 13

CAS

pulse width (RMW) 54 – 60 – ns

CAS

-50 -60

OE

8–10–ns

013015ns8

Unit NotesMin Max Min Max

Unit NotesMinMaxMinMax

4/11/01; v.0.9.1 Alliance Semiconductor

P. 6 of 21

®

Notes

1I

, I

, and I

CC1

CC3

and I

2I

3 An initial pause of 200 µs is required after power-up followed by any 8 RAS

refresh counter, a minimum of 8 CAS extended periods of bias without clocks (greater than 8 ms).

4 AC Characteristics assume t

≤

VCC.

(max)

5V

(min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL.

IH

6 Operation within the t

specified t

7 Operation within the t

specified t

8 Assumes three state test load (5 pF and a 380

9Either t

10 t

11 t

RCH

(max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. t

OFF

rising edge of RAS

, t

WCS

WCH

≥ tWS (min) and tWH ≥ tWH (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the

If t

WS

cycle. If t

RW D

selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate.

12 These parameters are referenced to CAS

13 Access time is determined by the longest of t

14 t

≥ tCP to achieve tPC (min) and t

ASC

15 These parameters are sampled and not 100% tested.

16 These characteristics apply to AS4C1M16F5 5V devices.

are dependent on frequency.

CC4

depend on output loading. Specified values are obtained with the output open.

CC4

cycles before proper device operation is achieved. In the case of an internal

-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after

= 2 ns. All AC parameters are measured with a load equivalent to two TTL loads and 100 pF, VIL(min) ≥ GND and VIH

T

(max) limit insures that t

RCD

(max) limit, then access time is controlled exclusively by t

RCD

(max) limit, then access time is controlled exclusively by tAA.

RAD

(max) limit insures that t

RAD

Ω

or t

must be satisfied for a read cycle.

RRH

(max) can be met. t

RAC

(max) can be met. t

RAC

Thevenin equivalent).

(max) is specified as a reference point only. If t

RCD

.

CAC

(max) is specified as a reference point only. If t

RAD

or CAS, whichever occurs last.

, t

RW D

≥ t

CWD

RW D

and t

(min), t

are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only.

AW D

≥ t

CWD

(min) and t

CWD

AWD

≥ t

(min), the cycle is a read-write cycle and the data out will contain data read from the

AW D

leading edge in early write cycles and to WE leading edge in read-write cycles.

or t

CAC

or t

CPA

CAA

(max) values.

CPA

AS4C1M16F5

is greater than the

RCD

is greater than the

RAD

is referenced from

OFF

AC test conditions

- Access times are measured with output reference levels

of V

= 2.4V and VOL = 0.4V,

OH

V

= 2.4V and VIL = 0.8V

IH

- Input rise and fall times: 2 ns

D

out

100 pF* R2 = 295

Figure A: Equivalent output load

Key to switching waveforms

+5V

R1 = 828

GND

Ω Ω

*including scope

and jig capacitance

Undefined output/don’t careFalling inputRising input

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P. 7 of 21

AS4C1M16F5

Read waveform

RAS

UCAS,

LCAS

Address

WE

OE

DQ

t

CRP

t

ASR

Row address

t

RAH

®

t

CLZ

RC

t

ROH

t

RRH

REZ

t

RP

t

RCH

t

WEZ

t

OEZ

t

(see note 11)

OFF

t

RSH

t

CAH

t

CAS

t

RAL

t

ROH

t

AA

t

OEA

t

CAC

t

OLZ

Data out

t

RAS

t

RCD

t

ASC

t

RAD

CSH

t

RCS

Column address

t

RAC

t

Upper byte read waveform

RAS

t

CRP

UCAS

t

CRP

LCAS

t

ASR

Address

WE

OE

Upper DQ

Lower DQ

t

RAS

t

RCD t

t

RAH

t

RAD

t

ASC

Row

t

RCS

Column

t

RAC

t

CSH

t

AA

t

CLZ

RC

RSH

t

CAS

t

RAL

t

CAH

t

ROH

t

OEA

t

OLZ

t

CAC

t

RP

t

CRP

t

RPC

t

RCH

t

RRH

t

WEZ

t

REZ

t

OEZ

t

OFF

Data out

4/11/01; v.0.9.1 Alliance Semiconductor

P. 8 of 21

Lower byte read waveform

RAS

LCAS

UCAS

t

Address

WE

OE

Upper DQ

Lower DQ

ASR

AS4C1M16F5

®

t

RAS

t

RCD

t

CRP

t

CRP

t

RAH

t

RAD

Row

t

CSH

t

ASC

Column

t

RCS

t

RAC

t

AA

t

CLZ

RC

t

RSH

t

CAS

t

RAL

t

CAH

t

ROH

t

OEA

t

OLZ

t

CAC

t

RP

t

CRP

t

RPC

t

RCH

t

RRH

t

WEZ

t

REZ

t

OEZ

t

OFF

Data out

Early write waveform

RAS

t

CRP

UCAS

,

LCAS

t

ASR

Address

WE

OE

DQ

Row address

t

ASC

t

CAH

RC

t

RSH

t

CAS

t

RAL

t

RP

t

RAS

t

CSH

t

RCD

t

RAD

t

RAH

Column address

t

CWL

t

RW L

t

WCS

t

DS

WP

t

WCH

t

DH

Data in

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P. 9 of 21

AS4C1M16F5

Upper byte early write waveform

RAS

t

ASR

Address

UCAS

LCAS

WE

OE

t

Row address

t

CRP

t

CRP

RAH

®

t

RAL

CWL

RC

t

CAH

t

RSH

t

CAS

t

WCH

t

RWL

t

WP

t

RP

t

CRP

t

RPC

t

RAS

t

RAD

Column address

t

ASC

t

RCD

t

CSH

t

WCS

Upper DQ

Lower DQ

Lower byte early write waveform

RAS

t

ASR

Address

UCAS

LCAS

WE

OE

Upper DQ

Row address Column address

t

CRP

t

CRP

t

RAH

t

RAD

t

DS

t

DH

Data in

t

CWL

RC

t

CAH

t

RWL

t

WCH

t

WP

t

CAS

t

RSH

t

RPC

t

RP

t

CRP

t

RAS

t

RAL

t

ASC

t

RCD

t

WCS

t

CSH

t

DS

Lower DQ

Data in

4/11/01; v.0.9.1 Alliance Semiconductor

t

DH

P. 10 of 21

Write waveform

RAS

UCAS,

LCAS

AS4C1M16F5

®

OE

controlled

t

RAS

t

CSH

t

CRP

t

RCD

RC

t

RSH

t

CAS

t

RAL

t

RP

t

ASR

Address

Row address

WE

OE

DQ

Upper byte write waveform

RAS

t

ASR

Address

UCAS

LCAS

WE

OE

Upper DQ

Lower DQ

Row address Column address

t

CRP

t

CRP

t

RAH

t

RAD

t

RAH

t

ASC

t

CAH

Column address

t

RWL

t

CWL

t

WP

t

OEH

t

OED

DS

t

DH

Data in

OE

controlled

t

RAS

t

RAD

t

RCD

t

ASC

CSH

t

DS

RC

t

RAL

t

RSH

t

CAH

t

CWL

t

OEH

t

CAS

t

RWL

WP

t

DH

t

RP

t

CRP

t

RPC

Data in

t

OED

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P. 11 of 21

AS4C1M16F5

Lower byte write waveform

RAS

t

ASR

Address

LCAS

UCAS

WE

OE

Upper DQ

Lower DQ

t

RAH

Row address Column address

t

CRP

®

OE

controlled

t

RAL

Data in

RC

t

CAH

t

CAS

t

RSH

t

CWL

t

RWL

t

WP

t

OEH

t

DH

t

RPC

t

RP

t

CRP

t

RAS

t

RAD

t

RCD

t

ACS

t

CRP

t

CSH

t

DS

Read-modify-write waveform

RAS

t

CRP

UCAS,

LCAS

t

ASR

Address

WE

OE

DQ

Row address Column address

t

RAS

t

RCD

t

AR

t

RAD

t

RAH

t

RCS

t

RAC

t

ASC

t

RWD

t

OEA

t

AA

RW C

t

CAS

t

CWD

RSH

t

OED

t

CWL

t

DS

t

DH

t

CSH

t

RAL

t

CAH

t

AW D

t

OEZ

t

CAC

t

CLZ

t

RP

t

RW L

WP

Data inData out

t

OLZ

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P. 12 of 21

Upper byte read-modify-write waveform

RAS

t

RCD

t

RAH

Column address

t

RCS

t

RAC

UCAS

LCAS

Address

WE

OE

Upper input

Upper output

Lower input

Lower output

t

CRP

t

CRP

t

ASR

RAD

t

Row

t

CAC

CLZ

t

AA

t

ACS

t

RW D

t

OLZ

Data out

AS4C1M16F5

®

t

RAS

t

CSH

t

CAH

t

AWD

t

OED

RW C

t

CAS

t

RSH

t

RAL

t

CWL

t

CWD

t

OEA

t

DS

RW L

t

WP

DH

t

RPC

CRP

t

RP

Data in

t

OEZ

t

OED

Lower byte read-modify-write waveform

RAS

UCAS

LCAS

Address

WE

OE

Upper input

Upper output

Lower input

Lower output

t

ASR

t

CRP

t

RAH

RCD

t

ACS

t

RAD

t

CRP

Row Column address

t

RCS

t

RAC

t

RAS

t

CSH

t

CAH

t

RW D

t

AW D

t

OLZ

t

OED

t

AA

t

CAC

t

CLZ

RWC

t

CAS

t

RSH

t

RAL

t

CWL

t

CWD

OEA

t

OED

RWL

t

WP

t

DH

t

DS

t

RPC

t

RP

t

CRP

Data in

t

OEZ

Data out

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P. 13 of 21

AS4C1M16F5

Fast page mode read waveform

RAS

t

RASP

®

t

RP

t

CRP

t

RCD

CAS

t

AR

t

Address

t

ASR

Row

t

RAD

RAH

WE

OE

t

RAC

I/O

Fast page mode byte write waveform

RAS

t

CSH

t

RWD

t

CWD

t

AWD

t

OEA

t

AA

t

CLZ

t

CAC

Data out

CAS

Address

WE

I/O

t

RCD

t

RAD

t

ASR

t

RAH

Row Column ColumnColumn

t

RCS

OE

t

RAC

t

CSH

t

CAS

Column Column

t

RCS

t

RCH

t

OEA

t

CLZ

t

AA

Data out Data out Data out

t

PCM

t

CAH

CAS

t

OEZ

t

DS

t

CWL

t

DH

t

RSH

t

CP

t

ASC

t

PC

t

RAL

t

CAH

Column

t

Data in

RRH

t

RP

t

CRP

t

RWL

t

CWL

t

WP

t

RCS

t

OEZ

t

OFF

t

RASP

CP

t

CAH

t

CWD

t

OED

t

DS

t

CLZ

t

CAC

t

CAP

t

RCH

t

OEA

t

CAC

t

RAL

t

CAH

t

CWD

t

AWD

t

OEA

t

CAP

CLZ

t

CAC

Data inData in

Data out

4/11/01; v.0.9.1 Alliance Semiconductor

P. 14 of 21

Fast page mode early write waveform

t

RAH

RAS

CAS

Address

WE

OE

I/O

t

CRP

t

ASR

t

RCD

t

CSH

t

RAD

AR

Row Column Column Column

t

HDR

t

DS

®

t

RASP

t

WCH

t

PC

OED

t

CAS

t

DH

t

ASC

WCS

Data In Data in Data in

t

RW L

t

CP

t

RAL

t

CWL

t

WP

t

AS4C1M16F5

t

CAH

t

RSH

OEH

CAS before RAS refresh waveform

t

RP

RAS

t

RPC

UCAS,

LCAS

DQ

RAS only refresh waveform

RAS

UCAS,

LCAS

Address

t

ASR

t

CP

t

CSR

Row address

WE

= VIH

t

RC

t

CHR

t

RAS

OPEN

WE

= OE = VIH or V

t

RAS

t

CRP

t

RAH

RC

t

RP

t

RPC

IL

4/11/01; v.0.9.1 Alliance Semiconductor

P. 15 of 21

AS4C1M16F5

Hidden refresh waveform (read)

®

t

RAS

t

CRP

t

RCD

CAS

t

RAD

t

ASR

RAH

AR

Address

t

RCS

WE

OE

t

RAC

t

AA

DQ

Hidden refresh waveform (write)

RAS

UCAS,

LCAS

Address

WE

DQ

t

CRP

t

ASR

t

RAH

t

RAD

t

WCS

t

RCD

t

AR

t

ASC

t

WCR

t

DS

Col addressRow

t

ASC

DHR

t

RC

t

RSH

t

CAH

t

OEA

t

RP

t

CHR

t

RRH

t

RAS

t

CAC

t

CLZ

t

OFF

OEZ

t

RC

t

CRP

t

RP

Data out

t

RAS

RC

t

RSH

t

RAL

t

CAH

t

RP

t

CHR

Col addressRow address

t

RWL

t

WP

t

WCH

t

DH

Data in

OE

4/11/01; v.0.9.1 Alliance Semiconductor

P. 16 of 21

CAS before RAS refresh counter test waveform

RAS

t

CSR

t

UCAS,

LCAS

Address

DQ

Read cycleWrite cycleRead-Write cycle

WE

OE

WE

DQ

CHR

t

RCS

AS4C1M16F5

®

t

RAS

t

CPT

t

ASC

t

CAH

Col address

t

AA

t

CAC

t

CLZ

t

OEA

t

WP

t

WCS

t

DH

t

DS

Data in

t

WCH

CWL

t

CAS

t

RW L

t

RSH

RAL

Data out

t

ROH

t

RP

t

OEZ

OFF

t t

RRH

RCH

OE

WE

OE

DQ

t

CWL

RW L

t

WP

t

DH

t

RCS

t

CWD

t

AWD

t

OEA

t

AA

t

CLZ

t

CAC

t

OED

t

OEZ

t

DS

Data out Data in

4/11/01; v.0.9.1 Alliance Semiconductor

P. 17 of 21

AS4C1M16F5

Package dimensions

Pin 1

A1

SOJ

®

42-pin SOJ

400 mil

e

D

c

E1

E2

E

B

A

b

Seating

Plane

A2

A A1 A2

B

b

c

D

E E1 E2

e

Min Max

0.128 0.148

0.025 -

0.105 0.115

0.026 0.032

0.015 0.020

0.007 0.013

1.070 1.080

0.370 NOM

0.395 0.405

0.435 0.445

0.050 NOM

50 49 48 47 46 45 44 43 42 41 40

1234567891011

A

1

b

TSOP II

d

36 35

15 16

34 33 3 2 31

17 18 19 20

e

29 28 27 26

213022 23 24 25

c

50-pin TSOP II

Min

(mm)

Max

(mm)

A1.2

H

E

e

A

1

2

0.05

0.95 1.05

b0.300.45

c0.120.21

d 20.85 21.05

E 10.03 10.29

l

e 0.80 (typical)

H

e

11.56 11.96

l0.400.60

A

2

0–5°

4/11/01; v.0.9.1 Alliance Semiconductor

P. 18 of 21

Typical DC and AC characteristics

Normalized access time t

vs. supply voltage V

1.5

RAC

CC

Normalized access time t

vs. ambient temperature T

1.5

AS4C1M16F5

®

RAC

a

100

Typical access time t

vs. load capacitance C

RAC

L

1.4 Ta = 25°C

1.3

1.2

1.1

1.0

Normalized access time

0.9

0.8

4.0 5.5

Supply voltage (V)

Typical supply current I

vs. supply voltage V

170

160

150

-50

-60

Supply current (mA)

140

130

120

110

1.4

1.3

90

80

-70

1.2

1.1

1.0

Normalized access time

0.9

0.8

5.04.5

6.0

–55 80

35–10

125

Ambient temperature (°C)

Typical supply current I

vs. ambient temperature T

CC

a

CC

170

160

150

140

-50

-60

130

120

Supply current (mA)

110

70

60

50

Typical access time

40

30

35

30

25

20

15

10

Power-on current (mA)

5

-60

-50

50 200 250150100

Load capacitance (pF)

Typical power-on current I

vs. cycle rate 1/t

PO

RC

100

4.0 5.5

Supply voltage (V)

Typical refresh current I

vs. supply voltage V

160

140

120

100

-50

-60

80

60

Refresh current (mA)

40

20

4.0 5.5

Supply voltage (V)

5.04.5

6.0

–55 80

35–10

125

Ambient temperature (°C)

100

Typical refresh current I vs. Ambient temperature Ta vs. supply voltage V

CC3

-50

-60

CC

CC3

160

140

120

100

80

60

Refresh current (mA)

40

20

5.04.5

6.0

0.0 60

4020

Ambient temperature (°C)

80

0.0 28

64

10

Cycle rate (MHz)

Typical TTL stand-by current I

3.5

CC2

CC

3.0

2.5

2.0

1.5

1.0

Stand-by current (mA)

0.5

0

4.0 5.5 6.05.04.5

Supply voltage (V)

4/11/01; v.0.9.1 Alliance Semiconductor

P. 19 of 21

AS4C1M16F5

®

Typical TTL stand-by current I

vs. ambient temperature T

3.5

CC2

a

3.0

2.5

2.0

1.5

1.0

Stand-by current (mA)

0.5

0.0 060

4020

80

Ambient temperature (°C)

Typical hyper page mode current I

vs. ambient temperature T

140

CC4

a

120

100

80

-50

-60

60

Typical output sink current I

vs. output voltage V

70

60

50

40

30

20

Output sink current (mA)

10

0.0

0.0 1.5

1.00.5

Output voltage (V)

Typical hyper page mode current I

vs. supply voltage V

140

120

100

80

-50

-60

60

OL

CC

OL

2.0

CC4

Typical output source current I

vs. output voltage V

70

60

50

40

30

20

10

Output source current (mA)

0.0

0.0 3.0

Output voltage (V)

OH

2.01.0

4.0

40

20

Hyper page mode current (mA)

0.0 060

Ambient temperature (°C)

Capacitance

4020

15

80

40

20

Hyper page mode current (mA)

0.0

4.0 5.5 6.05.04.5

Supply voltage (V)

ƒ = 1 MHz, Ta = Room temperature

Parameter Symbol Signals Test conditions Max Unit

Input capacitance

DQ capacitance C

C

IN1

C

IN2

DQ

A0 to A9 Vin = 0V 5 pF

RAS, UCAS, LCAS, WE, OE

DQ0 to DQ15 Vin = V

Vin = 0V 7 pF

= 0V 7 pF

out

AS4C1M16F5 ordering information

Package \

Plastic SOJ, 400 mil, 42-pin 5V

TSOP II, 400 mil, 44/50-pin 5V

RAS

access time 50 ns 60 ns

AS4C1M16F5-50JC AS4C1M16F5-50JI

AS4C1M16F5-50TC AS4C1M16F5-50TI

AS4C1M16F5-60JC AS4C1M16F5-60JI

AS4C1M16F5-60TC AS4C1M16F5-60TI

4/11/01; v.0.9.1 Alliance Semiconductor

P. 20 of 21

®

AS4C1M16F5 part numbering system

AS4 C 1M16E0 –XX X X

Package:

DRAM prefix C = 5V CMOS Device number

RAS

access time

J = 42-pin SOJ 400 mil T=44/50-pin TSOP II 400 mil

AS4C1M16F5

Temperature range C=Commercial, 0°C to 70°C I=Industrial, -40°C to 85°C

4/11/01; v.0.9.1 Alliance Semiconductor

P. 21 of 21

Datasheet AS4C1M16F5-60TI, AS4C1M16F5-60TC, AS4C1M16F5-60JI, AS4C1M16F5-60JC, AS4C1M16F5-50TI Datasheet (Alliance Semiconductor Corporation)

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

Pin arrangement

Selection guide

Pin designation

Functional description

Logic block diagram

Recommended operating conditions

Absolute maximum ratings

DC electrical characteristics

AC parameters common to all waveforms

Read cycle

Write cycle

Read-modify-write cycle

Refresh cycle

Fast page mode cycle

Output enable

Notes

15 These parameters are sampled and not 100% tested.

16 These characteristics apply to AS4C1M16F5 5V devices.

AC test conditions

Key to switching waveforms

Read waveform

Upper byte read waveform

Lower byte read waveform

Early write waveform

Upper byte early write waveform

Lower byte early write waveform

Read-modify-write waveform

Upper byte read-modify-write waveform

Lower byte read-modify-write waveform

Fast page mode read waveform

Fast page mode byte write waveform

Fast page mode early write waveform

Hidden refresh waveform (read)

Hidden refresh waveform (write)

CAS before RAS refresh counter test waveform

Package dimensions

Typical DC and AC characteristics

AS4C1M16F5 ordering information

AS4C1M16F5 part numbering system