Datasheet AS4C14400-70JC, AS4C14400-60JC, AS4C14400-50TC, AS4C14400-50JC, AS4C14400-40TC Datasheet (Alliance Semiconductor Corporation)

High Performance 1M×4

AS4C14400 AS4C14405

CMOS DRAM

1M-bit × 4 CMOS DRAM (Fast page mode or EDO)

Preliminary information

Features

• Organization: 1,048,576 words × 4 bits

• High speed

- 40/50/60/70 ns RAS access time

- 20/25/30/35 ns column address access time

- 10/13/15/18 ns CAS

access time

• Low power consumption

- Active: 385 mW max (-60)

- Standby: 5.5 mW max, CMOS I/O

• Fast page mode (AS4C14400) or EDO (AS4C14405)

Pin arrangement

I/O0 I/O1

WE

RAS

A9

A0 A1 A2 A3

V

SOJ

26

1 2 3 4 5

9 10

11 12 13

CC

GND

25

I/O3

24

I/O2

23

CAS

22

OE

18

A8 A7

17

A6

16 15

A5

14

A4

I/O0 I/O1

WE

RAS

A9

A0 A1 A2 A3

V

CC

1 2 3 4 5

9 10 11

12 13

TSOP

26

GND

25

I/O3

24

I/O2

23

CAS

22

OE

18

A8 A7

17

A6

16

A5

15 14

A4

®

• 1024 refresh cycles, 16 ms refresh interval

- RAS-only or CAS-before-RAS refresh

• Read-modify-write

• TTL-compatible, three-state I/O

• JEDEC standard packages

- 300 mil, 20/26-pin SOJ

- 300 mil, 20/26-pin TSOP

• Single 5V power supply

• ESD protection ≥ 2001V

• Latch-up current ≥ 200 mA

Pin designation

Pin(s) Description

A0 to A9 Address inputs RAS

I/O0 to I/O3 Input/output

OE

CAS WE

V

CC

GND Ground

Row address strobe

Output enable

Column address strobe Read/write control Power (5.0 ± 0.5V)

Selection guide

Maximum RAS

Maximum column address access time t

Maximum CAS Maximum output enable (OE

Minimum read or write cycle time t

Minimum fast page mode cycle time t

Maximum operating current I Maximum CMOS standby current I

Shaded areas contain advance information.

access time t

) access time t

ALLIANCE SEMICONDUCTOR

Symbol 4C14400-40 4C14400-50 4C14400-60 4C14400-70 Unit

RAC

CAA

CAC

OEA

RC

PC

CC1

CC5

40 50 60 70 ns

20 25 30 35 ns

10 13 15 18 ns 10 13 15 18 ns

70 90 110 130 ns

30 35 40 45 ns

90 80 70 60 mA

1.0 1.0 1.0 1.0 mA

AS4C14400

®

Functional description

The AS4C14400 is a high performance CMOS Dynamic Random Access Memory organized as 1,048,576 words × 4 bits. The AS4C14400 is fabricated with advanced CMOS technology and designed with innovative design techniques resulting in high speed, extremely low power and wide operating margins at component and system levels.

The AS4C14400 features a high speed page mode operation in which high speed read, write and read-write are performed on any of the 1024 × 4 bits defined by the column address. The asynchronous column address uses an extremely short row address capture time to ease the system level timing constraints associated with multiplexed addressing. Output is tri-stated by a column address strobe (CAS as an output enable independent of RAS

. Very fast CAS to output access time eases system design.

Refresh on the 1024 address combinations of A0 to A9 during a 16 ms period is accomplished by performing any of the following:

•RAS-only refresh cycles

• Hidden refresh cycles

-before-RAS refresh cycles

•CAS

• Normal read or write cycles

The AS4C14400 is available in JEDEC standard 20/26-pin plastic SOJ and 20/26-pin plastic TSOP packages. System level features include single power supply of 5.0 ± 0.5V tolerance and direct interface with TTL logic families.

) which acts

Logic block diagram

I/O3 I/O2 I/O1 I/O0

OE

RAS

CAS

WE

RAS

clock

generator

clock

CAS generator

WE

clock

generator

Vcc

GND

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9

Column decoder

REFRESH

CONTROLLER

Address buffer

Row decoder

Sense amp

1024 × 1024 × 4

Array

(4,194,304)

Data

I/O

Recommended operating conditions

Parameter Symbol Minimum Nominal Maximum Unit

V

Supply voltage

CC

GND 0.0 0.0 0.0 V

V

Input voltage

IH

V

IL

Operating temperature TA 0 70 °C

Recommended operating conditions apply to all specifications unless otherwise noted.

4.5 5.0 5.5 V

2.4 – VCC + 1 V

–1.0 – 0.8 V

2

AS4C14400

®

Absolute maximum ratings

Parameter Symbol Minimum Maximum Unit

Input voltage V

Output voltage V Power supply voltage V

Storage temperature (plastic) T Soldering temperature × time T

Power dissipation P DC output current I

NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

in

out

CC

STG

SOLDER

D

out

-1.0 +7.0 V

-55 +150 °C – 260 × 10

o

C × sec

–1W –50mA

DC electrical characteristics

-40 -50 -60 -70

Parameter Symbol Test Conditions

Input leakage current I

Output leakage current I

Operating power supply current

TTL standby power supply current

Average power supply current, RAS

refresh mode

Fast page mode average power supply current

CMOS standby power supply current

-before-RAS refresh

CAS power supply current

I

V

Output voltage

V

Shaded areas contain advance information.

0V ≤ Vin ≤ +5.5V

I

Pins not under test = 0V Outputs disabled,

OZ

0V ≤ V

out

RAS, CAS, Address

CC1

cycling: t

RAS = CAS = V

CC2

RAS cycling, CAS = VIH,

CC3

t

RC

= min

RAS = VIL, CAS cycling, Address cycling:

CC4

CC5

= min

t

PC

RAS = CAS = VCC - 0.2V – 1.0 – 1.0 – 1.0 – 1.0 mA

RAS, CAS cycling:

CC6

OHIOUT

OLIOUT

= min

t

RC

= -5.0 mA 2.4 – 2.4 –2.4–2.4–V = 4.2 mA – 0.4 – 0.4 – 0.4 – 0.4 V

≤ +5.5V

=min

RC

IH

Min Max Min Max Min Max Min Max

Unit Notes

-2 +2 -2 +2 -2 +2 -2 +2 µA

-10 +10 -10 +10 -10 +10 -10 +10 µA

– 90 – 80 – 70 – 60 mA 1,2

– 2.0 – 2.0 – 2.0 – 2.0 mA

– 90 – 80 – 70 – 60 mA 1

– 80 – 70 – 60 – 50 mA 1,2

– 90 – 80 – 70 – 60 mA 1

3

AS4C14400

AC parameters common to all waveforms

Symbol Parameter

t

RC

t

RP

t

RAS

t

CAS

t

RCD

t

RAD

t

RSH(R)

t

CSH

t

CRP

t

ASR

t

RAH

t

T

t

REF

t

CLZ

Shaded areas contain advance information.

Random read or write cycle time 70 – 90 –110–130– ns RAS precharge time 20 – 30 –40–50–ns

RAS pulse width 40 10K 50 10K 60 10K 70 10K ns

CAS pulse width 10 – 13 –15–18–ns

RAS to CAS delay time 18 30 20 37 20 45 20 52 ns 6 RAS to column address delay time 13 20 15 25 15 30 15 35 ns 7

CAS to RAS hold time (read) 10 – 13 –15–18–ns

RAS to CAS hold time 40 – 50 –60–70–ns

CAS to RAS precharge time 0 – 0 –0–0–ns Row address setup time 0 – 0 –0–0–ns

Row address hold time 8 – 10 –10–10–ns

Transition time (rise and fall) 2 50 2 50 2 50 2 50 ns 4,5

Refresh period – 16 – 16 – 16 – 16 ms 3 CAS to output in low Z 0 – 0 –0–0–ns8

®

-40 -50 -60 -70

Min Max Min Max Min Max Min Max

Unit Notes

Read cycle

Symbol Parameter

t

RAC

t

CAC

t

AA

t

AR(R)

t

RCS

t

RCH

t

RRH

t

RAL

t

CPN

t

ODS

t

OFF

Shaded areas contain advance information.

Access time from RAS – 40 – 50 – 60 – 70 ns 6

Access time from CAS – 10 – 13 – 15 – 18 ns 6,13

Access time from address – 20 – 25 – 30 – 35 ns 7,13

Column add hold from RAS 30 – 40 –45–55–ns Read command setup time 0 – 0 –0–0–ns

Read command hold time to CAS 0 – 0 –0–0–ns9

Read command hold time to RAS 0 – 0 –0–0–ns9

Column address to RAS lead time 20 – 25 –30–35–ns CAS precharge time 5 – 10 –10–10–ns

Output disable setup time 0 – 0 –0–0–ns

Output buffer turn-off time 0 10 0 13 0 15 0 18 ns 8,10

-40 -50 -60 -70

Min Max Min Max Min Max Min Max

Unit Notes

4

AS4C14400

®

Write cycle

-40 -50 -60 -70

Symbol Parameter

Column address setup time 0 – 0 –0–0–ns

t

ASC

Column address hold time 8 – 10 –10–15– ns

t

CAH

Column address hold time to RAS 30 – 40 –45–55– ns

t

AWR

Write command setup time 0 – 0 –0–0–ns11

t

WCS

Write command hold time 5 – 10 –10–15– ns11

t

WCH

Write command hold time to RAS 30 – 40 –45–55– ns

t

WCR

Write command pulse width 8 – 10 –10–15– ns

t

WP

Write command to RAS lead time 10 – 13 –15–18– ns

t

RWL

Write command to CAS lead time 10 – 13 –15–18– ns

t

CWL

Data-In setup time 0 – 0 –0–0–ns12

t

DS

Data-In hold time 8 – 10 –10–15– ns12

t

DH

Data-In hold time to RAS 30 – 40 –45–55– ns

t

DHR

Shaded areas contain advance information.

Min Max Min Max Min Max Min Max

Unit Notes

Read-modify-write cycle

-40 -50 -60 -70

Symbol Parameter

Read-write cycle time 105 – 131 – 155 – 181 – ns

t

RWC

RAS to WE delay time 60 – 73 –85–98– ns11

t

RWD

CAS to WE delay time 30 – 36 –40–46– ns11

t

CWD

Column address to WE delay time 40 – 48 –55–63–ns11

t

AWD

t

RSH(W)

t

CAS(W)

Shaded areas contain advance information.

CAS to RAS hold time (write) 10 – 13 –15–18–ns

CAS pulse width (write) 10 – 13 –15–18–ns

Min Max Min Max Min Max Min Max

Unit Notes

5

AS4C14400

®

Fast page mode cycle

-40 -50 -60 -70

Symbol Parameter

Read-write cycle time

t

PC

t

CAP

t

CP

t

PCM

t

CRW

t

RASP

Shaded areas contain advance information.

(fast page)

Access time from CAS precharge – 25 – 30 – 35 – 40 ns 13

CAS

precharge time

(fast page)

Fast page mode RMW cycle 65 – 76 –85–96–ns

Page mode CAS pulse width (RMW)

RAS pulse width 40 100K 50 100K 60 100K 70 100K ns

Min Max Min Max Min Max Min Max

Unit Notes

30 – 35 –40–45–ns14

5 – 10 –10–10–ns

45 – 54 –60–69–ns

Refresh cycle

-40 -50 -60 -70

Symbol Parameter

CAS setup time (CAS-before-RAS) 10 – 10 –10–10–ns3

t

CSR

CAS hold time (CAS-before-RAS) 10 – 10 –15–15–ns3

t

CHR

RAS precharge to CAS hold time 0 – 0 –0–0–ns

t

RPC

CAS

t

CPT

Shaded areas contain advance information.

precharge time

-before-RAS counter test)

(CAS

Min Max Min Max Min Max Min Max

5 – 10 –10–10–ns

Unit Notes

Output enable

Std Symbol Parameter

t

ROH

t

OEA

t

OED

t

OEZ

t

OEH

Shaded areas contain advance information.

6

RAS hold time referenced to OE 5 – 10 –10–10–ns OE access time – 10 – 13 – 15 – 18 ns

OE to data delay 10 – 13 –15–18–ns

Output buffer turnoff delay from OE

OE command hold time 10 – 13 –15–18–ns

-40 -50 -60 -70

Min Max Min Max Min Max Min Max

Unit Notes

– 10 – 13 – 15 – 18 ns 8, 10

®

A

AA

A

AAAA

Notes

1I

, I

CC1

2I

CC1

and I

, and I

CC3

CC4

depend on output loading. Specified values are obtained with the output open.

CC4

3 An initial pause of 200 µs is required after power-up followed by any 8 RAS

refresh counter, a minimum of 8 CAS extended periods of bias without clocks (greater than 16 ms).

4 AC Characteristics assume t

≤ V

(max)

5V

IH

. See AC test conditions for more information.

CC

(min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL.

6 Operation within the t

specified t

(max) limit, then access time is controlled exclusively by t

RCD

7 Operation within the t

specified t

(max) limit, then access time is controlled exclusively by tAA.

RAD

8 Assumes three state test load (5 pF and a 380 Ω Thevenin equivalent). 9 Either t 10 t

OFF

11 t

WCS

t

WCS

If t selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate.

or t

RCH

RRH

(max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels.

, t

WCH

RWD

(min) and t

≥ t

RWD

12 These parameters are referenced to CAS 13 Access time is determined by the longest of t

≥ t

14 t

to achieve tPC (min) and t

ASC

CP

15 These parameters are sampled and not 100% tested.

depend on cycle rate.

CC6

-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after

= 5 ns. All AC parameters are measured with a load equivalent to two TTL loads and 100 pF, V

T

(max) limit ensures that t

RCD

(max) limit ensures that t

RAD

must be satisfied for a read cycle.

, t

CWD

≥ t

WCH

(min), t

and t

CWD

are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only. If t

AWD

(min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the cycle.

WCH

≥ t

(min) and t

CWD

leading edge in early write cycles and to WE leading edge in read-write cycles.

(max) values.

CAP

CAA

(max) can be met. t

RAC

(max) can be met. t

RAC

≥ t

AWD

or t

CAC

cycles before proper device operation is achieved. In the case of an internal

(max) is specified as a reference point only. If t

RCD

.

CAC

(max) is specified as a reference point only. If t

RAD

(min), the cycle is a read-write cycle and the data out will contain data read from the

.

CAP

AS4C14400

(min) ≥ GND and V

IL

is greater than the

RCD

is greater than the

RAD

WCS

IH

≥

AC test conditions

- Access times are measured with output reference levels of VOH = 2V and VOL = 0.8 V

- Input rise and fall times: 5 ns

+3.0V

90%

10%

Figure A: Input waveform

90%

10%

Key to switching waveforms

AAA

A

AAA

Don’t care input Rising input Falling input

AAA

A

AAA

+5V

R1 = 828W

D

out

100 pF*

R2 = 295W

GND

Figure B: Equivalent output load

AAAA

Undefined output

AAAA

*including scope

and jig capacitance

7

AS4C14400

AAAA

AAA

AAAA

AA

AAAA

AA

AAAA

AA

AAAA

AAA

AAAA

AAA

A

AA

AAAA

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AAAA

AAA

AAAA

AAAAAA

AAAA

AAA

AAAA

AAAAAAAA

Timing waveform of read cycle

RAS

t

CRP

CAS

t

ASR

Address

WE

OE

Row

t

RAH

t

RAD

t

RCD

t

ASC

®

t

RAL

RC

t

RP

t

CAS

t

RSH

t

CAH

t

RAS

t

CSH

t

RCS

t

AR

Column

t

ROH

RRH

t

RCH

I/O

Timing waveform of early write cycle

RAS

t

CRP

CAS

t

ASR

Address

WE

RAH

Row

t

RAD

t

RCD

t

WCS

t

RAC

t

AWR

t

CSH

t

CLZ

t

RAS

Column

t

WCR

t

OEZ

t

AA

t

CAC

OEA

t

OFF

Data Out

t

ASC

t

CWL

t

CAH

RC

t

RWL

t

RAL

CAS

t

RSH

t

WP

t

WCH

t

RP

8

OE

I/O

t

DHR

t

DS

t

DH

Data In

AS4C14400

A

AA

AAAA

AAAAAA

AAAA

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AAAA

AAA

AAAA

AAA

AAAA

AAA

AAAA

AAAAAA

AAAA

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AAAA

AA

AAAA

AAAAAAAA

AAAA

AA

AAAA

A

AAAA

A

AAAA

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AAAA

AAAAAA

AAAA

®

Timing waveform of write cycle (OE controlled)

t

ASC

t

CAH

RC

t

CAS

t

RAL

t

DS

Data In

t

RSH

t

CWL

DH

t

RWL

t

OEH

t

RP

t

WP

RAS

CAS

Address

WE

OE

I/O

t

ASR

t

CRP

Row

t

RAD

t

RAH

t

RCD

t

DHR

t

OED

t

AWR

t

CSH

t

RAS

Column

t

WCR

Timing waveform of read-write cycle

RAS

t

CRP

CAS

t

RAD

t

RAH

Row Column

Address

WE

OE

I/O

t

ASR

t

RCS

RCD

t

RAC

t

AWD

t

OEA

t

CAC

t

CLZ

t

RAL

CAH

t

OEZ

t

CWD

RWC

t

CAS

t

RSH

t

OED

t

RP

t

RWL

t

CWL

t

WP

t

DS

t

DH

t

RAS

t

CSH

t

AR

t

ASC

t

RWD

t

AA

Data InData Out

9

AS4C14400

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AAA

AAAA

A

AAAA

AAAAAA

AAAA

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AAAA

AAA

AA

AAAA

AAAAAAAA

AAAA

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AAA

A

AAAA

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AAAA

AAAAAA

AAAA

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AAAA

AAAAAA

AAAA

AAA

AAAA

AAA

AAAA

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AA

AAAA

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AAAAAA

AAAA

AAAAAA

AAAA

Timing waveform of fast page mode read cycle

RAS

t

RASP

®

t

RP

t

CRP

t

RCD

CSH

t

CAS

t

AR

t

Row

RAH

RAD

Column Column

t

RCS

t

RCH

Address

t

ASR

WE

t

OEA

OE

t

RAC

I/O

t

CLZ

t

AA

Data Out

Timing waveform of fast page mode early write cycle

t

RAH

RAS

CAS

Address

WE

t

CRP

t

ASR

t

RCD

t

RAD

CSH

t

AR

t

CAS

Row Column Column Column

t

CP

t

RASP

t

ASC

RCS

t

OEZ

t

OFF

Data Out

t

ASC

t

WCS

t

WCH

t

PC

CAP

t

RSH

t

PC

t

CAH

Column

t

CP

RAL

t

RCH

t

OEA

t

CAC

Data Out

t

RWL

t

RAL

t

WP

t

CWL

t

OEH

t

RRH

t

RSH

t

CAH

10

OE

I/O

t

HDR

t

DS

t

DH

t

OED

Data In Data In Data In

Timing waveform of fast page mode read-write cycle

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A

AAAA

AA

AAAA

AAA

AAAA

A

AAAA

A

AAAA

AAA

AAAA

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AS4C14400

®

RAS

CAS

Address

t

ASR

t

RAD

Row Column ColumnColumn

t

RCS

WE

OE

I/O

Timing waveform of RAS

RAS

CAS

Address

t

RASP

t

RCD

t

RAC

t

RAH

t

OEA

t

RWD

CSH

t

AWD

t

CWD

t

AA

t

CLZ

t

CAC

Data Out

t

CAH

CAS

t

OEZ

PCM

t

CP

t

CAH

t

CWL

t

CWD

t

OED

t

DH

t

DS

t

CLZ

t

CAC

t

DS

Data InData In

Data Out

t

CAH

t

CWD

t

AWD

t

OEA

t

CAP

t

CLZ

t

CAC

Data Out

RAL

Data In

t

CRP

t

RWL

t

CWL

t

WP

only refresh cycle (WE = OE = V

t

RC

t

RP

t

RPC

t

ARS

Row

t

CRP

t

RAH

t

RAS

t

RP

or VIL)

IH

Timing waveform of CAS-before-RAS refresh cycle (WE = OE = V

t

RC

t

RAS

t

CHR

RAS

CAS

I/O

t

RPC

t

OFF

RP

t

CPN

t

CSR

or VIL)

IH

11

AS4C14400

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AAAA

AA

AAAA

AA

AAAA

A

AAAA

AA

AAAA

AAA

AAAA

AAA

AAAA

AAA

AAAA

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Timing waveform of hidden refresh cycle (read)

®

t

RC

t

RAS

t

CRP

t

RCD

t

RSH

CAS

t

AR

t

ASC

ColumnRow

Address

t

ASR

t

RAD

t

RAH

t

RCS

WE

t

OEA

OE

t

RAC

t

AA

t t

CAC CLZ

I/O

Timing waveform of hidden refresh cycle (write)

t

RAS

CAS

Address

WE

I/O

t

CRP

t

ASR

t

RAH

t

RCD

t

RAD

t

ASC

AR

t

RAL

t

ColumnRow

t

WCR

t

WCS

t

DS

t

DHR

RWL

t

WP

Data In

t

t t

OFF OEZ

RC

t

PR

t

CRP

t

RRH

t

PR

t

CHR

t

RAS

Data Out

t

RC

t

CAH

RSH

t

WCH

t

DH

t

RP

12

OE

Timing waveform of CAS before RAS refresh counter test cycle

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AAA

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AAA

AAAA

AAA

AAAA

AAAAAAAA

AAAA

AAA

RAS

t

CSR

t

CHR

CAS

Address

I/O

WE

Read CycleWrite CycleRead-Write Cycle

OE

WE

I/O

t

CPT

t

AA

t

RCS

®

t

RAS

t

Column

t

WP

t

WCS

t

DS

Data In

CAH

t

CLZ

t

DH

CAC

t

WCH

t

CWL

OEA

t

RSH

t

CAS

t

RAL

Data Out

t

RWL

t

ROH

t

OFF

AS4C14400

t

RP

t

RRH

t

RCH

OE

WE

OE

I/O

t

CLZ

CAC

t

RCS

t

CWD

t

AWD

t

OEA

AA

t

OEZ

t

OED

Data Out Data In

t

WP

t

CWL

t

DH

t

DS

13

AS4C14400

Typical DC and AC characteristics

Normalized access time t

vs. supply voltage V

1.5

RAC

CC

Normalized access time t

vs. ambient temperatur e T

1.5

®

RAC

a

Typical access time t

vs. load capaci tance C

90

RAC

L

1.4 Ta = 25°C

1.3

1.2

1.1

1.0

Norm al ized access tim e

0.9

0.8

4.1 5.5 Supply voltage (V)

Typical supply current I

vs. supply voltage V

70 60 50 40 30 20

Supply current (mA)

10

1.4

1.3

80 70

-60

1.2

1.1

1.0

Norm al ized access tim e

0.9

0.8

5.04.5

6.0

–55 80

35–10

125

Ambient temperature (°C)

CC

Typical supply current I

vs. ambient temperatur e T

70

CC

a

60 50 40 30 20

Supply current (mA)

10

60 50 40

Typica l acces s time (ns)

30

-50

-40

20

50 200 250150100

Load capacitance (pF)

Typical power-on current I

vs. cycle rate 1/t

70 60 50 40 30 20

Power-on current (mA)

10

PO

RC

0.0

4.0 5.5 Supply voltage (V)

Typical refresh current I

vs. supply voltage V

70 60 50 40 30 20

Refresh current (mA)

10

0.0

4.0 5.5 Supply voltage (V)

14

5.04.5

6.0

–55 80

35–10

125

Ambient temperature (°C)

0.0

CC3

CC

Typical refresh current I

vs. ambient temperatur e T

70

CC3

a

60 50 40 30 20

Refresh current (mA)

10

0.0

5.04.5

6.0

–55 80

35–10

125

Ambient temperature (°C)

0.0 28

64

10

Cycle rate (MHz)

Typical TTL stand-by current I

vs. supply voltage V

3.5

CC2

CC

3.0

2.5

2.0

1.5

1.0

Stand-b y current (mA)

0.5

0.0 28

64

10

Supply voltage (V)

AS4C14400

®

Typical TTL stand-by current I

vs. ambient tempe rat ure T

3.5

3.0

2.5

2.0

1.5

1.0

Stand-b y current (mA)

0.5

0.0 060804020

Ambient temperature (°C)

CC2

a

Capacitance (f = 1 MHz, T

Typical fast page mode current I

vs. ambient temperature T

70 60 50 40 30 20 10

Fast pa g e m o de curr en t (m A )

0.0 060804020

Ambient temperature (°C)

a

CC4

Typical fast page mode current I

70 60 50 40 30 20 10

Fast page mode current (mA)

0.0

vs. supply voltage V

4.0 5.5 6.05.04.5 Supply voltage (V)

= Room Temperature)

a

CC

Parameter Symbol Signals Test Conditions Max Unit

Input capacitance

I/O capacitance C

C

IN1

RAS, CAS, WE, OE Vin = 0V 7 pF

C

IN2

I/O

A0 to A8 Vin = 0V 5 pF

I/O0 to I/O3 Vin = V

= 0V 7 pF

out

CC4

15

AS4C14400

®

Ordering codes

Package \ RAS Access Time 40 ns 50 ns 60 ns 70 ns

Plastic SOJ, 300 mil, 20/26-pin

Plastic TSOP, 300 mil, 20/26-pin

AS4C14400-40JC AS4C14405-40JC

AS4C14400-40TC AS4C14405-40TC

AS4C14400-50JC AS4C14405-50JC

AS4C14400-50TC AS4C14405-50TC

AS4C14400-60JC AS4C14405-60JC

AS4C14400-60TC AS4C14405-60TC

AS4C14400-70JC AS4C14405-70JC

AS4C14400-70TC AS4C14405-70TC

Shaded areas contain advance information.

Part numbering system

AS4C 144 00 –XX X C

DRAM Prefix Device number RAS

access time

Package: J = SOJ 300 mil,

T = TSOP 300 mil

Commercial temperature range, 0°C to 70 °C

Representatives, distributors, and sales offices

DOMESTIC REPS

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Alliance Semiconductor reserves the right to make changes in this data sheet at any time to improve design and supply the best product possible. Publication of advance information does not constitute a committment to produce or supply the product described. The company cannot assume responsibility for circuits shown or represent that they are free from patent infringement. Alliance products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of Alliance. ProMotion of Alliance Semiconductor Corporation. All other trademarks are property of their respective holders.

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interACTIVE

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®

and the Alliance logo are registered trademarks

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Please contact your rep to

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