Datasheet AS3842 Datasheet (ASTEC)

SWITCHING POWER SUPPLY CONTROL
LOOP DESIGN

AS3842

Application Note 5

Mike Wong

2. Basic Control Loop Concepts

2.1 Transfer Functions and the Bode Plots

1. Introduction

In a switched mode power converter, the con­duction time of the power switch is regulated
according to the input and output voltages. Thus,
a power converter is a self-contained control
system in which the conduction time is modu­lated in reaction to changes in the input and
output voltages. From a theoretical approach,
control loop design often involves complicated
equations, making control a challenging but

The transfer function of a system is defined as
the output divided by the input. It consists of a
gain and a phase element that can be plotted
separately in a Bode plot. The gain around a
closed loop system is the product of the gains of
all the elements around the loop. In a Bode plot,
the gain is plotted logarithmically. Since the
product of two numbers is their logarithmic sum,
their gains can be summed graphically. The
phase of the system is the sum of all phase shifts
around the loop.

often misunderstood area in switched mode
power supply design. A simplified approach to
feedback control loop analysis is presented in
the following pages, beginning with a general
overview of various parameters affecting per­formance in a switching power system. A dem­onstration of an actual power supply is given to
show the components involved in designing the
characteristics of the control loop. Test results
and measurement techniques are also included.

R

V

IN

C

V

OUT

2.2 Poles

Mathematically, in a transfer equation, a pole
occurs when its denominator becomes zero.
Graphically, a pole in the bode plot occurs when
the slope of the gain decreases by 20 dB per
decade. Figure 1 illustrates a low pass filter
commonly used for creating a pole in the sys­tem. Its transfer function and Bode plots are
also shown.

GAIN

0dB

T(S) = =

f

© ASTEC Semiconductor

POLE

V

V

=

OUT (S)

IN (S)

2πRC

1

1

RCs + 1

PHASE

–45°
–90°

Figure 1.

161

f

POLE

0°

f

POLE

AS3842

Application Note 5

C

R2

V

IN

V

(S)

ZERO

=

OUT

V

(S)

IN

1

2πR2C

R1Cs

T(S) = =

f

2.3 Zeros

A zero in a frequency domain transfer function
occurs when the numerator of the equation goes
to zero. In a Bode plot, a zero occurs at a point
where the slope of the gain increases by 20 dB
per decade accompanied by 90° phase lead. A
high pass filter circuit causing a zero is depicted
in Figure 2.

R1

–
+

–1

1

R2

+

R1

V

OUT

20 log ( )

Figure 2.

3.0 Ideal Gain-phase Plots for a
Switching Mode Power Supply

A goal must be clearly defined prior to designing
any control system. Generally, the goal is simply
a Bode plot constructed to achieve the best
system dynamic response, tightest line and load
regulation, and greatest stability. An ideal
closed loop Bode plot should possess three
characteristics: sufficient phase margin, wide

There is a second type of zero, known as a right
half plane zero, that causes phase lag instead of
phase lead. A right half plane zero causes a 90°
phase lag, accompanied by an increase in gain.
Right half plane zeros are usually found in boost
and buck-boost converters and so extra precau­tion should be taken during feedback compen­sation design so the crossover frequency of the
system is well below the frequency of the right
half plane zero. The Bode plot of a right half
plane zero is shown below in Figure 3.

bandwidth, and high gain. A high phase margin
damps oscillations and shortens the transient
settling time. Wide bandwidth allows the power
system to quickly respond to sudden line and
load changes. A high gain ensures good line
and load regulation.

3.1 Phase Margin

Referring to Figure 4, the phase margin is the
amount of phase above 0° at the crossover
frequency (fcs). This is different from most con­trol system textbooks that present a measuring
phase margin from -180°. They include the

GAIN

R1
R2

PHASE

–90°
–135°
–180°

f

ZERO

f

ZERO

GAIN

20 log ( )

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R1
R2

PHASE

–180°

f

f

ZERO

Figure 3.

162

–270°

ZERO

Application Note 5

GAIN

60

(dB)

40

AS3842

f

: CORNER FREQUENCY

CN

: CROSSOVER FREQUENCY

f

f

CN

CS

: SWITCHING FREQUENCY

f

S

20

0

180°

PHASE

90°

0°

Figure 4.

negative feedback at DC that gives them 180°
phase shift at the beginning. In the actual
measurement, the 180° phase shift is compen­sated at DC and enables the phase margin to be
measured from 0°.

According to Nyquist’s stability criterion, a sys­tem is stable when its phase margin exceeds 0°.
However, a region of marginal stability exists
where the system transient response oscillates
and eventually damps out after a long settling
time. A system is marginally stable if its phase
margin is less than 45°. A phase margin above
45° provides the best dynamic response, short
settling time and minimal amount of overshoot.

false information and must not be transmitted by
the control loop.

Therefore, the crossover frequency of the sys­tem must not exceed half the switching fre­quency. Otherwise, the switching noise, the
ripple, distorts the desired information, the out­put voltage, causing the system to be unstable.

3.3 Gain

High system gain contributes significantly to
ensuring good line and load regulation. It en­ables the PWM comparator to accurately change
the power switch duty cycle in response to
variants in the input and output voltage. Often,
a tradeoff needs to be determined between

3.2 Gain-Bandwidth

higher gain and lower phase margin.
The gain-bandwidth is the frequency at which
the gain is unity. In Figure 4, the gain-bandwidth
is the crossover frequency, f

. A major limiting

cs

factor of the maximum crossover frequency is
the power supply switching frequency. Accord­ing to sampling theory, if the sampling frequency
is less than 2 times the frequency of the informa­tion, the information will not be properly read.

In a switched mode power supply, the switching
frequency is seen in the output ripple, which is

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4. A Practical Design Analysis

Example

Applying classical control loop analysis tech-

niques, the control loop of a switching regulator

is divided into four main stages, output filter,

PWM circuit, error amplifier compensation, and

feedback . Figure 5 illustrates a block diagram

of the four stages and Figure 6 illustrates a

power supply circuit diagram.

163

f

CS fS

PHASE MARGIN

AS3842

)

Application Note 5

V

IN

4.1 Feedback Network, H(s):

+

Σ

REF

ERROR

AMP

G3 (S)

–

V

G2 (S) G1 (S)

PWM

CIRCUIT

H (S)

Figure 5.

FILTER

V

OUT

The feedback network divides the output volt­age down to the reference level of the error
amplifier. Its transfer equation is simply a resis­tor divider equation:

The output voltage is first divided down by the
feedback network. The feedback voltage is then
fed into an error amplifier, which compares it
with a reference level and generates an error
voltage. The pulse width modulation stage takes
the error voltage and compares with the power
transformer current and converts it to the proper

4.2 Output Filter Stage, G1(s)

In a current mode control system, the output
current is regulated to achieve the desired out­put voltage. The output filter stage converts the
pulsating output current into the desired output
voltage. Small signal analysis reveals that the

duty cycle to control the amount of power pulsing
to the output stage. The output filter stage
smoothes out the chopped voltage or current
from the power transformer, completing the
feedback control loop. The following deter­mines gain and phase of each stage and com­bines them to form the system transfer function
and the system gain and phase plots.

H(S)=

R2

R1+R2

RRR

=+

12

FB



=

VIR

() ()

OUT S OUT S






||

FB



1

CS

ESR

+









(1)

2

()

3

()

R12

C9

ASTEC Semiconductor

C7

C8

R11

COMP V

REG

V

V

FB

CC

SENSE OUT
R

GND

TCT

AS3842

R10

PWM CIRCUIT (G2

C5

C6

V

()

()

GS

1

+

R9

+

C4

C3

R8

Figure 6.

164

R7

OUT S

==

I

()

OUT S

R5

R6

AS431

ERROR AMP COMPENSATION (G3)

()

+

1

R ESRCS

FB

()

++

R ESR CS

FB

R4

R3

C2

C1

+

C

R1

R2

FEEDBACK
NETWORK (H)

1

OUT

OUTPUT
FILTER
(G1)

V

OUT

4

()

Application Note 5

AS3842

I

OUT

optocoupler diode, and the output impedance of

the AS3842 error amplifier. This is discussed

ESR

+

C

OUT

R

SENSE

V

OUT

extensively in the application note “Secondary

Error Amplifier with the AS431.“ The transfer

function from the output of the error amplifier to

the comp pin of the AS3842 is:

Figure 7.

ESR of the output capacitor and the feedback
network resistors (R1 + R2 = RFB) dictate the
characteristics of the output filter transfer func­tion. The circuit analysis of Figure 7 demon­strates the effects of ESR and R

SENSE

.

Transfer equation G1(s) shows an initial low
frequency gain of R

. The gain starts to roll off

FB

at fpole = 1/2π (RFB+ESR)C and levels off at
f

= 1/2πESRC. The Bode plots of G1(s) are

ZERO

shown in Figure 8.

4.3 PWM Circuit Stage, G2(s)

The optocoupler circuit transfers the error signal
created by the error amplifier network to the
primary side. The AS3842 PWM circuit com­pares the error voltage with current through
primary side of the power transformer. The duty
cycle of the power FET is then modulated to
supply sufficient current to the secondary to
maintain a desired output level.

V

and the output of the compensation error ampli-

fier. CTR is the current transfer ratio of the

optocoupler. R6 is the current limit resistor in

series with the optocoupler diode. R

output impedance of the AS3842 Comp pin

when it tries to source above its maximum output

current.

After the error signal is transferred to the com-

pensation pin, it is compared with a current

sense signal. Figure 9 shows a simplified block

diagram of the current sense comparator and

switching stages.

In a closed loop system V

the same level as I

effectively regulated by V
The small signal transfer function of the

optocoupler has a constant gain proportional to
the current transfer ratio of the optocoupler,
R6,a current limit resistor in series with the

∆V

∆V

CATHODE

CATHODE

I

PRIMARY =

COMP

=

CTR

R6

R

COMP

5

(

)

is the cathode voltage of the AS431

is the

COMP

is maintained in

COMP

; therefore, I

SENSE

V

COMP

R

SENS E

COMP

PRIMARY

.

is

6

(

)

20 LOG R

ASTEC Semiconductor

SENSE

GAIN

f

POLE

f

ZERO

Figure 8.

165

PHASE

–90°

0°

f

f

POLE

ZERO

AS3842

I

SECONDARY

SENSE

Figure 9.

N:1

I

PRIMARY

The transfer function of PWM stage can be
created by combining equation (3) and (6):

GS

26()=

V

COMP

I

SENSE

Since I

+
–

SECONDARY

R

, the secondary current or out­put current, is proportional to the primary cur­rent, equation (4) can be rearranged to show a
relationship between secondary current and
V

.

COMP

Application Note 5

I

I

PRIMARY =

∆V

COMP

∆I

OUT

I

∆

OUT

(9)

V

∆

CATHODE

SECONDARY

V

COMP

=

R

SENSE

I

OUT

=

N

R

SENSE

=

N

=

N

NRCTR

SENSE

R

COMP

R

7

(

)

8

(

)

C1

R1

R

IN

V

FB

V

REF

V

G3(s) = =

fp1 = 0
fZ =

f

p2

A = OPEN LOOP GAIN OF THE AMPLIFIER

ASTEC Semiconductor

ERROR

V

FB

1

2πR1C2

=

2πR1C2 ( )

–
+

(C2 + C1) + SR1 (C2 C1)

R

IN

1

C1

C1 + C2

C2

V

1 + R1C2

ERROR

20 LOG A

GAIN

(dB)

–45°

–90°

PHASE

Figure 10.

166

–20dB/DEC

–20dB/DEC

f

z

0°

fp2

Application Note 5

20 LOG A

AS3842

GAIN

(dB)

0°

–45°

–90°

PHASE

–135°

–180°

OUTPUT

ERROR

AMP

OVERALL

Transfer function G2 consists of only gain and
no phase shift.

4.4 Error Amplifier Compensation
Network,G3(s)

Once the transfer functions of the output filter
and PWM circuit stage are determined, the error
amplifier compensation network can then be
configured to achieve the optimum system per­formance. Figure 10 illustrates a compensation

ERROR AMP.

OUTPUT FILTER

Figure 11.

nique can be applied to derive the overall sys­tem transfer function. By superimposing the
gains and phases of the stages around the loop,
a Bode plot of the overall system is generated.
The poles and zeros of the compensation net­work can then be placed to optimize the system
performance. Figure 11 combines the Bode
plots of the stages and 180° phase shift is also
added to account for the negative feedback of
the system.

scheme that gives high frequency roll-off and
high gain at low frequency.

This compensation scheme has some favorable
characteristics for error amplifier compensation.
It has very high DC gain and well-controlled roll
off.

4.5 Overall System

Since this is a linear system, superposition tech-

5. Measurement Results

A 150-watt current mode forward converter was
constructed and its small signal loop character­istics modified to demonstrate its effects on
system transient response. Figure 12 shows its
gain-phase plot. As predicted by Figure 11, the
same
gain-phase shows the system has a phase margin

OVERALL

F

CS

PHASE

MARGIN

Bode plot curvature was acquired. The

ASTEC Semiconductor

167

AS3842

Application Note 5

of 86.7°, implying a stable system with a fast
transient response. Figure 13 shows the transient
response of the system. To demonstrate the
effects of phase margin, the phase margin of the
system was decreased by increasing the overall
gain of the system, increasing the crossover fre­quency. The phase margin decreases with in­creasing crossover frequency. Figure 14 shows a
Bode plot of the system with higher cross over
frequency and smaller phase margin of 65°. Its

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transient response is shown on figure 15. Note
that smaller phase margin results in greater oscil­lation and longer settling time. Table 1 compares
the changes in line and load regulations between
two systems with different gain magnitudes. As
discussed previously, high loop gain results in
tighter line and load regulation. It should also be
noted that a tradeoff has been made between the
high phase margin and lower loop gain.

168

Application Note 5

AS3842

Load Regulation High Loop Low Loop

Gain Gain

VIN = 85 V

= 135 V

IN

AC

AC

127 mV 132 mV
101 mV 116 mV

Line Regulation

Low Load 21 mV 25 mV
High Load 5 mV 9 mV

(Table 1.)

6.0 Measurement Techniques

To guarantee accurate results, the input imped­ance of the test signal injection node must be
larger than its output impedance. In the test
circuit (Figure 6) where the error amplifier is on
the secondary side and the PWM circuit is on the
primary side, the test signal is injected at the
output of the optocoupler and before the V

COMP

input of the AS3842. The input impedance is the
impedance looking into the V

pin and the

COMP

output impedance is the output impedance of
the optocoupler. In other applications where the
error amplifier can not be separated from the
PWM circuitry, the test signal can be injected
following the output filter capacitor, in series with
the input to the error amplifier.

References

Venable, D., “Practical techniques for Analyzing, Measuring and Stabilizing Feedback Control Loop in Switching

Regulators and Converters,” PowerCon 7 Proceedings, March, 1980, page 12. 1–12.17.

Chetty, P.R.K., “Modeling and Design of Switching Regulators,” IEEE Transactions on Aerospace and Electric Systems,

May 1992, page 333–343.

Jamerson, C., and Hosseini, “A Simplified Procedure for Compensation Current-Mode Control Loops,” HFPC Proceed-

ings, June 1991, page 299–318.

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or design. ASTEC does not assume any liability arising out of the application or use of any product or circuit described herein; neither
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169

AS3842

Notes

Application Note 5

ASTEC Semiconductor

170