Datasheet AS29LV400T-70SC, AS29LV400T-70TI, AS29LV400T-70TC, AS29LV400T-70SI, AS29LV400B-70TI Datasheet (Alliance Semiconductor Corporation)

Preliminary Information

AS29LV400

March 2001

3V 512K x 8/256K × 16 CMOS Flash EEPROM

Features

• Organization: 512Kx8/256Kx16

• Sector architecture

- One 16K; two 8K; one 32K; and seven 64K byte sectors

- One 8K; two 4K; one 16K; and seven 32K word sectors

- Boot code sector architecture—T (top) or B (bottom)

- Erase any combination of sectors or full chip

• Single 2.7-3.6V power supply for read/write operations

• Sector protection

• High speed 70/80/90/120 ns address access time

• Automated on-chip programming algorithm

- Automatically programs/verifies data at specified address

• Automated on-chip erase algorithm

- Automatically preprograms/erases chip or specified
sectors

• Hardware

- Resets internal state machine to read mode

RESET

pin

®

• Low power consumption

- 200 nA typical automatic sleep mode current

- 200 nA typical standby current

- 10 mA typical read current

• JEDEC standard software, packages and pinouts

- 48-pin TSOP

- 44-pin SO; availabillity TBD

• Detection of program/erase cycle completion

-DQ7

DATA

polling

- DQ6 toggle bit

- DQ2 toggle bit
output

BY

-RY/

• Erase suspend/resume

- Supports reading data from or programming data to a

sector not being erased

•Low VCC write lock-out below 1.5V

• 10 year data retention at 150C

• 100,000 write/erase cycle endurance

Logic block diagram

Sector protect/

V

ESET

BYTE

CE

A-1

A0–A17

CC

V

SS

WE

OE

BY

RY/

Program/erase

control

Command

register

VCC detector

Timer

erase voltage

Erase voltage

Program voltage

generator

Output enable

STB

switc hes

generator

Chip enable

Logic

Y decoder Y gating

X decoder

Address latch

Selection guide

Maximum access time t

Maximum chip enable access time t

Maximum output enable access time t

Pin arrangement

48-pin TSOP

RESET

A1

14

15

16

1718192021

22

23

24

AS29LV40

35

34

33

3231302928

27

26

25

V

A0

CE

SS

OE

DQ0

DQ2

DQ10

DQ3

DQ11

DQ8

DQ1

VCCDQ4

DQ9

STB

DQ0–DQ15

Input/output

buffers

Data latch

Cell matrix

RY/ B Y

A17

NC

NC

NC

A7

A6A5A4A3A2

29LV400-70 29LV400-80 29LV400-90 29LV400-120 Unit

AA

CE

OE

70 80 90 120 ns

70 80 90 120 ns

30 30 35 50 ns

A10

A11

A12

A13

A14

WE

NC

NC

A8

A9

DQ12

DQ5

DQ6

DQ13

A15

12345678910111213

A6

A5

A4

A3

A2

A1

A0

CE

V

SS

OE

DQ0

DQ8

DQ1

DQ9

DQ2

48474645444342414039383736

DQ10

DQ3

DQ11

A16

BYTE

V

DQ15/A-1

DQ7

DQ14

SS

44-pin SO

1RY/ B Y

2NC

3A17

4A7

5

6

7

8

9

10

11

12

13

AS29LV40

14

15

16

17

18

19

20

21

22

44

RESET

43

WE

42

A8

41

A9

A10

40

A11

39

A12

38

A13

37

A14

36

A15

35

A16

34

33

BYTE

V

32

SS

31

DQ15/A-1

30

DQ7

29

DQ14

28

DQ6

27

DQ13

26

DQ5

25

DQ12

24

DQ4

23

V

CC

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Copyright © Alliance Semiconductor. All rights reserved.

March 2001

®

AS29LV400

Functional description

The AS29LV400 is an 4 megabit, 3.0 volt Flash memory organized as 512Kbyte of 8 bits/256Kbytes of 16 bits each. For
flexible Erase and Program capability, the 4 megabits of data is divided into eleven sectors: one 16K, two 8K, one 32K, and
seven 64k byte sectors; or one 8K, two 4K, one 16K, and seven 32K word sectors. The ×8 data appears on DQ0–DQ7; the ×16
data appears on DQ0–DQ15. The AS29LV400 is offered in JEDEC standard 48-pin TSOP. A 44-pin SOP package may be offered
in the future. This device is designed to be programmed and erased with a single 3.0V V
reprogrammed in standard EPROM programmers.

The AS29LV400 offers access times of 70/80/90/120 ns, allowing 0-wait state operation of high speed microprocessors. To
eliminate bus contention the device has separate chip enable
mode (×16 output) is selected by BYT E

= high. Byte mode (×8 output) is selected by B Y TE = low.

, write enable (WE), and output enable (OE) controls. Word

(CE)

The AS29LV400 is fully compatible with the JEDEC single power supply Flash standard. The device uses standard
microprocessor write timings to send Write commands to the register. An internal state-machine uses register contents to
control the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the Programming
and Erase operations. Data is read in the same manner as other Flash or EPROM devices. Use the Program command sequence
to invoke the on-chip programming algorithm that automatically times the program pulse widths, and verifies proper cell
margin. Use the Erase command sequence to invoke the automated on-chip erase algorithm that preprograms the sector when
it is not already programmed before executing the erase operation. The Erase command also times the erase pulse widths and
verifies the proper cell margins.

Boot sector architecture enables the system to boot from either the top (AS29LV400T) or the bottom (AS29LV400B) sector.
Sector erase architecture allows specified sectors of memory to be erased and reprogrammed without altering data in other
sectors. A sector typically erases and verifies within 1.0 seconds. Hardware sector protection disables both the Program and the
Erase operations in all, or any combination of the eleven sectors. The device provides true background erase with Erase
Suspend, which puts erase operations on hold to either read data from, or program data to, a sector that is not being erased.
The Chip Erase command will automatically erase all unprotected sectors.

When shipped from the factory, AS29LV400 is fully erased (all bits = 1). The programming operation sets bits to 0. Data is
programmed into the array one byte at a time in any sequence and across sector boundaries. A sector must be erased to change
bits from 0 to 1. Erase returns all bytes in a sector to the erased state (all bits = 1). Each sector is erased individually with no
effect on other sectors.

The device features a single 3.0V power supply operation for Read, Write, and Erase functions. Internally generated and
regulated voltages are provided for the Program and Erase operations. A low V
operations during power transtitions. The

BY pin, DATA polling of DQ7, or toggle bit (DQ6) may be used to detect the

RY /

CC

end of the program or to erase operations. The device automatically resets to the Read mode after the Program or Erase
operations are completed. DQ2 indicates which sectors are being erased.

The AS29LV400 resists accidental erasure or spurious programming signals resulting from power transitions. The Control
register architecture permits alteration of memory contents only when successful completion of specific command sequences
has occured. During power up, the device is set to Read mode with all Program/Erase commands disabled if V
V

(lockout voltage). The command registers are not affected by noise pulses of less than 5 ns on OE, CE,

LKO

Write commands, CE

When the device’s hardware RE S ET
state machine is reset to Read mode. If the R E SE T

and WE must be a logical zero and OE a logical 1.

pin is driven low, any Program/Erase operation in progress is terminated and the internal

pin is tied to the system reset circuitry and a system reset occurs during an
automated on-chip Program/Erase algorithm, the operating data in the address locations may become corrupted and require
rewriting. Resetting the device enables the system’s microprocessor to read boot-up firmware from the Flash memory.

The AS29LV400 uses Fowler-Nordheim tunnelling to electrically erase all bits within a sector simultaneously. Bytes are
programmed one at a time using the EPROM programming mechanism of hot electron injection.

supply. The device can also be

CC

detector automatically inhibits write

is less than

CC

WE. To initiate

or

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March 2001

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AS29LV400

Operating modes

Mode CE OE WE A0 A1 A6 A9 RESET DQ

ID read MFR codeLLHLLLV

ID read device code L L H H L L V

ID

ID

Read L L H A0 A1 A6 A9 H D

Standby HXXXXXXHHigh Z

Output disable L HHXXXXHHigh Z

Write L H L A0 A1 A6 A9 H D

Enable sector protect L V

Sector unprotect L V

Temporary sector
unprotect

Verify sector protect

Verify sector unprotect

XXXXXXXV

†

LLHLHLVIDHCode

†

LLHLHHVIDHCode

ID

ID

Pulse/L L H L V

ID

Pulse/LL HHVIDHX

Hardware Reset XXXXXXXLHigh Z

L = Low (<VIL) = logic 0; H = High (>VIH) = logic 1; VID = 10.0 ± 1.0V; X = don’t care.
In ×16 mode, BYTE = V

†

Verification of sector protect/unprotect during A9 = V

. In ×8 mode, BYTE = VIL with DQ8-DQ14 in high Z and DQ15 = A-1.

IH

ID.

HCode

HCode

OUT

IN

HX

ID

X

Mode definitions

Item Description

ID MFR code,
device code

Read mode

Selected by A9 = V
When A0 is low (V
When A0 is high (V

Selected with CE
and t

after O E is low.

OE

Selected with CE

Standby

If activated during an automated on-chip algorithm, the device completes the operation before entering
standby.

Output disable Part remains powered up; but outputs disabled with OE

Selected with CE

Write

register. Contents of command register serve as inputs to the internal state machine. Address latching occurs
on the falling edge of WE
whichever occurs first. Filters on WE

Enable
sector protect

Sector
unprotect

Ver if y s ec t or
protect/
unprotect

Hardware protection circuitry implemented with external programming equipment causes the device to
disable program and erase operations for specified sectors. For in-system sector protection, refer to Sector
protect algorithm on page 14.

Disables sector protection for all sectors using external programming equipment. All sectors must be
protected prior to sector unprotection. For in-system sector unprotection, refer to Sector unprotect algorithm
on page 14.

Verifies write protection for sector. Sectors are protected from program/erase operations on commercial
programming equipment. Determine if sector protection exists in a system by writing the ID read command
sequence and reading location XXX02h, where address bits A12–17 select the defined sector addresses. A
logical 1 on DQ0 indicates a protected sector; a logical 0 indicates an unprotected sector.

(9.5V–10.5V), CE = O E = A1 = A6 = L, enabling outputs.

ID

) the output data = 52h, a unique Mfr. code for Alliance Semiconductor Flash products.

IL

IH

), D

represents the device code for the AS29LV400.

OUT

= OE = L, WE = H. Data is valid in t

= H. Part is powered down, and ICC reduced to <1.0 µA when C E = VCC ± 0.3V = R ES E T.

= WE = L, OE = H

. Accomplish all Flash erasure and programming through the command

or CE , whichever occurs later. Data latching occurs on the rising edge WE or CE ,

prevent spurious noise events from appearing as write commands.

time after addresses are stable, tCE after CE is low

ACC

pulled high.

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March 2001

®

AS29LV400

Item Description

Te m p o ra r y
sector
unprotect

RESET

Deep
power down

Automatic
sleep mode

Temporarily disables sector protection for in-system data changes to protected sectors. Apply +10V to
RESET

to activate temporary sector unprotect mode. During temporary sector unprotect mode, program
protected sectors by selecting the appropriate sector address. All protected sectors revert to protected state on
removal of +10V from RES E T

.

Resets the interal state machine to read mode. If device is programming or erasing when RESET = L, data
may be corrupted.

Hold RESET

low to enter deep power down mode (<1 µA). Recovery time to start of first read cycle is 50ns.

Enabled automatically when addresses remain stable for 300ns. Typical current draw is 1 µA. Existing data is
available to the system during this mode. If an address is changed, automatic sleep mode is disabled and new
data is returned within standard access times.

Flexible sector architecture

Bottom boot sector architecture (AS29LV400B) Top boot sector architecture (AS29LV400T)

Size

Sector

0 00000h–03FFFh 00000h–01FFFh 16 00000h–0FFFFh 00000h–07FFFh 64

1 04000h–05FFFh 02000h–02FFFh 8 10000h–1FFFFh 08000h–0FFFFh 64

2 06000h–07FFFh 03000h–03FFFh 8 20000h–2FFFFh 10000h–17FFFh 64

3 08000h–0FFFFh 04000h–07FFFh 32 30000h–3FFFFh 18000h–1FFFFh 64

4 10000h–1FFFFh 08000h–0FFFFh 64 40000h–4FFFFh 20000h–27FFFh 64

5 20000h–2FFFFh 10000h–17FFFh 64 50000h–5FFFFh 28000h–2FFFFh 64

6 30000h–3FFFFh 18000h–1FFFFh 64 60000h–6FFFFh 30000h–37FFFh 64

7 40000h–4FFFFh 20000h–27FFFh 64 70000h–77FFFh 38000h–3BFFFh 32

8 50000h–5FFFFh 28000h–2FFFFh 64 78000h–79FFFh 3C000h–3CFFFh 8

9 60000h–6FFFFh 30000h–37FFFh 64 7A000h–7BFFFh 3D000h–3DFFFh 8

10 70000h–7FFFFh 38000h–3FFFFh 64 7C000h–7FFFFh 3E000h–3FFFFh 16

In word mode, there are one 8K word, two 4K word, one 16K word, and seven 32K word sectors. Address range is A17–A-1 if
is A17–A0 if

BYTE

×8 ×16

= VIH.

(Kbytes) ×8 ×16

= VIL; address range

BYTE

Size

(Kbytes)

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March 2001

®

AS29LV400

ID Sector address table

Bottom boot sector address

(AS29LV400B)

Sector

0 00000X 0 0 0XXX

1 000010 00 1XXX

2 000011 01 0XXX

3 0001XX 011XXX

4 001XXX 100XXX

5 010XXX 101XXX

6 011XXX 110XXX

7 100XXX 1110XX

8 101XXX 111100

9 110XXX 111101

10 111XXX 11111X

A17 A16 A15 A14 A13 A12 A17 A16 A15 A14 A13 A12

Top boot sector address

(AS29LV400T)

READ codes

Mode A17–A12 A6 A1 A0 Code

MFR code (Alliance Semiconductor) X L L L 52h

×8 T boot X L L H B9h

Device code

Sector protection Sector address L H L

Key: L =Low (<VIL); H = High (>VIH); X =Don’t care

×8 B boot X L L H BAh

×16 T boot X L L H 22B9h

×16 B boot X L L H 22BAh

01h protected
00h unprotected

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Command format

Required bus

Command sequence

Reset/Read 1 XXXh F0h

Reset/Read

Autoselect
ID Read

Program

Unlock bypass

Unlock bypass program 2 XXX A0h

Unlock bypass reset 2 XXX 90h XXX 00h

Chip Erase

Sector Erase

Sector Erase Suspend 1 XXXh B0h

Sector Erase Resume 1 XXXh 30h

×16

×8 AAAh 555h AAAh

×16

×8 AAAh 555h AAAh

×16 555h

×8 AAAh 555h AAAh 52h

×16 555h

×8 AAAh 555h AAAh

×16

×8 AAAh 555h AAAh

×16

×8 AAA 555 AAA

×16

×8 AAAh 555h AAAh AAAh 555h AAAh

×16

×8 AAAh 555h AAAh AAAh 555h

write cycles

3

3

4

3

6

6

1 Bus operations defined in "Mode definitions," on page 3.

2 Reading from and programming to non-erasing sectors allowed in Erase Suspend mode.

3 Address bits A11-A17 = X = Don’t Care for all address commands except where Program Address and Sector Address are required.

4 Data bits DQ15-DQ8 are don’t care for unlock and command cycles.

5 The Unlock Bypass command must be initiated before the Unlock Bypass Program command.

6 The Unlock Bypass Reset command returns the device to reading array data when it is in the unlock bypass mode.

1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle

Address Data Address Data Address Data Address Data Address Data Address Data

Read

Read Data

Address

555h

555h

555h

555

555h

555h

AAh

AAh

AAh

AAh

AAh

AAh

AAh

AAh

2AAh

2AAh

2AAh

2AAh

2AAh

2AA

Program

address

2AAh

2AAh

55h

55h

55h

55h

55h

55h

Program

data

55h

55h

555h

555h

555h

555h

555h

555

555h

555h

F0h Read Address

01h

90h

90h

90h

A0h Program Address Program Data

20h

80h

80h

Device code

02h

Device code

00h

MFR code

XXX02h

Sector protection

XXX04h

Sector protection

555h

555h

Read
Data

22B9h (T)
22BAh (B)

B9h(T)
BAh( B)

0052h

0001h = protected
0000h = unprotected

0001h=protected
0000h=unprotected

AAh

AAh

2AAh

2AAh

AS29LV400

555h

55h

Sector

55h

Address

10h

30h

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March 2001

Command definitions

Item Description

Initiate read or reset operations by writing the Read/Reset command sequence into the command
register. This allows the microprocessor to retrieve data from the memory. Device remains in read

Reset/Read

mode until command register contents are altered.

Device automatically powers up in read/reset state. This feature allows only reads, therefore
ensuring no spurious memory content alterations during power up.

AS29LV400 provides manufacturer and device codes in two ways. External PROM programmers
typically access the device codes by driving +10V on A9. AS29LV400 also contains an ID Read
command to read the device code with only +3V, since multiplexing +10V on address lines is
generally undesirable.

AS29LV400

®

ID Read

Hardware Reset

Byte/word
Programming

Initiate device ID read by writing the ID Read command sequence into the command register.
Follow with a read sequence from address XXX00h to return MFR code. Follow ID Read command
sequence with a read sequence from address XXX01h to return device code.

To verify write protect status on sectors, read address XXX02h. Sector addresses A17–A12 produce
a 1 on DQ0 for protected sector and a 0 for unprotected sector.

Exit from ID read mode with Read/Reset command sequence.

Holding RE SET
handled in the operation is corrupted. The internal state machine resets 20 µs after RE SET
driven low. RY/BY
is a delay of 50 ns for the device to permit read operations.

Programming the AS29LV400 is a four bus cycle operation performed on a byte-by-byte or word­by-word basis. Two unlock write cycles precede the Program Setup command and program data
write cycle. Upon execution of the program command, no additional CPU controls or timings are
necessary. Addresses are latched on the falling edge of CE
on the rising edge of C E
algorithm provides adequate internally-generated programming pulses and verifies the
programmed cell margin.

Check programming status by sampling data on the RY/BY
or toggle bit (DQ6) at the program address location. The programming operation is complete if
DQ7 returns equivalent data, if DQ6 = no toggle, or if RY/B Y

The AS29LV400 ignores commands written during programming. A hardware reset occurring
during programming may corrupt the data at the programmed location.

low for 500 ns resets the device, terminating any operation in progress; data

is

remains low until internal state machine resets. After RE SET is set high, there

or WE , whichever is last; data is latched

or WE , whichever is first. The AS29LV400’s automated on-chip program

pin, or either the DATA polling (DQ7)

pin = high.

AS29LV400 allows programming in any sequence, across any sector boundary. Changing data from
0 to 1 requires an erase operation. Attempting to program data 0 to 1 results in either DQ5 = 1
(exceeded programming time limits); reading this data after a read/reset operation returns a 0.
When programming time limit is exceeded, DQ5 reads high, and DQ6 continues to toggle. In this
state, a Reset command returns the device to read mode.

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March 2001

Item Description

The unlock bypass feature increases the speed at which the system programs bytes or words to the
device because it bypasses the first two unlock cycles of the standard program command sequence.

To initiate the unlock bypass command sequence, two unlock cycles must be written, then
followed by a third cycle which has the unlock bypass command, 20h.

The device then begins the unlock bypass mode. In order to program in this mode, a two cycle

Unlock Bypass
Command Sequence

unlock bypass program sequence is required. The first cycle has the unlock bypass program
command, A0h. It is followed by a second cycle which has the program address and data. To
program additional data, the same sequence must be followed.

The unlock bypass mode has two valid commands, the Unlock Bypass Program command and the
Unlock Bypass Reset command. The only way the system can exit the unlock bypass mode is by
issuing the unlock bypass reset command sequence. This sequence involves two cycles. The first
cycle contains the data, 90h. The second cycle contains the data 00h. Addresses are don’t care for
both cycles. The device then returns to reading array data.

Chip erase requires six bus cycles: two unlock write cycles; a setup command, two additional
unlock write cycles; and finally the Chip Erase command.

AS29LV400

®

Chip Erase

Sector Erase

Chip erase does not require logical 0s to be written prior to erasure. When the automated on-chip
erase algorithm is invoked with the Chip Erase command sequence, AS29LV400 automatically
programs and verifies the entire memory array for an all-zero pattern prior to erase. The 29LV400
returns to read mode upon completion of chip erase unless DQ5 is set high as a result of exceeding
time limit.

Sector erase requires six bus cycles: two unlock write cycles, a setup command, two additional
unlock write cycles, and finally the Sector Erase command. Identify the sector to be erased by
addressing any location in the sector. The address is latched on the falling edge of WE
command, 30h is latched on the rising edge of W E
erase time-out.

To erase multiple sectors, write the Sector Erase command to each of the addresses of sectors to
erase after following the six bus cycle operation above. Timing between writes of additional sectors
must be less than the erase time-out period, or the AS29LV400 ignores the command and erasure
begins. During the time-out period any falling edge of W E
(other than Sector Erase or Erase Suspend) during time-out period resets the AS29LV400 to read
mode, and the device ignores the sector erase command string. Erase such ignored sectors by
restarting the Sector Erase command on the ignored sectors.

The entire array need not be written with 0s prior to erasure. AS29LV400 writes 0s to the entire
sector prior to electrical erase; writing of 0s affects only selected sectors, leaving non-selected
sectors unaffected. AS29LV400 requires no CPU control or timing signals during sector erase
operations.

Automatic sector erase begins after sector erase time-out from the last rising edge of WE
sector erase command stream and ends when the DATA
address must be performed on addresses that fall within the sectors being erased. AS29LV400
returns to read mode after sector erase unless DQ5 is set high by exceeding the time limit.

. The sector erase operation begins after a sector

resets the time-out. Any command

polling (DQ7) is logical 1. DATA polling

; the

from the

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March 2001

Item Description

Erase Suspend allows interruption of sector erase operations to read data from or program data to a
sector not being erased. Erase suspend applies only during sector erase operations, including the
time-out period. Writing an Erase Suspend command during sector erase time-out results in
immediate termination of the time-out period and suspension of erase operation.

AS29LV400 ignores any commands during erase suspend other than Read/Reset, Program or Erase
Resume commands. Writing the Erase Resume Command continues erase operations. Addresses are
Don’t Care when writing Erase Suspend or Erase Resume commands.

AS29LV400 takes 0.2–15 µs to suspend erase operations after receiving Erase Suspend command.

Erase Suspend

Sector Protect

Ready/Busy

To determine completion of erase suspend, either check DQ6 after selecting an address of a sector
not being erased, or poll RY/BY
being erased. AS29LV400 ignores redundant writes of Erase Suspend.

While in erase-suspend mode, AS29LV400 allows reading data (erase-suspend-read mode) from or
programming data (erase-suspend-program mode) to any sector not undergoing sector erase;
these operations are treated as standard read or standard programming mode. AS29LV400 defaults
to erase-suspend-read mode while an erase operation has been suspended.

Write the Resume command 30h to continue operation of sector erase. AS29LV400 ignores
redundant writes of the Resume command. AS29LV400 permits multiple suspend/resume
operations during sector erase.

When attempting to write to a protected sector, DATA
for about <1 µs. When attempting to erase a protected sector, DATA
Toggle Bit 1 (DQ6) are activated for about <5 µs. In both cases, the device returns to read mode
without altering the specified sectors.

RY/ B Y

indicates whether an automated on-chip algorithm is in progress (RY/BY = low) or
completed (RY/B Y
RY/ B Y

= low. RY/BY= high when device is in erase suspend mode. RY/B Y = high when device
exceeds time limit, indicating that a program or erase operation has failed. RY/B Y
output, enabling multiple RY/BY

AS29LV400

®

. Check DQ2 in conjunction with DQ6 to determine if a sector is

polling and Toggle Bit 1 (DQ6) are activated

polling and

= high). The device does not accept Program/Erase commands when

is an open drain

pins to be tied in parallel with a pull up resistor to VCC.

Status operations

Only active during automated on-chip algorithms or sector erase time outs. DQ7 reflects

DATA

polling (DQ7)

Toggle bit 1 (DQ6)

Exceeding time limit
(DQ5)

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complement of data last written when read during the automated on-chip program algorithm (0
during erase algorithm); reflects true data when read after completion of an automated on-chip
program algorithm (1 after completion of erase agorithm).

Active during automated on-chip algorithms or sector erase time outs. DQ6 toggles when CE
OE

toggles, or an Erase Resume command is invoked. DQ6 is valid after the rising edge of the
fourth pulse of W E
erase; after the last rising edge of the sector erase WE
DQ6 toggles for <1 µs during program mode writes, and <5 µs during erase (if all selected sectors
are protected).

Indicates unsuccessful completion of program/erase operation (DQ5 = 1). DATA
active. If DQ5 = 1 during chip erase, all or some sectors are defective; during byte programming or
sector erase, the sector is defective (in this case, reset the device and execute a program or erase
command sequence to continue working with functional sectors). Attempting to program 0 to 1
will set DQ5 = 1.

during programming; after the rising edge of the sixth W E pulse during chip

pulse for sector erase. For protected sectors,

polling remains

or

March 2001

AS29LV400

®

Sector erase timer
(DQ3)

Toggle bit 2 (DQ2)

Checks whether sector erase timer window is open. If DQ3 = 1, erase is in progress; no commands
will be accepted. If DQ3 = 0, the device will accept sector erase commands. Check DQ3 before and
after each Sector Erase command to verify that the command was accepted.

During sector erase, DQ2 toggles with OE
erased. During chip erase, DQ2 toggles with OE

or C E only during an attempt to read a sector being

or CE for all addresses. If DQ5 = 1, DQ2 toggles
only at sector addresses where failure occurred, and will not toggle at other sector addresses. Use
DQ2 in conjunction with DQ6 to determine whether device is in auto erase or erase suspend
mode.

Write operation status

Status DQ7 DQ6 DQ5 DQ3 DQ2 RY/BY

Standard mode

Auto programming D Q

Program/erase in auto erase 0 Toggle 0 1 Toggle

Read erasing sector 1 No toggle 0 N/A Toggle 1

Erase suspend mode

Read non-erasing sector Data Data Data Data Data 1

Program in erase suspend DQ

Auto programming (byte) D Q

Exceeded time limits

Program/erase in auto erase 0 Toggle 1 N/A Toggle

Program in erase suspend
(non-erase suspended sector)

DQ2 toggles when an erase-suspended sector is read repeatedly.

DQ6 toggles when any address is read repeatedly.

DQ2 = 1 if byte address being programmed is read during erase-suspend program mode.

†

DQ2 toggles when the read address applied points to a sector which is undergoing erase, suspended erase, or a failure to erase.

7 Toggle 0 N/A No toggle 0

7 Toggle 0 N/A Toggle

7 Toggle 1 N/A No toggle 1

DQ

7 Toggle 1 N/A No toggle 1

†

0

†

0

†

1

3/20/01; V.0.9.3 Alliance Semiconductor P. 10 of 25

®

Automated on-chip programming algorithm Automated on-chip erase algorithm

AS29LV400March 2001

START

Write program command sequence

(see below)

DATA polling or toggle bit

successfully completed

Last

address?

YES

Programming completed

NO

Increment

address

Write erase command sequence

DATA polling or toggle bit

successfully completed

Chip erase command sequence

×16 mode (address/data):

555h/AAh

2AAh/55h

555h/80h

START

(see below)

Erase complete

Individual sector/multiple sector

erase command sequence

×16 mode (address/data):

555h/AAh

2AAh/55h

555h/80h

Program command sequence

×16 mode (address/data):

555h/AAh

2AAh/55h

555h/A0h

Program address/program data

555h/AAh

2AAh/55h

555h/10h

555h/AAh

2AAh/55h

Sector address/30h

Sector address/30h

Sector address/30h

optional sector erase commands

†

The system software should check the status of DQ3 prior to and following each
subsequent sector erase command to ensure command completion. The device may
not have accepted the command if DQ3 is high on second status check.

3/20/01; V.0.9.3 Alliance Semiconductor P. 11 of 25

Programming using unlock bypass command

START

Write unlock

bypass command

(3 cycles)

Write unlock

bypass program command

(2 cycles)

DATA polling or

toggle bit

successfully completed

AS29LV400March 2001

®

Unlock bypass command sequence

x16 mode (address/data)

555h/AAh

2AAh/55h

555h/20h

Unlock bypass program

command sequence

x16 mode (address/data)

xxxh/A0h

Last

address?

YES

Write unlock

bypass reset command

(2 cycles)

Programming completed

NO

Increment

address

program address/

program data

Unlock bypass reset

command sequence

x16 mode (address/data)

xxxh/90h

xxxh/00h

3/20/01; V.0.9.3 Alliance Semiconductor P. 12 of 25

DATA

polling algorithm

AS29LV400March 2001

®

Toggle bit algorithm

Read byte (DQ0–DQ7)

Address = VA

NO

Read byte (DQ0–DQ7)

Address = VA

DQ7

data

DQ5

DQ7

data

†

=

YES

DONE

?

NO

=
1

?

YES

Read byte (DQ0–DQ7)

Address = don’t care

DQ6

=

toggle

?

NO

DQ5

=

1

?

YES

YES

NO

DONE

Read byte (DQ0–DQ7)

Address = don’t care

†

=

YES

‡

DONE

?

DQ6

toggle

=

NO

†

DONE

?

†

NO

FAI L

†

VA = Byte address for programming. VA = any of the sector
addresses within the sector being erased during Sector Erase. VA
= valid address equals any non-protected sector group address
during Chip Erase.

‡

DQ7 rechecked even if DQ5 = 1 because DQ5 and DQ7 may not
change simultaneously.

YES

FAIL

†

DQ6 rechecked even if DQ5 = 1 because DQ6 may stop toggling

when DQ5 changes to 1.

3/20/01; V.0.9.3 Alliance Semiconductor P. 13 of 25

March 2001

®

Sector protect algorithm Sector unprotect algorithm

AS29LV400

Temporary sector

unprotect mode

Increment

PLSCNT

No

START

PLSCNT = 1

RESET# = V

Wait 1 µs

No

First Write

Cycle=60h?

Set up sector

address

Sector protect:

write 60h to sector

address with

A6=0, A1=1,

A0=0

Wait 150 µs

Verify sector

protect; write 40h

to sector address

with A6=0,

A1=1, A0=0

Read from sector

address with A6=0,

A1=1, A0=0

START

PLSCNT = 1

No

RESET# = V

Wait 1 µs

First Write
Cycle=60h?

All sectors

protected?

Sector unprotect:

write 60h to sector

address with

A6=1, A1=1,

A0=0

Wait 15 ms

Set up first

sector address

Verify sector

unprotect; write 40h

to sector address

with A6=1,

A1=1, A0=0

ID

Yes

Yes

No

Temporary sector

unprotect mode

ID

Protect all sectors:

The shaded portion of

the sector protct

Yes

algorithm must be

initiated for all

unprotected sectors

before calling the

sector unprotect

Increment

PLSCNT

PLSCNT=25?

Device failed

No

Data=01h?

Protect
another

sector?

Remove V

from RESET#

Write reset

command

Sector protect

complete

Yes

Yes

No

ID

Yes

No

PLSCNT

=1000?

Yes

Device failed

Read from sector

address with A6=1,

A1=1, A0=0

No

Data=00h?

Last sector

verified?

Remove V

from RESET#

Write reset

command

Sector unprotect

complete

Set up next

sector address

Yes

No

Ye s

ID

3/20/01; V.0.9.3 Alliance Semiconductor P. 14 of 25

March 2001

AS29LV400

®

DC electrical characteristics

VCC = 2.7–3.6V

Parameter Symbol Test conditions Min Max Unit

Input load current I

A9 Input load current I

Output leakage current I

Active current, read @ 5MHz I

Active current, program/erase I

Automatic sleep mode

*

Standby current I

Deep power down current

3

Input low voltage V

Input high voltage V

Output low voltage V

Output high voltage V

Low V

lock out voltage V

CC

I

I

LI

LIT

LO

CC1

CC2

CC3

SB

PD

IL

IH

OL

OH

LKO

VIN = VSS to VCC, VCC = V

VCC = V

V

= VSS to VCC, VCC = V

OUT

CE = VIL, OE = V

CE = VIL, OE = V

, A9 = 10V 35 µA

CC MAX

IH

IH

CC MAX

CC MAX

CE = VIL, OE = VIH;
V

= 0.3V, VIH = VCC - 0.3V

IL

CE = VCC - 0.3V, RE SET = VCC - .3V - 5 µA

RESET = 0.3V - 5 µA

IOL = 4.0mA, VCC = V

IOH = -2.0 mA, VCC = V

CC MIN

CC MIN

-±1µA

-±1µA

-20mA

-100mA

-5µA

-0.5 0.8 V

0.7×V

CC

VCC + 0.3 V

-0.45V

0.85×V

-V

CC

1.5 - V

Input HV select voltage V

* Automatic sleep mode enables the deep power down mode when addresses are stable for 150 ns. Typical sleep mode current is 200 nA.

ID

911V

3/20/01; V.0.9.3 Alliance Semiconductor P. 15 of 25

March 2001

AC parameters — read cycle

JEDEC
Symbol Std Symbol Parameter

t

AVAV

t

AV Q V

t

ELQV

t

GLQV

t

EHQZ

t

GHQZ

t

AXQX

t

PHQV

t

RC

t

ACC

t

CE

t

OE

t

OES

t

DF

t

DF

t

OH

t

OEH

t

RH

t

READY

t

RP

Read cycle time 70 80 - 90 - 120 - ns

Address to output delay - 70 - 80 - 90 - 120 ns

Chip enable to output - 70 - 80 - 90 - 120 ns

Output enable to output - 30 - 30 - 35 - 50 ns

Output enable setup time 0 - 0 - 0 - 0 - ns

Chip enable to output High Z - 20 - 20 - 30 - 30 ns

Output enable to output High Z - 20 - 20 - 30 - 30 ns

Output hold time from addresses,
first occurrence of CE

Output enable hold time: Read 10 - 10 - 10 - 10 - ns

Output enable hold time:
Toggle and data polling

RESET high to output delay - 50 - 50 - 50 - 50 ns

RESET pin low to read mode - 10 - 10 - 10 - 10 µs

RESET pulse 500 500 - 500 - 500 - ns

or OE

AS29LV400

®

-70 -80 -90 -120

UnitMin Max Min Max Min Max Min Max

0-0-0-0- ns

10 - 10 - 10 - 10 - ns

Read waveform

Addresses

CE

OE

WE

Outputs

RESET

t

RC

Addresses stable

t

ACC

t

t

OE

t

OEH

t

CE

High Z High Z

t

RH

Output valid

t

OH

DF

t

OES

3/20/01; V.0.9.3 Alliance Semiconductor P. 16 of 25

March 2001

AC parameters — write cycle

JEDEC
Symbol Std Symbol Parameter

t

AVAV

t

AV WL

t

WLAX

t

DVW H

t

WHDX

t

GHWL

t

ELWL

t

WHEH

t

WLWH

t

WHWL

t

WC

t

AS

t

AH

t

DS

t

DH

t

GHWL

t

CS

t

CH

t

WP

t

WPH

Write cycle time 70 - 80 - 90 - 120 - ns

Address setup time 0 - 0 - 0 - 0 - ns

Address hold time 45 - 45 - 45 - 50 - ns

Data setup time 35 - 35 - 45 - 50 - ns

Data hold time 0 - 0 - 0 - 0 - ns

Read recover time before write 0 - 0 - 0 - 0 - ns

CE

setup time

CE

hold time

Write pulse width 35 - 35 - 35 - 50 - ns

Write pulse width high 30 - 30 - 30 - 30 - ns

Write waveform

AS29LV400

®

WE

controlled

-70 -80 -90 -120

UnitMin Max Min Max Min Max Min Max

0-0-0-0-ns

0-0-0-0-ns

WE

controlled

Addresses

CE

OE

WE

DATA

3rd bus cycle

t

WC

555h Program address Program address

t

CH

t

GHWL

t

CS

A0h

t

AS

t

AH

; t

OES

t

WP

t

WPH

t

DH

Program

t

DS

data

t

WHWH1 or 2

DATA polling

7D

DQ

OUT

3/20/01; V.0.9.3 Alliance Semiconductor P. 17 of 25

March 2001

AC parameters — write cycle 2

JEDEC
Symbol Std Symbol Parameter

t

AVAV

t

AV EL

t

ELAX

t

DVE H

t

EHDX

t

GHEL

t

WLEL

t

EHWH

t

ELEH

t

EHEL

t

WC

t

AS

t

AH

t

DS

t

DH

t

GHEL

t

WS

t

WH

t

CP

t

CPH

Write cycle time 70 - 80 - 90 - 120 - ns

Address setup time 0 - 0 - 0 - 0 - ns

Address hold time 45 - 45 - 45 - 50 - ns

Data setup time 35 - 35 - 45 - 50 - ns

Data hold time 0 - 0 - 0 - 0 - ns

Read recover time before write 0 - 0 - 0 - 0 - ns

WE

setup time 0 - 0 - 0 - 0 - ns

WE

hold time 0 - 0 - 0 - 0 - ns

CE

pulse width 35 - 35 - 35 - 50 - ns

CE

pulse width high 30 - 30 - 30 - 30 - ns

AS29LV400

®

-70 -80 -90 -120

CE

controlled

UnitMin Max Min Max Min Max Min Max

Write waveform 2

Addresses

WE

OE

CE

DATA

CE controlled

DATA polling

Program address555h Program address

t

t

WC

t

t

t

AS

, t

t

GHEL

OES

CP

t

CPH

A0h

DS

AH

t

DH

Program

data

t

WHWH1 or 2

7D

DQ

OUT

3/20/01; V.0.9.3 Alliance Semiconductor P. 18 of 25

March 2001

AC parameters — temporary sector unprotect

JEDEC
Symbol

Std
Symbol Parameter

t

VIDR

t

RSP

VID rise and fall time

RESET

temporary sector unprotect

setup time for

500 - 500 - 500 - 500 - ns

4-4-4-4-µs

Temporary sector unprotect waveform

RESET

CE

10V

0 or 3V

t

VIDR

Program/erase command sequence

®

-70 -80 -90 -120

t

VIDR

0 or 3V

AS29LV400

UnitMin Max Min Max Min Max Min Max

WE

RY/BY

AC parameters —

JEDEC
Symbol

RESET

Std
Symbol Parameter

t

RP

t

RH

t

READY

waveform

RESET

RY /B Y

DQ

RESET

RESET

Read

RESET

Erase waveform

Addresses

CE

OE

WE

Data

t

RSP

RESET

-70 -80 -90 -120

pulse

High time before

Low to Read mode

t

RP

t

READY

t

WC

555h 2AAh 555h 555h 2AAh Sector address

t

WP

t

CS

t

DS

t

AS

t

GHWL

t

WPH

AAh 55h 80h AAh 55h 30h

500 - 500 - 500 - 500 - ns

- 50 - 50 - 50 - 50 ns

- 10 - 10 - 10 - 10 µs

t

RP

t

AH

t

WC

t

DH

UnitMin Max Min Max Min Max Min Max

t

RH

valid dat avalid datastatusstatus

×16 mode

10h for Chip Erase

3/20/01; V.0.9.3 Alliance Semiconductor P. 19 of 25

March 2001

AC Parameters — READY/BUSY

JEDEC
Symbol Std Symbol Parameter

-t

VCS

-t

RB

-t

BUSY

VCC setup time

Recovery time from RY/BY

Program/erase valid to RY/BY delay

RY/BY waveform

CE

AS29LV400

®

-70 -80 -90 -120

50 - 50 - 50 - 50 -

0-0-0-0-

90 - 90 - 90 - 90 -

UnitMin Max Min Max Min Max Min Max

µs

ns

ns

WE

RY /BY

V

CC

t

DATA

polling waveform

CE

OE

WE

DQ7

Input DQ7 Output

Toggle bit waveform

VCS

Rising edge of last WE signal

Program/erase

tri-stated open-drain

t

CH

t

OE

t

OEH

t

CE

t

BUSY

t

OH

DQ7Output

t

WHWH1 or 2

operation

t

DF

High Z

t

RB

CE

t

OEH

WE

OE

DQ6

t

DH

3/20/01; V.0.9.3 Alliance Semiconductor P. 20 of 25

t

OE

toggletoggle no toggle

March 2001

Word/byte configuration

JEDEC
Symbol Std Symbol Parameter

-t

ELFL/tELFH

-t

FLQZ

-t

FHQZ

BYTE

read waveform

Wo r d

to

Byte

Byte

to

Wo r d

DQ0-DQ14

DQ15/A-1

DQ0-DQ14

DQ15/A-1

CE

OE

BYTE

BYTE

BYTE

CE

to BYTE switching Low or High

BYTE

switching Low to output High-Z

BYTE

switching High to output Active

t

t

ELFL

ELFH

®

-70 -80 -90 -120

- 10 - 10 - 10 - 10 ns

- 30 - 30 - 35 - 40 ns

70 - 80 - 90 - 120 -

DQ0-DQ14

Data output

t

FLQZ

DQ0-DQ7

Data output

Address input DQ15 output

t

FHQV

DQ0-DQ14
Data output

DQ0-DQ7

Data output

Address inputDQ15 output

AS29LV400

UnitMin Max Min Max Min Max Min Max

ns

BYTE

write waveform

CE

WE

BYTE

See Erase/Program operations table for tAS and tAH specifications.

Sector protect/unprotect

V

ID

V

RESET#

SA, A6,
A1, A0

DATA

CE#

WE#

IH

1 µs

falling ed ge of last WE signal

t

SET

(tAS)t

Don’t care Don’t care Don’t care

Sector protect/unprotect

Valid* Valid* Valid*

60h 40h Status60h

Sector protect: 100 µs
Sector unprotect: 10 ms

Verify

HOLD

(tAH)

Don’t careDon’t care

OE#

* For sector protect, A6=0, A1=1, A0=0. For sector unprotect, A6=1, A1=1, A0=0.

3/20/01; V.0.9.3 Alliance Semiconductor P. 21 of 25

March 2001

®

AS29LV400

AC test conditions

+3.0V

1N3064

Device under test

CL*

V

SS

or equivalent

Ω

6.2K

V

SS

V

SS

Ω

2.7K

1N3064
or equivalent

Test specifications

-70,

Test Condition

-80

Output Load

Output Load Capacitance C

Input Rise and Fall Times 5 ns

Input Pulse Levels 0.0-3.0 V

Input timing measurement reference levels 1.5 V

Output timing measurement reference levels 1.5 V

(including jig capacitance) 30 100 pF

L

-90,

-120 Unit

1 TTL gate

Erase and programming performance

Limits

Parameter

Sector erase and verify-1 time (excludes 00h programming
prior to erase)

-

1.0 15 sec

Byte - 10 300 µs

Programming time

Wo r d - 1 5 3 6 0 µ s

Chip programming time - 7. 2

Erase/program cycles

* Erase/program cycle test is not verified on each shipped unit.

*

- 100,000 - cycles

27 sec

Latchup tolerance

Parameter Min Max Unit

Input voltage with respect to

Input voltage with respect to

Current -100 +100 mA

Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.

V

SS

V

SS

on A9,

OE, and R E SE T pin

on all DQ, address, and control pins

-1.0 +12.0 V

-0.5

VCC

+0.5

V

UnitMin Typical Max

3/20/01; V.0.9.3 Alliance Semiconductor P. 22 of 25

March 2001

®

AS29LV400

Recommended operating conditions

Parameter Symbol Min Max Unit

Supply voltage

Input voltage

V

CC

V

SS

V

IH

V

IL

+2.7 +3.6 V

00V

1.9 V

+ 0.3 V

CC

–0.5 0.8 V

Absolute maximum ratings

Parameter Symbol Min Max Unit

Input voltage (Input or DQ pin) V

Input voltage (A9 pin, OE

, RE S ET )VIN–0.5 +12.5 V

Power supply voltage V

Operating temperature T

Storage temperature (plastic) T

Short circuit output current I

Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute max­imum rating conditions for extended periods may affect reliability.

IN

CC

OPR

STG

OUT

–0.5 VCC+ 0.5 V

-0.5 +4.0 V

–55 +125 °C

–65 +150 °C

- 150 mA

TSOP pin capacitance

Symbol Parameter Test setup Typ Max Unit

C

C

C

IN

OUT

IN2

Input capacitance VIN = 0 6 7.5 pF

Output capacitance V

= 0 8.5 12 pF

OUT

Control pin capacitance VIN = 0 8 10 pF

SO pin capacitance

Symbol Parameter Test setup Typ Max Unit

C

C

C

IN

OUT

IN2

Input capacitance VIN = 0 6 7.5 pF

Output capacitance V

= 0 8.5 12 pF

OUT

Control pin capacitance VIN = 0 8 10 pF

Data retention

Parameter Temp.(°C) Min Unit

Minimum pattern data retention time

150° 10 years

125° 20 years

3/20/01; V.0.9.3 Alliance Semiconductor P. 23 of 25

March 2001

AS29LV400

®

hin small outline package (TSOP-I)

ackage dimensions

c

L

pin 1 pin 48

pin 24 pin 25

48-pin

α

Small Outline Plastic (SO)

Package dimensions

JEDEC MO - 175 AA

44-pin SO

Min (mm) Max (mm)

A–3.1

A1 0.05 –

A2 2.5 2.9

b0.250.45

c0.09

d 28.0 28.4

e 12.4 12.8

E 1.27 (typical)

He 16.05 (typical)

l0.731.3

0.25

A1AA2

44 43 42 41 40 39 38 37 36 35 34 33 32 31

SO

1234567891011121314

d

A

A

1

b

E

b

E

30 29

15 16

28 27 26 25

17 18 19 20

e

48-pin
12×20

Min Max

c

0–10°

l

D

212422

A

A – 1.27

A1 0.05 0.15

A2 0.95 1.05

Hd

23

H

e

2

b0.170.27

c 0.15 nominal

D 18.20 18.60

e 0.50 nominal

E 11.90 12.10

Hd 19.80 20.20

L0.500.70
α 0° 5°

e

3/20/01; V.0.9.3 Alliance Semiconductor P. 24 of 25

®

AS29LV400 ordering codes

70 ns (commercial/

Package \ Access Time

TSOP, 12×20 mm, 48-pin
Top boot configuration

TSOP, 12×20 mm, 48-pin
Bottom boot configuration

SO, 13.3 mm, 44-pin
Top boot configuration

SO, 13.3 mm, 44-pin
Bottom boot configuration

industrial)

AS29LV400T-70TC
AS29LV400T-70TI

AS29LV400B-70TC
AS29LV400B-70TI

AS29LV400T-70SC
AS29LV400T-70SI

AS29LV400B-70SC
AS29LV400B-70SI

Shaded area indicates advance information. Avialability of SO package is TBD.

80 ns (commercial/
industrial)

AS29LV400T-80TC
AS29LV400T-80TI

AS29LV400B-80TC
AS29LV400B-80TI

AS29LV400T-80SC
AS29LV400T-80SI

AS29LV400B-80SC
AS29LV400B-80SI

90 ns (commercial/
industrial)

AS29LV400T-90TC
AS29LV400T-90TI

AS29LV400B-90TC
AS29LV400B-90TI

AS29LV400T-90SC
AS29LV400T-90SI

AS29LV400B-90SC
AS29LV400B-90SI

120 ns (commercial/
industrial)

AS29LV400T-120TC
AS29LV400T-120TI

AS29LV400B-120TC
AS29LV400B-120TI

AS29LV400T-120SC
AS29LV400T-120SI

AS29LV400B-120SC
AS29LV400B-120SI

AS29LV400 part numbering system

AS29LV 400 X –XXX X X X

3V Flash
EEPROM
prefix

Device
number

T= Top boot configuration
B= Bottom boot configuration

Address
access time

Package:
S= SO

T= TSOP

Temperature range:
C = Commercial: 0°C to 70°C
I = Industrial: -40°C to 85°C

AS29LV400March 2001

Options:
B = Burn-in
H= High I
Blank= Standard

(<1mA)

SB

3/20/01; V.0.9.3 Alliance Semiconductor P. 25 of 25

© Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and pr oduct names may
be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that
may appear in this document. The data contained herein represents Alliance’s best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at a ny time, without
notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information
for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer . All iance does not assume any responsibility or liability arising out of the appli­cation or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular
purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance’s Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance
products are made exclusively according to Alliance’s Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights, mask works rights,
trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure
may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees