Datasheet AS29LV400T-120TI, AS29LV400T-120TC, AS29LV400T-120SI, AS29LV400T-120SC, AS29LV400R-90TI Datasheet (Alliance Semiconductor Corporation)

Advanced Information
January 2001

Copyright © Alliance Semiconductor. All rights reserved.

®

AS29LV400

12/21/00 Alliance Semiconductor 1

3V 512Kx8/256K×16 CMOS Flash EEPROM

Features

• Organization: 512Kx8/256K x1 6

• Sector arc hitecture

- One 16K; two 8K; one 3 2K ; and seven 64K byte sectors

- One 8K; two 4K; one 1 6K ; an d seven 32K word sectors

- Boot code sector architecture— T (top ) or B (bottom )

- Erase any combination of sectors or full chip

• Single 2.7-3.6V power supply for read/write operations

• Secto r protection

• High speed 80/90/120 ns address access time

• Automated on-chip programming alg ori thm

- Automatically programs/verifies data at specified address

• Automated on -ch ip erase algorithm

- Automatically preprograms/erases chip or specified
sectors

• Hardware RESET

pin

- Resets internal state machine to read m od e

• Low power consumption

- 200 nA typical automatic sleep mode current

- 200 nA typical standby current

- 10 mA typical read current

• JEDEC standard software, packages and pinouts

- 48-pin TSOP

- 44-pin SO

• Detection of program/erase cycle completion

-DQ7 DATA

polling

-DQ6 toggle bit

-DQ2 toggle bit

-RY/BY

output

• Erase suspe nd /re sum e

- Supports reading d ata from o r programm ing data to a
sector not being erased

•Low V

CC

write lock-out below 1.5V

• 10 year data retention at 150C

• 100,000 write/erase cycle endurance

Logic block diagram

X decoder

V

CC

V

SS

Cell matrix

Y decoder Y gating

Data latch

Chip enable

Address l a t ch

Input/output

buffers

Sector protect/

Command

register

Program/erase

control

VCC detector

Erase voltage

generator

Program voltage

generator

Timer

A0–A17

CE

OE

STB

STB

Output enable

Logic

RY/BY

WE

RESET

DQ0–DQ15

switches

erase voltage

BYTE

A-1

Pin arrangement

5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

A14
A15
A16
BYTE
V

SS

DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V

CC

A6
A5
A4
A3
A2
A1
A0
CE
V

SS

OE
DQ0
DQ8
DQ1
DQ9
DQ2

DQ10

44-pin SO

21
22

DQ3

DQ11

A10
A11
A12
A13

2NC
3A17
4A7

1RY/BY

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

43
42
41

44

WE
A8
A9

RESET

A8

A9

A10

A11

A12

A13

A14

A15 A16

BYTE

VSSDQ15/A-1

DQ7

DQ14

NC

NC

WE

RESET

NC

NC

RY/BY

NC DQ2

DQ10

DQ3

DQ11

VCCDQ4

DQ12

DQ5

DQ6

DQ13

12345678910111213

14

48474645444342414039383736

35

15

16

34

33

48-pin TSOP

A17

A7

A6A5A4A3A2

A1 A0

CE

VSSOE

DQ0

DQ8

DQ1

DQ917

1819202122

3231302928

27

23

24

26

25

AS29LV400

AS29LV400

Selection guide

29LV400-80 29LV400-90 29LV400-120 Unit

Maximum access time t

AA

80 90 120 ns

Maximum chip enable access time t

CE

80 90 120 ns

Maximum output enable access time t

OE

30 35 50 ns

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AS29LV400

January 2001

Alliance Semiconductor 2

Functional description

The AS29LV400 is an 4 megabit, 3.0 volt only Flash memory organized as 512Kbyte of 8 bits/256Kbytes of 16 bits each. For
flexible era se and p rogram cap ability, the 4 megabits of data i s divide d into eleven sectors: o ne 16K , two 8K, one 32K, and
seven 64k byte sectors; or one 8K, two 4K, one 16K, and seven 32K word sectors. The ×8 data appears on DQ0–DQ7; the ×16
data appears on DQ0–DQ15. The AS29L V 400 is off ere d in JED EC stand ard 48-p in T SOP and 44-pin SOP packa g es. This device
is designed to be progra mmed a nd e ras ed in-s ys tem wit h a sin gl e 3.0 V V

CC

supply. The device can al so be re progr ammed in

standard EPROM programmers.
The AS29LV400 offers access times of 80/90/120 ns, allowing 0-wait state operation of high speed microprocessors. To

eliminate bus contention the device has separate chip enable (CE

), write e nable (WE), and output enable (OE) controls. Word

mode (×16 output) is selected by BYTE

= high and Byte mode (×8 output) is selected by BYTE = low.

The AS29LV400 is fully compatible with the JEDEC single power supply Flash standard. Write commands to the command
register using st anda rd mi cr oprocessor write timings. An inter nal stat e-m achine uses re gist er co nte nts t o control the erase and
programming ci rcuitry. Write cycles also internally latch add resses and data needed for the programming and erase operations.
Read data from t he device in the sam e manner as other Fla sh or EPROM devices. Use the progr am command sequen ce to
invoke the automated on-chip progra mming algorithm that automatically times the program pulse widths and verifies proper
cell margin. Use the erase command sequence to invoke the automated on-chip erase algorithm that preprograms the sector if
it is not already programmed before executing the erase operation, times the erase pulse widths, and verifies proper cell
margin.

Boot sector architecture enables the system to boot from either the top (AS29LV400T) or the bottom (AS29LV400B) sector.
Sector erase architec ture allows specifie d sectors of mem ory to be era sed and reprogra mmed without al tering data in other
sectors. A sect or typic al ly erases an d ver ifies wit h in 1.0 seconds. Hardware sector protection disables both program and erase
operations in all or a ny combination of the eleven sectors. The device provides tru e background erase wit h Erase Suspend,
which p uts erase operation s on h old to e ither read data from or prog ram data t o a se ctor th at is not being erased. The c hip
erase command will automatically erase all unprotected sectors.

A factory shipped AS29LV400 is fully erased (all bits = 1). The programming operation sets bits to 0. Data is programmed into
the array on e byte at a time i n any sequence and across sector boundaries. A sector must be erased to change bits from 0 to 1.
Erase returns all bytes in a sector to the erased state (all bits = 1). Each sector is erased individually with no effect on other
sectors.

The device features single 3.0V power supply operation for read, write, and erase functions. Internally generated and regulated
voltages are provided for the program and erase operations. A low V

CC

detector automatically inhibits write operations during

power transtitions. The RY/BY

pin, DATA polling of DQ7, or toggle bit (DQ6) may be used to detect end of program or erase
operations. The device automatically resets t o the read mode after p rogram/erase operation s are completed. DQ2 indicates
which sectors are being erased.

The AS29LV400 resists accidental erasure or spurious programming signals resulting from power transitions. Control register
architecture permits alteration of memory contents only after successful completion of specific command sequences. During
power up, the device is s et to rea d mode with all prog ram/erase com mands dis abled when V

CC

is les s than V

LKO

(lockout

voltage). The command registers are not affected by noise pulses of less than 5 ns on OE

, CE, or WE. To initiate wr ite

commands, CE

and WE must be logical zero and OE a logical one.

When the device’s hardware R ES ET

pin is driven low, any program/erase operati on in progress is ter mi nated and th e int er nal

state mach ine is reset to read mode. If the RESET

pin is tied to the system reset circuitry and a system reset occurs during an
automated on-chip program/erase algorithm, data in address locations being operated on may become corrupted and requires
rewriting. Resetting the device enables the system’s microprocessor to read boot-up firmware from the Flash memory.

The AS29LV400 uses Fowler-Nordheim tunnelling to electrically erase all bits within a sector simultaneously. Bytes are
programmed one at a time usin g EPROM progr amming mechanism of ho t electron injection.

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AS29LV400

January 2001

Alliance Semiconductor 3

Operating modes

L = Low (<VIL) = logic 0; H = High (>VIH) = logic 1; VID = 10.0 ± 1.0 V; X = don’t car e.
In ×16 mode, BYTE = V

IH

. In ×8 mode, BYTE = VIL with DQ8-DQ14 in high Z and DQ15 = A-1.

†

Verification of sector protect/unprotect during A9 = V

ID.

Mode definitions

Mode CE OE WE A0 A1 A6 A9 RESET DQ

ID read MFR codeLLHLLLV

ID

H Code

ID read device code L L H H L L V

ID

H Code

Read L L H A0A1A6A9H D

OUT

Standby HXXXXXXHHigh Z
Output disable LHHXXXXHHigh Z
Write L H L A0 A1 A6 A9 H D

IN

Enable sector protect L V

ID

Pulse/L L H L V

ID

HX

Sector unprotect L V

ID

Pulse/LL HHVIDHX

Temporary sector
unprotect

XXXXXXXV

ID

X

Verify sector prote c t

†

L L HLHL VIDH Code

Verify secto r un p rotect

†

L L HLHHVIDH Code

Hardware Reset XXXXXXXLHigh Z

Item Description

ID MFR code,
device code

Selected by A9 = V

ID

(9.5V–10.5V), CE = OE = A1 = A6 = L, enabling outputs.

When A0 is low (V

IL

) the output data = 52h, a unique Mfr . cod e for Allian ce Semicondu ctor Flash pro duct s .

When A0 is high (V

IH

), D

OUT

represents the device code for the AS29LV400.

Read mo de

Selected with CE

= OE = L, WE = H. Data is valid in t

ACC

time after addresses are stable, tCE after CE is low

and t

OE

after OE is low.

Standby

Selected with CE

= H. Part is powered down, and ICC reduced to <1.0 µA when CE = VCC ± 0.3V = RESET . If
activated during an automated on-chip algorithm, the device completes the operation before entering
standby.

Output disable Part remains powered up; but outputs disabled with OE

pulled high.

Write

Selected with CE

= WE = L, OE = H. Accomplish al l Flash erasure and programm ing throug h the command
register. Contents of command r egi s ter ser ve a s input s to the internal state machine. A ddress latching occurs
on the falling edge of WE

or CE, whichever occurs later. Data latching occurs on the rising edge WE or CE,

whichever occurs first. Filters on WE

prevent spurious noise events from appearing as write commands.

Enable
sector prot ect

Hardware protection circuitry implemented with external programmin g equipment cause s the device to
disable program and erase operations for specified sectors. For in-system sector protection, refer to Sector
protect algorithm on page 14.

Sector
unprotect

Disables sector protection for all sectors using external programming equipment. All sectors must be
protected prior to sector unprotection. For in-system sector unprotection, refer to Sector unprotect
algorithm on page 14.

Verify secto r
protect/
unprotect

Verifies write protection for sector. Sectors are protected from program/erase operations on commercial
programming equipment. Determine if sector protection exists in a system by writing the ID read command
sequence and reading location XXX02h, where address bi ts A1 2–17 select the defined sector addresses. A
logical 1 on DQ0 indicates a protected sect or; a logi cal 0 indicat es an unprotect ed sector.

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AS29LV400

January 2001

Alliance Semiconductor 4

Flexible sector architecture

In word mode, there are one 8K word, two 4K word, one 16K word, and seven 32K word sectors. Address range is A17–A-1 if BYTE = VIL; address range is
A17–A0 if BYTE

= VIH.

Temporary
sector
unprotect

Temporarily d isables sect or p r o tecti o n for in-system da ta chan ge s to prot ecte d sect o rs. Apply +10V to RESET
to activate temporary sector unprotect mode. During temporary sector unprotect mode, program protected
sectors by selecting the appropriate sector address. All protected sectors revert to protected state on removal
of +10V from RESE T

.

RESET

Resets the interal state machine to read mode. If device is programming or erasing when RESET = L, data
may be corrupted.

Deep
power down

Hold RE S E T

low to enter deep power down mode (<1 µA). Recovery time to start of first read cycle is 50ns.

Automatic
sleep mode

Enabled automatically when addresses remain stable for 300ns. Typical current draw is 1 µA. Existing data is
available to the system during this mode. If an address is changed, automatic sleep mode is disabled and new
data is returned within standard access ti me s .

Sector

Bottom boot sector ar chitecture (AS29 LV400B) Top boot sector arc hi t e ctur e (AS29LV400T)

×8 ×16

Size

(Kbytes) ×8 ×16

Size

(Kbytes)

0 00000h–03FFFh 00000h–01FFFh 16 00000h–0FFFFh 00000h–07FFFh 64
1 04000h–05FFFh 02000h–02FFFh 8 10000h–1FFFFh 08000h–0FFFFh 64
2 06000h–07FFFh 03000h–03FFFh 8 20000h–2FFFFh 10000h–17FFFh 64
3 08000h–0FFFFh 04000h–07FFFh 32 30000h–3FFFFh 18000h–1FFFFh 64
4 10000h–1FFFFh 08000h–0FFFFh 64 40000h–4FFFFh 20000h–27FFFh 64
5 20000h–2FFFFh 10000h–17FFFh 64 50000h–5FFFFh 28000h–2FFFFh 64
6 30000h–3FFFFh 18000h–1FFFFh 64 60000h–6FFFFh 30000h–37FFFh 64
7 40000h–4FFFFh 20000h–27FFFh 64 70000h–77FFFh 38000h–3BFFFh 32
8 50000h–5FFFFh 28000h–2FFFFh 64 78000h–79FFFh 3C000h–3CFFFh 8
9 60000h–6FFFFh 30000h–37FFFh 64 7A000h–7BFFFh 3D000h–3DFFFh 8

10 70000h–7FFFFh 38000h–3FFFFh 64 7C000h–7FFFFh 3E000h–3FFFFh 16

Item Description

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AS29LV400

January 2001

Alliance Semiconductor 5

ID Sector address table

READ codes

Key: L =Low (<VIL); H = High (>VIH); X =Don’t care

Sector

Bottom boot sector address

(AS29LV400B)

Top boot sector address

(AS29LV400T)

A17 A16 A15 A14 A13 A12 A17 A16 A15 A14 A13 A12

0 00000X 000XXX
1 000010 001XXX
2 000011 010XXX
3 0001XX 011XXX
4 001XXX 1 00XXX
5 010XXX 1 01XXX
6 011XXX 1 10XXX
7 100XXX 1 110XX
8 101XXX 111100
9 110XXX 111101

10 111XXX 11111X

Mode A17–A12 A6 A1 A0 Code

MFR code (Alliance Semiconductor) X L L L 52h

Device code

×8 T boot X L L H B9h
×8 B boot X L L H BAh
×16 T boot X L L H 22B9h
×16 B boot X L L H 22BAh

Sector protection Sector address L H L

01h protected
00h unprotected

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Command format

1 Bus operations defined in "Mode definitions," on page 3.
2 Reading from and programming to non-erasing sectors allowed in Erase Suspend mode.
3 Address bits A11-A17 = X = Don’t Care for all address commands except where Program Address and Sector Address are required.
4 Data bits DQ15-DQ8 are don’t care for unlock and command cycles.
5 The Unlock Bypass command must be initiated before the Unlock Bypass Program command.
6 The Unlock Bypass Reset command returns the device to reading array data when it is in the unlock bypass mode.

Command sequence

Required bus

write cycles

1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle

Address Data Address Data Address Data Address Data Address Data Address Data

Reset/Read 1 XXXh F0h

Read

Address

Read Data

Reset/Read

×16

3

555h

AAh

2AAh

55h

555h

F0h Read Address

Read
Data

×8 AAAh 555h AAAh

Autoselect
ID Read

×16

3

555h

AAh

2AAh

55h

555h

90h

01h

Device code

22B9h (T)
22BAh (B)

×8 AAAh 555h AAAh

02h

Device code

B9h(T)
BAh(B)

×16 555h

AAh

2AAh

55h

555h

90h

00h

MFR code

0052h

×8 AAAh 555h AAAh 52h

×16 555h

AAh

2AAh

55h

555h

90h

XXX02h

Sector protection

0001h = protected
0000h = unprotected

×8 AAAh 555h AAAh

XXX04h

Sector protection

0001h=protected
0000h=unprotected

Program

×16

4

555h

AAh

2AAh

55h

555h

A0h Program Address Program Data

×8 AAAh 555h AAAh

Unlock bypass

×16

3

555

AAh

2AA

55h

555

20h

×8 AAA 555 AAA

Unlock bypass program 2 XXX A0h

Program

address

Program

data

Unlock bypass reset 2 XXX 90h XXX 00h

Chip E rase

×16

6

555h

AAh

2AAh

55h

555h

80h

555h

AAh

2AAh

55h

555h

10h

×8 AAAh 555h AAAh AAAh 555h AAAh

Sector Erase

×16

6

555h

AAh

2AAh

55h

555h

80h

555h

AAh

2AAh

55h

Sector

Address

30h

×8 AAAh 555h AAAh AAAh 555h
Sector Erase Suspend 1 XXXh B0h
Sector Erase Resume 1 XXXh 30h

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Command definitions

Item Description

Reset/Read

Initiate read or reset operations by writing the Read/Reset command sequence into the command
register. This allows the microprocessor to retrieve data from the memory. Device remains in read
mode until command register contents are altered.

Device automa ti cally powers up i n read/ r eset state. This feature allows onl y re ads, therefore
ensuring no spurious memory content alterations during power up .

ID Re ad

AS29LV400 provides manufact urer and device codes in two ways. External PRO M programmers
typically access the device codes by driving +10 V on A9. AS29LV400 also contai ns an ID Read
command to read the device code with only +3V, since multiplexing +10V on address lines is
generally unde sirable.

Initiate device ID read by writing the ID Read command sequence into the command register.
Follo w with a read sequence f rom add ress X X X00h t o return MFR co d e . Follow ID Read command
sequence with a read sequence from address XXX01h to return device code.

To verify write protect status on sectors, read address XXX02h. Sector addresses A17–A12 produce
a 1 on DQ0 for protected sector and a 0 for unprotected sector.

Exit from ID read mode with Read/Reset command sequence.

Hardware Reset

Hold ing RESE T

low for 500 ns resets the de vice, terminating any oper ation in progr ess ; data

handled in the operation is corrupted. The internal state machine resets 20 µs after RESET

is driven

low. RY/ B Y

remains low until i n ternal st ate mach ine rese t s. After RESET is se t hi gh, there is a delay

of 50 ns for the device to permit read operations.

Byte/word
Programming

Programming the AS29LV400 is a four bus cycle operation performed on a byte-by-byte or word­by-word basis. Two unlock write cycles p recede the Program Setu p c om man d a nd program d ata
write cycle. Upon ex ecution of the program comman d, no ad d itional CPU controls or timings are
necessary. Addresses are latched on the falling edge of CE

or WE, whichever is last; data is latched

on the rising edge of CE

or WE, whichever is first. The AS29LV400’s automated on-chip program
algorithm provides adequate internally-generated programming pulses and verifies the
progra mmed cell margin.

Check programming status by sampling data on the RY/BY

pin, or e ither the DATA polling (DQ7)
or toggle bit (DQ6) at the program address location. The programming operation is complete if
DQ7 returns equiv alent da ta, if DQ6 = no togg le , or if RY/BY

pin = high.

The AS29LV400 ignores co mmands written during programming . A har dware reset occurring
during programming may corrupt the data at the programmed location.

AS29LV400 allows programming in any sequence, across any sector boundary. Changing data from
0 to 1 requires an erase opera tion . Attemptin g to progra m data 0 to 1 results in either DQ 5 = 1
(exceeded progra mm in g ti me lim it s) ; rea d ing th i s data after a read/reset operation returns a 0.
When program mi ng time limi t is exceeded , DQ5 r e ads high, an d DQ6 co nt inues to toggle. In this
state, a Reset comman d r etu rns the device to read mode.

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Alliance Semiconductor 8

Unlock Bypass
Command Sequence

The unlock bypass feature increases the speed at which the system programs bytes or words to the
device because it bypasses the first two unlock cycles of the standard program command sequence.

To initiate the unl o ck bypass command seq uence, two unlock cycles must be written, the n
followed by a third cycle which has the unlock bypass command, 20h.

The device then begins the unlock bypass mode. In orde r t o program in this mode, a two cycle
unlock bypass program sequence is required. The first cycle has the unlock bypass program
command, A0h. It is followed by a second cycle which has the program address and data. To
program additional data, the same sequence must be followed.

The unlock bypass mode has two valid commands, the Unlock Bypass Program command and the
Unlock Bypass Reset command. The only way the system can exit the unlock bypass mode is by
issuing the unlock bypass reset command sequence. This sequence inv o lv es tw o cycles . The first
cycle contains the data, 90h. The second cycle contains the data 00h. Addresses are don’t care for
both cycles. The device then returns to reading array data.

Chip Er a se

Chip erase requires six bus cycles: two unlock write cycles; a setup command, two additional
unlock write cycles; and finally the Chip Erase command.

Chip erase does not require logical 0s to be written prior to erasure. When the automated on-chip
erase algorithm is invoked with the Chip Erase command sequence, AS29LV400 automatically
programs and verifies the entire memory array for an all-zero pattern prior to erase. The 29LV400
returns to read mode upon completion of chip erase unless DQ5 is set high as a result of exceeding
time limit.

Sector Erase

Secto r erase r e quires six bus cycle s: two unlock wr i t e cycles, a setup command, two additional
unlock write cycles, and finally the Sector Erase command. Identify the sector to be erased by
addressing an y location in the sector. The address is latched on the falling edge of WE

; the

command, 30h is latched on th e rising edge of WE

. The sector erase opera ti on b egin s afte r a secto r

erase time-out.
To erase multiple sectors, write the Sector Erase command to each of the addresses of sectors to

erase after following the six bus cycle operation above. Timing between writes of additional sectors
must be less than the erase time-ou t period, or the AS29LV400 ignores the command and erasure
begins. During the time-out period any falling ed ge of WE

resets the time-out. Any command
(other than Sector Erase or Erase Suspend) d uring time-out period re se ts the AS29LV400 to read
mode, and the device ignores the sector erase command string. Erase such ignored sectors by
restarting the Sector Erase command on the ignored sectors.

The entire array need not be written with 0s prior to erasure. AS29LV400 writes 0s to the entire
sector prior to electrical erase; writing of 0s aff ects only selected sectors, leaving non-sel ected
sectors unaffected . AS29LV400 requires no CPU control or timing signals during sector erase
operations.

Automatic sector erase begins after sector erase time-out from the last rising edge of WE

from the

sector erase command stream and ends when the DATA

polling (DQ7) is logical 1. DATA polling
address must be performed on addresses that fall within the sectors being erased. AS29LV400
returns to read mode after sector erase unless DQ5 is set high by exceeding the time limit.

Item Description

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Alliance Semiconductor 9

Erase Suspend

Erase Suspend allows interruption of sector erase operations to read data from or program data to a
sector not being erased. Erase suspend applies only during sector erase operations, including the
time- out period. Wri ti n g an E ras e Su sp e n d c om mand durin g s ec t or erase time -out res ult s in
immediate termination of the time-out period and suspension of erase operatio n.

AS29LV400 ignores any commands during erase suspend other than Rea d/Reset, P ro gram or Erase
Resume commands . Writing the Erase Re sume Command continu es erase operation s. Addres ses are
Don’t Care when writing Erase Suspend or Erase Resume commands.

AS29LV400 takes 0.2–15 µs to suspen d erase o perations aft e r receiving Erase Suspend command.
To determine completion of erase suspend, either check DQ6 after selecting an address of a sector
not being erased, or poll RY/BY

. Chec k DQ2 in conju nctio n with DQ6 to determine if a sector is

being era se d. AS29 LV400 ignores redundant wri t es of Erase Susp en d.
While in erase-suspend mode, AS29L V400 allows reading data (erase-suspend-read mode) from or

prog ra m m ing data (er a s e -s u s pe n d -p r o gr a m mo d e ) to any sector not un dergoing sector er a s e;
these operations are treated as standard read or standard programming mode. AS29LV400 defaults
to erase-suspend -r ead mode while an erase operation has b een su spended.

Write the Resume command 30h to continue operation of sector erase. AS29LV400 ignores
redundant writes of the Resume command. AS29LV400 permits multiple suspend/resume
operations during sector erase.

Sector Protect

When attempting to write to a protected sector, D ATA

polling and Toggle Bit 1 (DQ6) ar e activa ted

for about <1 µs. When attempting to erase a protected sector, DAT A

polling and
Toggle Bit 1 (DQ6) are activated for about <5 µs. In both cases, the device returns to read mode
without altering the specified sectors.

Ready/Busy

RY/BY

indicates whether an automated on-chip algorithm is in progress (RY/BY = low) or

completed (RY/BY

= high). The device does not accept Program/Erase commands when

RY/BY

= low. RY/BY= high when device is in erase suspend mode. RY/BY = high when device

exceeds time limit, indica ti ng t hat a pro g ram or eras e operat ion h as f ail ed. RY/BY

is an open drain

output, ena bling multiple RY/BY

pins to be tied in parallel with a pull up resistor to VCC.

Item Description

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AS29LV400

January 2001

Alliance Semiconductor 10

Status operations

Write operation status

DQ2 toggles when an erase-suspended sector is read repeatedly.
DQ6 toggles when any address is read repeatedl y.
DQ2 = 1 if byte address being programmed is read during erase-suspend program mode.

†

DQ2 tog gl es when the rea d a d d ress appli ed po in ts t o a sec t or which is und ergoing erase, suspended erase, or a failure to erase.

DAT A polling (DQ7)

Only active during automated on-chip algorithms or sect or erase time outs. DQ 7 reflects
complement of data last written when read during the automated on-chip program algorithm (0
during erase algorithm); reflects true data when read after completion of an automated on-chip
program algorithm (1 after completion of erase agorithm).

Toggle bit 1 (DQ6)

Active during automated on-chip algorithms or sector erase time outs. DQ6 toggles when CE

or OE
toggles, or an Erase Resume command is invoked. DQ6 is valid after the rising edge of the fourth
pulse of WE

during programming; after the rising edge of the sixth WE pulse during chip erase;

after the last rising edge of the sector erase WE

pulse for se ctor erase. For protected sectors,
DQ6 toggles for <1 µs during pr o gram mode writes, and <5 µ s during erase (if all selected sectors
are protected).

Exceeding tim e lim it
(DQ5)

Indicates unsuccessful completion of program/erase operation (DQ5 = 1). DATA

polling remains
active. If DQ5 = 1 during chip erase, all or som e sectors are def ective ; during byte pro gramming or
sector erase, the sector is defective (in this case, reset the device and execute a program or erase
command sequence to continue working with functional sectors). Attempting to program 0 to 1
will set DQ5 = 1.

Sector erase timer
(DQ3)

Checks whether sector erase timer wind ow is open. If DQ3 = 1, erase is in progress; no commands
will be accepted. If DQ3 = 0, the device will accept sector erase commands . Check DQ3 before and
after each Sector Erase command to verify that the command was accepted.

Toggle bit 2 (DQ2)

During sector erase, DQ2 toggles with OE

or CE only during an attempt to r ead a s ect or b ei ng

erased. During chip erase, DQ2 toggles with OE

or CE for all addresses. If DQ5 = 1, DQ2 toggles
only at sector addresses where failure occurred, and will not toggle at other sector addresses. Use
DQ2 in conjunction with DQ6 to determine whether device is in auto erase or erase suspend
mode.

Status DQ7 DQ6 DQ5 DQ3 DQ2 RY/BY

Standard mode

Auto programming DQ

7 Toggle 0 N/A N o to gg le 0

Program/erase in auto erase 0 Toggle 0 1 Toggle

†

0

Erase suspend mode

Read erasing sector 1 No toggle 0 N/A Toggle 1
Read non-erasing sector Data Data Data Data Data 1
Program in erase suspend DQ

7 Toggle 0 N/A Toggle

†

0

Exceeded time limi ts

Auto programming (byte) DQ

7 Toggle 1 N/A N o to gg le 1

Program/erase in auto erase 0 Toggle 1 N/A Toggle

†

1

Program in erase suspend
(non-erase suspended sector)

DQ

7 Toggle 1 N/A N o to gg le 1

®

AS29LV400January 2001

Alliance Semiconductor 11

Automated on-chip programming algorithm Automated on-chip erase algorithm

†

The system software should check the status of DQ3 prior to and following each
subsequent sector erase command to ensure command completion. The device may
not have accepted the command if DQ3 is high on second status check.

START

555h/AAh

2AAh/55h

555h/A0h

Program address/program data

Program command sequence

×16 mode (address/data):

Write progra m command sequ e nce

(see below)

DATA polling or toggle bit

successfully completed

Last

address?

Programming completed

YES

Increment

address

NO

555h/AAh

2AAh/55h

555h/80h

erase command sequence

555h/AAh

2AAh/55h

Sector address/30h

Erase complete

×16 mode (address/d ata):

DATA polling or toggle bit

successfully completed

Write erase command sequence

(see belo w)

555h/AAh

2AAh/55h

555h/80h

Chip erase c ommand s e quence

555h/AAh

2AAh/55h

555h/10h

×16 mode (address/data):

Individual sector/multiple sector

Sector address/30h

Sector address/30h

optio nal sector erase commands

START

®

AS29LV400January 2001

Alliance Semiconductor 12

Programming using unlock bypass command

START

Write unlock

bypass command

(3 cycles)

Write unlock

bypass program command

(2 cycles)

DATA polling or

Last

address?

YES

Increment

address

NO

Write unlock

bypass reset command

(2 cycles)

Programming completed

toggle bit

successfully completed

555h/AAh

2AAh/55h

555h/20h

Unlock bypass command sequence

x16 mode (address/data)

xxxh/A0h

Unlock bypass program

x16 mode (addres s/data)

command sequence

program address/

program data

xxxh/90h

Unlock bypass reset

x16 mode (addres s/data)

command sequence

xxxh/00h

®

AS29LV400January 2001

Alliance Semiconductor 13

DATA polling algorithm

†

VA = Byte address for programming. VA = any of the sector
addresses within the sector being erased during Sector Erase. VA
= valid address equals any non-protected sector group address
during Chip Erase.

‡

DQ7 rec he c ke d even if D Q5 = 1 b ecause DQ5 a n d DQ7 may not
change simultaneously.

Toggle bit algorithm

†

DQ6 rechecked even if DQ5 = 1 because DQ6 may stop toggling

when DQ5 changes to 1.

Read byte (DQ0–DQ7)

Address = VA

†

Read byte (DQ0–DQ7)

Address = VA

NO

DONE

NO

NO

†

YES

FAIL

YES

†

YES

DONE

DQ7

=

data

?

DQ5

=

1
?

DQ7

=

data

‡

?

Read byte (DQ0–DQ7)

Address = don’t care

Read byte (DQ0–DQ7)

Address = don’t care

NO

DONE

YES

YES

YES

FAIL

NO

NO

DONE

DQ6

=

toggle

?

DQ6

=

toggle

†

?

DQ5

=

1

?

®

AS29LV400

January 2001

Alliance Semiconductor 14

Sector protect algorithm Sector unprotect algorithm

START

PLSCNT = 1

RESET# = V

ID

Wait 1 µs

First Write

Cycle=60h?

Temporary sector

unprotect mode

No

Set up sector

Sector protect:

address

write 60h to sector

address with

A6=0, A1=1 ,

A0=0

Wait 150 µs

Verify sector

protect; write 40h

to sector address

with A6=0,

A1=1, A0=0

Read from sector

address with A 6 =0,

A1=1, A0=0

Data=01h?

Protect
sector?

PLSCNT=25?

No

Increment

PLSCNT

No

Device failed

Yes

Yes

Yes

No

START

PLSCNT = 1

RESET # = V

ID

Wait 1 µs

First Write
Cycle=60h?

Temporary sector

unprotect mode

No

Yes

All sectors

protected?

Set up first

Sector unprotect:

sector address

write 60h to sector

address with

A6=1, A1=1,

A0=0

Wait 15 ms

Verify sector

unprotect; writ e 40h

to sector address

with A6=1,

A1=1, A0=0

Read from sector

address with A6=1,

A1=1, A0=0

Data=00h?

Last sector

verified?

No

Yes

Yes

Remove V

ID

from RESET#

Write reset

command

Sector unprotect

complete

Remove V

ID

from RESET#

Write reset

command

Sector protect

complete

PLSCNT

Increment

PLSCNT

No

Device failed

Yes

=1000?

Set up next

sector address

No

Protect all sectors:

The shaded portion of

the sector protct

initiated for all

unprotected sectors

before calling the

sector unprotect

No

Yes

Yes

algorithm must be

another

®

AS29LV400

January 2001

Alliance Semiconductor 15

DC electrical characteristics

VCC = 2.7–3.6V

Parameter Symbol Test conditions Min Max Unit

Input load current I

LI

VIN = VSS to VCC, VCC = V

CC MAX

-±1µA

A9 Input load current I

LIT

VCC = V

CC MAX

, A9 = 10V 35 µA

Outpu t le akag e curr ent I

LO

V

OUT

= VSS to VCC, VCC = V

CC MAX

-±1µA

Active current, read @ 5MHz I

CC1

CE = VIL, OE = V

IH

-20mA

Active current, program/erase I

CC2

CE = VIL, OE = V

IH

- 100 mA

Automatic sleep mode

*

* Automatic sleep mode enables the deep power down mode when addresses are stable for 150 ns. Typical sleep mode current is 200 nA.

I

CC3

CE = VIL, OE = VIH;
V

IL

= 0.3V, VIH = VCC - 0.3V

-5µA

Standby current I

SB

CE = VCC - 0.3V, RESET = VCC - .3V - 5 µA

Deep power down current

3

I

PD

RESET = 0.3V - 5 µA

Input low voltage V

IL

-0.5 0.8 V

Input high voltage V

IH

0.7×V

CC

VCC + 0.3 V

Outp ut low volt age V

OL

IOL = 4.0mA, VCC = V

CC MIN

-0.45V

Output high v o ltage V

OH

IOH = -2.0 mA, VCC = V

CC MIN

0.85×V

CC

-V

Low V

CC

lock out volt age V

LKO

1.5 - V

Input HV selec t voltage V

ID

911V

®

AS29LV400

January 2001

Alliance Semiconductor 16

AC parameters — read cycle

Read waveform

JEDEC
Symbol Std Symbol Parameter

-80 -90 -120
UnitMin Max Min Max Min Max

t

AVAV

t

RC

Read cycle time 80 - 90 - 120 - ns

t

AVQV

t

ACC

Addres s to output delay - 80 - 90 - 120 ns

t

ELQV

t

CE

Chip enable to output - 80 - 90 - 120 ns

t

GLQV

t

OE

Output enable to output - 30 - 35 - 50 ns

t

OES

Output enable setup time 0 - 0 - 0 - ns

t

EHQZ

t

DF

Chip ena ble to output High Z - 20 - 30 - 30 ns

t

GHQZ

t

DF

Output enable to output High Z - 20 - 30 - 30 ns

t

AXQX

t

OH

Output hold time from addresses,
first occurren ce of CE

or OE

0-0-0-ns

t

OEH

Output enable hold time: Read 10 - 10 - 10 - ns
Output enable hold time:

Toggle and data polling

10 - 10 - 10 - ns

t

PHQV

t

RH

RESET high to output delay - 50 - 50 - 50 ns

t

READY

RESET pin low to read mode - 10 - 10 - 10 µs

t

RP

RESET pulse 500 - 500 - 500 - ns

Addresses stab le

Addresses

t

RC

t

ACC

t

OE

t

OEH

t

CE

t

OH

t

DF

CE

OE

WE

Outputs

High Z High Z

Output valid

t

RH

RESET

t

OES

®

AS29LV400

January 2001

Alliance Semiconductor 17

AC parameters — write cycle

WE controlled

Write waveform

WE controlled

JEDEC
Symbol Std Symbol Parameter

-80 -90 -120
UnitMin Max Min Max Min Max

t

AVAV

t

WC

Write cycle time 80 - 90 - 120 - ns

t

AVWL

t

AS

Address setup time 0-0-0-ns

t

WLAX

t

AH

Address hold time 45 - 45 - 50 - ns

t

DVWH

t

DS

Data setup time 35 - 45 - 50 - ns

t

WHDX

t

DH

Data hold time 0-0-0-ns

t

GHWL

t

GHWL

Read recover t ime bef o re write 0 - 0 - 0 - ns

t

ELWL

t

CS

CE

setup time

0-0-0-ns

t

WHEH

t

CH

CE

hold time

0-0-0-ns

t

WLWH

t

WP

Write pulse width 35 - 35 - 50 - ns

t

WHWL

t

WPH

Write pulse width high 30 - 30 - 30 - ns

Addresses

CE

OE

WE

DATA

t

WC

t

AS

t

AH

t

GHWL

; t

OES

t

WP

t

CS

t

WPH

t

DH

t

WHWH1 or 2

t

DS

DQ7D

OUT

Program

555h Program address Program address

3rd bus cy cle

t

CH

DATA polling

A0h

data

®

AS29LV400

January 2001

Alliance Semiconductor 18

AC parameters — write cycle 2

CE controlled

Write waveform 2

CE controlled

JEDEC
Symbol Std Symbol Parameter

-80 -90 -120
UnitMin Max Min Max Min Max

t

AVAV

t

WC

Write cycle time 80 - 90 - 120 - ns

t

AVEL

t

AS

Address setup time 0 - 0 - 0 - ns

t

ELAX

t

AH

Address hold time 45 - 45 - 50 - ns

t

DVEH

t

DS

Data setup time 35 - 45 - 50 - ns

t

EHDX

t

DH

Data hold time 0-0-0-ns

t

GHEL

t

GHEL

Read recover time before write 0 - 0 - 0 - ns

t

WLEL

t

WS

WE setup time 0 - 0 - 0 - ns

t

EHW H

t

WH

WE hold time 0-0-0-ns

t

ELEH

t

CP

CE pulse width 35 - 35 - 50 - ns

t

EHEL

t

CPH

CE pulse width high 30 - 30 - 30 - ns

Addresses

WE

OE

CE

DATA

Program address555h Program address

A0h

Program

DQ7D

OUT

t

WC

t

AS

t

AH

t

CP

t

CPH

t

DH

t

DS

t

WHWH1 or 2

DATA polling

data

t

GHEL

, t

OES

®

AS29LV400

January 2001

Alliance Semiconductor 19

AC parameters — temporary sector unprotect

Temporary sector unprotect waveform

AC parameters — RESET

RESET waveform

Erase waveform

×16 mode

JEDEC
Symbol Std Symbol Parameter

-80 -90 -120
UnitMin Max Min Max Min Max

t

VIDR

VID rise and fall time 500 - 500 - 500 - ns

t

RSP

RESET

setup time for temporary

sector unprotect

4-4-4-µs

JEDEC
Symbol Std Symbol Parameter

-80 -90 -120
UnitMin Max Min Max Min Max

t

RP

RESET

pulse

500 - 500 - 500 - ns

t

RH

RESET

High time before Read

-50-50-50ns

t

READY

RESET

Low to Read mode - 10 - 10 - 10 µs

RESET

CE

WE

RY/BY

0 or 3V

t

VIDR

t

VIDR

0 or 3V

t

RSP

Program/erase command sequence

10V

RESET

RY/BY

DQ

t

RP

t

READY

t

RP

t

RH

valid datavalid dat astatusstatus

Addresses

CE

OE

WE

Data

555h 2AAh 555h 555h 2AAh Sector address

t

WC

t

AS

t

AH

t

GHWL

AAh 55h 80h AAh 55h 30h

10h for Chip Erase

t

WP

t

CS

t

WPH

t

DH

t

DS

t

WC

®

AS29LV400

January 2001

Alliance Semiconductor 20

AC Parameters — READY/BUSY

RY/BY waveform

DATA polling waveform

Toggle bit waveform

JEDEC
Symbol Std Symbol Parameter

-80 -90 -120
UnitMin Max Min Max Min Max

-t

VCS

VCC setup time 50 - 50 - 50 -

µs

-t

RB

Recovery time from RY/BY

0-0-0-

ns

-t

BUSY

Program/erase valid to RY/BY delay

90 - 90 - 90 -

ns

CE

WE

RY/BY

Rising edge of last WE signal

Program/erase

operation

tri-stated open-drain

V

CC

t

VCS

t

RB

t

BUSY

CE

OE

WE

DQ7

t

CH

t

OH

t

WHWH1 or 2

t

OE

t

OEH

t

CE

t

DF

High Z

Input DQ7 Output DQ

7Output

CE

WE

OE

DQ6

t

OEH

t

DH

t

OE

toggletoggle no toggle

®

AS29LV400

January 2001

Alliance Semiconductor 21

Word/byte configuration

BYTE read waveform

BYTE write waveform

Sector protect/unprotect

JEDEC
Symbol Std Symbol Parameter

-80 -90 -120
UnitMin Max Min Max Min Max

-t

ELFL/tELFH

CE

to BYTE switching Low or High - 10 - 10 - 10 ns

-t

FLQZ

BYTE

switching Low to output High-Z

-30-35-40 ns

-t

FHQZ

BYTE

switching High to output Active

80 - 90 - 120 -

ns

CE

OE

BYTE

DQ0-DQ14

DQ15/A-1

BYTE

DQ0-DQ14

DQ15/A-1

BYTE

Word

to

Byte

Byte

to

Word

Data output

Data output

Address inputDQ15 output

Data output

DQ0-DQ7

DQ0-DQ14 DQ0-DQ7

Data output

DQ0-DQ14

Address input DQ15 output

t

ELFL

t

ELFH

t

FLQZ

t

FHQV

CE

WE

BYTE

falling edge of last WE signal

t

SET

(tAS)t

HOLD

(tAH)See Erase/Program operations table for tAS and tAH specifications.

RESET#

CE#

OE#

* For sector protect, A6=0, A1=1, A0=0. For sector unprotect, A6=1, A1=1, A0=0.

V

ID

V

IH

Valid* Valid* Valid*

SA, A6,
A1, A0

60h 40h Status60h

DATA

Sector protect/unprotect

1 µs

Sector protect: 100 µs
Sector unprotect: 10 ms

WE#

Verify

Don’t care Don’t care Don’t care

Don’t careDon’t care

®

AS29LV400

January 2001

Alliance Semiconductor 22

AC test conditions

Test specifications

Erase and programming performance

Latchup tolerance

Includ es a ll pin s exc e pt VCC. Test conditions: VCC = 3.0V, one pin at a time.

Recommended operating conditions

Test Condition 80 90, 120 Unit

Outp ut L oa d

1 TTL gate

Output Load Capacitance C

L

(including jig capacitance) 30 100 pF
Input Rise and Fall Times 5ns
Input Pulse Levels 0.0-3.0 V
Input timing measurement reference levels 1.5 V
Output timing measurement reference levels 1.5 V

Parameter

Limits

UnitMin Typical Max

Sector erase and verify-1 time (excludes 00h p r ogramming
prior to erase)

-

1.0 15 sec

Programming time

Byte - 10 300 µs

Word - 15 360 µs
Chip programming time - 7.2 27 sec
Erase/program cycles

*

* Erase/program cycle test is not verified on each shipped unit.

-100,000- cycles

Parameter Min Max Unit

Input voltage with respect to

V

SS

on A9,

OE, and RESET pin

-1.0 +12.0 V

Input voltage with respect to

V

SS

on all DQ, address, and control pins -0.5

VCC

+0.5 V

Current -100 +100 mA

Parameter Symbol Min Max Unit

Supply voltage

V

CC

+2.7 +3.6 V

V

SS

00V

Input voltage

V

IH

1.9 V

CC

+ 0.3 V

V

IL

–0.5 0.8 V

6.2K

Ω

CL*

2.7K

Ω

Device under test

V

SS

+3.0V

V

SS

V

SS

1N3064
or equi va lent

1N3064
or equivalent

®

AS29LV400

January 2001

Alliance Semiconductor 23

Absolute maximum ratings

Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the de vice. This is a stress rating only and functional operation
of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute max­imum rating conditions for extended periods may affect reliability.

TSOP pin capacitance

SO pin capacitance

Data retention

Parameter Symbol Min Max Unit

Input voltage (Input or DQ pin) V

IN

–0.5 VCC+ 0.5 V

Input voltage (A9 pin, OE

, RESET)VIN–0.5 +12.5 V

Power supply voltage V

CC

-0.5 +4.0 V

Operating tem p era ture T

OPR

–55 +125 °C

Storage temperature (plastic) T

STG

–65 +150 °C

Short circuit output current I

OUT

- 150 mA

Symbol Parameter T e st setup Typ Max Unit

C

IN

Input capacitance VIN = 0 6 7.5 pF

C

OUT

Output capacit ance V

OUT

= 0 8.5 12 pF

C

IN2

Control pin cap aci tance VIN = 0 8 10 pF

Symbol Parameter T e st setup Typ Max Unit

C

IN

Input capacitance VIN = 0 6 7.5 pF

C

OUT

Output capacit ance V

OUT

= 0 8.5 12 pF

C

IN2

Control pin cap aci tance VIN = 0 8 10 pF

Parameter Temp.(°C) Min Unit

Minimum pa t tern da ta re tention time

150° 10 years
125° 20 years

© Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product na m e s
may be the trademarks of their respective companies. Alliance reserves the right to make c hanges to this document and its produc ts at any time without notice. Alliance assumes no responsibility for any errors
that may appear in this document. The data contained herein represents Alliance’s best data an d/or esti mate s at the time of issu a nce. Allia nce rese rve s the ri ght to change or corr ect this data at any time,
without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive
information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising
out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sa le and/or use of Alliance products including liability or warranties related to
fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance’s Terms and Conditions of Sale (which are available from Alliance).
All sales of Alliance products are made exclusively according to Alliance’s Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights,
copyrights, mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supportin g systems
whe re a mal f un ct i on or fa il u re ma y r e as on ab ly be e xp ec te d to re su lt i n s ig ni f ic an t i nj ur y t o th e us er, and t he inclusion of Alli ance products in such life-supporting systems implies that the manufacturer
assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.

®

AS29LV400January 2001

12/21/00 Alliance Se miconductor 24

AS29LV400 ordering codes

AS29LV400 part numbering system

Package \ Access Time 80 ns (commercial/industrial) 90 ns (commercial/industrial) 120 ns (commer cial/industrial)

TSOP, 12×20 mm, 48-pin
Top boot c onfiguration

AS29LV400T-80TC
AS29LV400T-80TI

AS29LV400T -90TC
AS29LV400T -90TI

AS29LV400T -120TC
AS29LV400T -120TI

TSOP, 12×20 mm, 48-pin
Bottom boot configuration

AS29LV400B-80TC
AS29LV400B-80TI

AS29LV400B-90TC
AS29LV400B-90TI

AS29LV400B-120TC
AS29LV400B-120TI

SO, 13.3 mm, 44-pi n
Top boot c onfiguration

AS29LV400T-80SC
AS29LV400T-80SI

AS29LV400T -90SC
AS29LV400T -90SI

AS29LV400T -120SC
AS29LV400T -120SI

SO, 13.3 mm, 44-pi n
Bottom boot configuration

AS29LV400B-80SC
AS29LV400B-80SI

AS29LV400B-90SC
AS29LV400B-90SI

AS29LV400B-120SC
AS29LV400B-120SI

AS29LV 400 X –XXX X X X

3V Flash
EEPROM
prefix

Device
number

T= Top boot configuration
B= Bottom boot configuration

Address
access time

Package:
S= SOJ
T= TSOP

Temperature range:
C = Commercial: 0°C to 70°C
I= Industrial: -40°C to 85°C

Options:
B= Burn-in
H= High I

SB

(<1mA)

Blank= Standard