Datasheet AS2702-20T, AS2702-20, AS2702-16T, AS2702-16 Datasheet (Austria Mikro Systeme International)

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AS-Interface Slave IC
AS2702 (SAP4.1)

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• Interface Device to connect Actuators and Sensor s to an AS-Interface Bus

• Conforms to AS-Interface Spec. V2.11

• DC Power Extraction from the AS-I nterface Bus

• Serial bidir. Data Communication with the Bus

• Data Communication Watchdog

• 4-Bit bidir. Data Port plus Strobe to poll the Sensors and control the Actuators con-

nected

• 4-Bit Parameter Port plus Str obe to provide Settings to the Sensors and Actuators

• 24V Power Supply for the Sensors and Actuators

• Periphery Fault Input to signal Hardware Failure of t he Sensor s and Actuators

• Integrated 16 x 8 Bit EEPROM to store (5 + 1) - Bit Slave Address and Set tings

• 2 LED Outputs to optically flag Slave Unit O peration Status

• Operating Temperat ur e Ta: - 25 °C … + 85 °C

• Operating Supply Voltage / Bus DC Volt age: typ. 30 V

• Operating Current (O sc. on, Outputs idle): ≤ 6 mA

• Supply for Sensors / Actuators: typ. 24 V, ≤ 50 mA

• Package: SOIC 20 for full Functionality;

SOIC 16 for Applications not r equiring the Parameter Port

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AS2702 (SAP4.1) is a new generation AS-interface slave device conforming to AS-interf ace­specification V2.11, which supports AS-interface bus systems with up to 62 slave modules.

Each slave module is equipped with an AS2702 device, which interfaces the module to the
unshielded 2-wire AS-interface bus for ser ial bidirectional data communication and power ex­traction.

Data communication over the AS-interf ace bus t akes place in master slave fashion, which
foresees that all slave devices AS2702 connected to the bus are sequent ially and cyclicly ad­dressed by a single, central master unit. Dat a on t he AS-interface bus are Manchester en­coded and can be found as sin2-pulses with a Vpp of between 3V and 8V on top of the bus’
dc voltage of nominally 30V.

AS2702 regulates the nominal dc bus voltage of 30V internally down to 5V to supply it’s inter­nal circuitry including a 16 x 8 bits EEPROM, as well as down to a nominal supply level 24V
with a max. loading of 50 mA for the act uators and sensors connected to it at the f ield side.

Each slave device AS2702 may interface to up to 4 sensors or 3 actuators. An AS- int erface
bus system based on AS2702 may hence link as many as 248 sensors or 186 actuators to a
single master unit.

Slave device AS2702 (SAP4.1) is system compatible with predecessor device AS2701A
(ISA3+): slave modules equipped with AS2702 (SAP4.1) will run in existing AS- interface bus
systems based on AS2701A (ISA3+).

The AS-interface concept is well established as a standar dized digit al bus system for indus­trial automation.

Rev. C, January 2001 Page 2 of 18

AS-Interface Slave IC
AS2702 (SAP4.1)

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CDC

LTGP

U5R U5R U5R

OSC1

OSC2

LTGN

OSCIL­LATOR

RECEIVE TRANSMIT

RESET

threshold

IMP_NEG

IMP_POS

V

-6V

LTGP

U5R

JABBER

INHIBIT

11

LOGIC BLOCK

+

U5R

-

THERMO-

DETECTOR

BANDGAPPORN

+

-

UOUT

U5R

SCL

SDA

16 x 8 BIT

2

PROM

SERIAL E

LED144LED2

PFAULT

DSTBn

D0...D3

P0...P3

PSTBn

TRIMMING

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Pin Nr.: Pin Nr.:

1 -- P1 I/O, digital,

pull-up

2 -- P0 I/O, digital,

pull-up
3 1 D1 I/O, digital Bidir. data port bit 1
4 2 D0 I/O, digital Bidir. data port bit 0
5 3 DSTBn I/O, digital,

pull-up
6 4 LED1 I/O, digital,

pull-up
7 5 OSC2 O, analog Output to quarz crystal
8 6 OSC1 I, analog Input from quartz crystal
9 7 U5R O, power Nom. 5V power supply output

10 8 LTGN I, power Neg. supply pin, connected

1, 2 Bidir. parameter port bit 1
1, 2 Bidir. parameter port bit 0

1 Data port strobe output; reset -input
1 LED output 1 (IC test input)

Rev. C, January 2001 Page 3 of 18

AS-Interface Slave IC
AS2702 (SAP4.1)

to neg. AS-interface bus line;
ground reference.

11 9 LTGP I , power Pos. supply pin, connected

to pos. AS-interface bus line
12 10 CDC I/O, analog Pin for ext. buffer capacitor
13 11 UOUT O, power Nom. 24V power supply output
14 12 PFAULT I, digital, pull-

up

15 13 LED2 I/O, digital,

pull-up

16 14 PSTBn I/O, digital,

pull-up
17 15 D3 I/O, digital Bidir. data port bit 3
18 16 D2 I/O, digital Bidir. data port bit 2
19 -- P3 I/O, digital,

pull-up
20 -- P2 I/O, digital,

pull-up

1 Low-active input to flag fa ilur e

of the sensors / actuators cir c uit ry con­nected

1 LED output 2 (IC test input)
1 Parameter port strobe output

(IC test input)

1, 2 Bidir. parameter port bit 3
1, 2 Bidir. parameter port bit 2

Notes:
1 The pull-up structure is a passive hig h- side current source with a nom. 10 µA current

2 The passive pull-up current source as per not e 1 on these parameter port pins is off,

if the slave device is programmed with I/O-configuration code 7 and a master data
call is present

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All voltages are referenced to g r ound pin LTGN. Timing is valid for a quartz crystal frequency
of 5.333 MHz.

a) Absolute maximum ratings

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VLTGP Voltage at the positive supply pin - 0.3 40 V 1
VCDC Volage at pin for ext. buf fer capacitor - 0.3 VLTGP +

0.3V
VU5R Voltage at pins U5R, OSC1, OSC2 - 0.3 7 V
IIN Input curr ent at any pin, except for LTGP,

CDC
ESD1 Elect r ost atic discharge voltage 1500 V 3
ESD2 Elect r ost atic discharge voltage 200 V 4

ΘSTG
ΘLEAD

PTOT Max. power dissipation 1 W 6
RTHJA Thermal resistance SOIC 16 61.2 74.8 °K / W 7
RTHJA Thermal resistance SOIC 20 58.5 71.5 °K / W 7

Storage temperature - 55 125 V

Solder temperature 260 °C 5

- 50 50 mA 2

V

Rev. C, January 2001 Page 4 of 18

AS-Interface Slave IC
AS2702 (SAP4.1)

Notes:
1 50 V during t > 50 µ s; repetition rate < 0.5 Hz

2 Latch-up immunity test. Pls. observe max. power dissipation allowed.
3 Human body model: R = 1.5 kOhm; C = 100 pF
4 Machine model; applies only for LTGP-LT G N
5 260 °C during 10 s (ref low and wave soldering); 360 °C during 3 s for manual solder-

ing. Twofold reflow soldering is accept able.
6 Free convection, see fig. 1
7 No forced cooling. PCB- surface: 21 cm2; still air volume around the device: 10 cm

3

Pv/ W

1

0,5

50 100

t/ °C

Pv/ W

0,5

1

50

62,&62,&

100

Fig. 1: Max. acceptable power dissipation relative to ambient temperat ur e

b) Recommended Operating Conditions

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VLTGP Positive supply voltage / dc

portion
ILTG Supply current consumption 6 mA 2
OA Ambient temperature - 25 25 85 °C 3
FC Quartz frequency 5.3333

Sensitivity against moisture 5

17.5 34 V 1

MHz 4

33

t/ °C

Notes:
1 False-poling protection diode to be inserted between pos. AS-interface bus line and

LTGP-pin. LTGP-pin to be pr otected furthermore with a voltage clam p bet ween

LTGP and LTGN.
2 Oscillator on; dat a transmission stage off ; no loads connected
3 Power dissipation restrictions as per fig. 1 to be observed
4 ASI Quarz
5 Level 5 acc. to JEDEC-standard JESD22-A112, Table 1

Rev. C, January 2001 Page 5 of 18

AS-Interface Slave IC
AS2702 (SAP4.1)

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Positive supply pin connected to positive AS-interface bus line and clamped relative to neg.
supply pin / ground LTGN as described under Recommended O per at ing Conditions.
VLTGP and ILTG specified under Recommended Operating Conditions as well.

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VSIG VPP of sin2-data-pulses

on top of dc supply voltage

Z Input impedance

between 50 kHz and 300 kHz

Note:
1 Input equivalent circuit is parallel arrangement of C, R and L

38V

40 pF CCDC = 100 nF

1
18 kOhm 1
50 mH 1

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An external buffer capacitor with a recommended value of 100 nF should be connected to this
pin to ensure a sufficiently high input impedance Z at power supply pin LTGP.
Voltage at this pin can be as high as VLTG P.

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The supply output voltage at UOUT is dir ectly derived from VLTGP and reg ulated to a level
with an offset of about - 6V relative to VLTGP.
UOUT provides bias to the sensors and actuators cir cuitry connected to the slave device as
well as to the LEDs connected to outputs LED1 and LED2.

UOUT is equipped with a thermal overload protection, which f oresees that VUOUT is switched

off as soon as the slave device’s substrate temper ature TJ passes a threshold value in the
range of (155 -+ 20)°C.
After TJ has come down and has passed a temperat ur e threshold about (15 -+ 5)°C lower
than (155 -+ 20)°C and after a consecutive minimum delay of 1 s has elapsed, VUOUT is
switched on again.

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VUOUT Power supply output voltage VLTGP -

6.3V
IUOUT Load curr ent 50 m A 1
VCOMOFF UOUT voltage level 9.5 10.5 V

below which data transmission
is inhibited

CUOUT Buffer capacitor 10 µF 2

VLTGP -

5.3V

V

Notes:
1 In case IUOUT > 40 m A and pr esence of sin2-data pulses on LTGP

Rev. C, January 2001 Page 6 of 18

AS-Interface Slave IC
AS2702 (SAP4.1)

with VSIG > 3V, VUOUT may drop as much as 1V below it’s level
in unloaded condition

2 Electrolythic and rf filter capacitor in parallel

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The voltage at U5R is derived from the voltage present at UOUT, as long as UOUT is not
switched off due to overload. In the latter case U5R is derived from an alternative voltage out
of the UOUT voltage regulator, which is more or less similar to VUOUT in non switched off
condition of UOUT. As a result VU5R is not affected by overload condition at UOUT and will
remain.

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VU5R Power supply output voltage 4. 85 5.15 V
IU5R Load current 1 mA
CU5R Buffer capacitor 100 nF

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The only component to be connected to these pins is a quartz crystal with a resonance fre­quency of 5.333333 MHz (AS-Interface quar tz crystal).

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CX2 Stray capacitance 10 pF

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Basically data port D3, …, D0 is designed for bidirectional data transfer out of and into the
slave device. Each data port pin is equipped with both a low-side open-drain output stage as
well as an input stage to this purpose.

Depending on the so called IO-configuration code, written into and stored in the slave device,
each data port pin is individually set to behave as

• output, or

• output / input, or

• input.

The timing of the data transfer is presented in fig. 2.
Strobe signal DSTBn flags and governs the data transfer as follows:
ha) data port pin is set ‘output’:

output data become valid upon the HL-edge of the strobe and will remain so until the next
HL-edge, hence during the entir e st robe cycle;

hb) data port pin is set ‘output / input ’:

output data become valid upon the HL-edge of the strobe and will remain so until it’s LH­edge; input data to be valid within a specific time window relative to the HL-edge, after
completion of the strobe’s L-phase;

hc) data port pin is set ‘input’:

Rev. C, January 2001 Page 7 of 18

AS-Interface Slave IC
AS2702 (SAP4.1)

input data to be valid within a specific time window relative to the HL-edge of the st r obe,

after completion of t he strobe’s L-phase.

If necessary, output data as per ha) and hb) can be easily latched with the LH- edge of strobe
DSTBn as they will remain valid for about 0.4 µs beyond as a minimum.
Care must be taken however, that signal delay added by external circuitr y is lower for the
strobe than for the data.

Dx

Dx

t

+ 0.4 µs

DSTBn

t

STB

t

DSTBn

Data out

+ t

OUTOFF

Data inData out

Data in

DSTBn

t

DSTBn

t

INPmin

t

INPmax

Fig. 2: Timing of data transfer at data port D3, …, D0 relative to strobe DSTBn
The following table specifies the t iming parameters relating to fig. 2:

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tSTB Delay DSTBn HL-edge to Dx

1.5 µs

output data valid
tDSTBn DSTBn strobe width 6 6.8 µs 1
tOUTOFF Delay DSTBn LH-edge t o Dx

0.2 1 µs 2

output off
tINP Input data valid time window 10.5 12.5 µs 3

Notes:
1 Pulse width depends substantially on value of external pull-up resistor
2 Applies only to data port pins set to 'output / input' operation
3 Timing r eference is DSTBn HL-edge.

Applies only to data port pins set to either 'output / input' or 'input' operation

Rev. C, January 2001 Page 8 of 18

AS-Interface Slave IC
AS2702 (SAP4.1)

The dc-parameters of the data port pins D3, …, D0 are specified as follows:

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IOUTLO Sink current @ output L 10 mA VOUT =

1V
IOUTHI Leakage current @ output of f - 1 1 µA 1
VSCHLT Input thr eshold voltage 2.5 3.5 V 2
VIN Acceptable input voltage @

- 0.3 40 V

output off

Notes:
1 Output stage is low-side open-drain; ext. pull-up resistor req uir ed as no pull- up

structure on chip

2 No hysteresis implemented

To govern the data transf er at data port D3, …,D0 strobe pin DSTBn is equipped with a low­side open-drain output switch plus a passive high-side current source with a nom. 10 µA pull­up current capability.
However a second function is assigned to the DSTBn pin which requires it t o be input as well:
if a low-pulse is imposed on DSTBn by external means with a pulse width of at least 50 to 100
ms, the slave device will be put in RESET condition, as described in section “Reset”.

The dc-and timing parameters of strobe pin DSTBn are specified as follows:

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IOUTLO Sink current @ output L 10 mA VOUT = 1V
IOUTHI Leakge current @ output of f - 10 10 µA VOUT = 5V
IINLO Input current @ VIN = 1V - 5 - 20 µA 1
VSCHLT Input thr eshold voltage 1.5 3.5 V 2
VIN Acceptable input voltage @

- 0.3 40 V

output off

tNORESET DSTBn L-phase width, not

50 m s

triggering RESET

tRESET DSTBn L-phase width, trig-

100 ms

gering RESET

CPINEXT Stray capacitance 20 pF
Notes:

1 DSTBn is equipped with an on-chip pull-up curr ent source, which ensures

a sufficiently fast LH-edge upon output switch-off in open-pin condit ion,
to prevent erroneous RESET triggering.
If DSTBn has an external load connected to it,
an additional external pull-up resistor may be needed
to prevent erroneous RESET triggering upon output switch-off

2 No hysteresis implemented

Rev. C, January 2001 Page 9 of 18

AS-Interface Slave IC
AS2702 (SAP4.1)

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(Note that parameter port pins P3, …, P0 are only available on AS2702 package option SOIC
20, not on the SOIC 16 option.)

The transfer of data at P3, …, P0 and the supporting str obe act ion at pin PSTBn takes place
similarly as at D3, …, D0 resp. DSTBn.

Each parameter port pin P3, …, P0 is eq uipped with both a low-side open-dr ain out put switch
plus a passive, but switchable high-side current source with a nom. 10 µA pull-up current ca­pability, and with an input stage.

Though equipped for bidir ect ional data transfer as D3, …, D0, t he par am eter port is less flexi­ble than the data port.
Basically the parameter port is set to behave portwise as

• output, or

• input

depending on the IO-configuration code, written into and stored in the slave device.
The timing of the data transfer is presented in fig. 3.

Strobe signal PSTBn flags and governs the data transfer as follows:
ia) parameter port is set ‘output’:

output data become valid upon the HL-edge of the strobe and will remain so until the
next HL-edge, hence during the entire strobe cycle;

ib) parameter port is set ‘input’:

input data to be valid within a specific time window relative to the HL-edge of the
strobe, after complet ion of the strobe’s L-phase.

Output data as per ia) could be easily latched with the LH-edge of strobe PSTBn, if at all nec­essary.

Px

t

STB

Px

Parameter out Parameter out

Data in

PSTBn

t

PSTBn

t

INPmin

t

INPmax

Fig. 3: Timing of data transfer at paramet er por t P3, …, P0 relative to strobe PSTBn

Rev. C, January 2001 Page 10 of 18

AS-Interface Slave IC
AS2702 (SAP4.1)

The following table specifies the t iming parameters relating to fig. 3:

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tSTB Delay PSTBn HL-edge to Px

1.5 µs

output data valid

tPSTBn PSTBn strobe width 6 6.8 µs 1
tINP Input data valid time window 10.5 12.5 µs 2

Notes:
1 Pulse width depends substantially on value of external pull-up resistor
2 Timing r eference is PSTBn HL-edge.

Applies only to parameter port set to 'input ' operation

The dc-parameters of the parameter port pins P3, …, P0 are specified as follows:

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IOUTLO Sink current @ output L 10 mA VOUT = 1V
IOUTHI Leakage current @ output of f - 10 10 µA VOUT = 5V
IOUTHI7 Leakage current @ output off;

pull-up current source off

- 1 1 µA VOUT = 5V;
IO-conf. = 7

IINLO Input current @ VIN = 1V - 5 - 20 µA 1
VSCHLT Input thr eshold voltage 2.5 3. 5 V 2
VIN Acceptable input voltage @

- 0.3 40 V

output off

Notes:
1 The passive high-side curr ent -source provides an about constant input current @

0V <= VIN <= 4V

2 No hysteresis implemented

Though equipped for bidir ect ional data transfer as D3, …, D0, t he par am eter port is never­theless less flexible than the data port.
Note the following differences:
ik) The parameter por t is set portwise, the data port bitwise by the IO-configuration code;
il) The parameter port can only be set t o either ‘output’ or ‘input’. A bidirect ional behaviour
within a strobe cycle is not possible;
im) The parameter port is set t o ‘output’ as a rule; the only exception occurs in case of IO­configuration 7 and a master data request, which set it to ‘input’.

To govern the data transf er at the parameter port P3, …, P0 st robe pin PSTBn is equipped
with a low-side open-drain output switch plus a passive high-side current source with a nom.
10 µA pull-up current capability. Typically the PSTBn-strobe width is about 6 µs , see fig. 3.
( However to simplify and shorten the component test t im e of the slave device, the PSTBn pin
is also used as an input. Input low pulses of more than 50 µs each will step and cycle the de­vice through 3 different testmodes beyond the regular operation as described in this da­tasheet.)

Rev. C, January 2001 Page 11 of 18

AS-Interface Slave IC
AS2702 (SAP4.1)

The dc- and timing parameters of strobe pin PSTBn are specified as follows:

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IOUTLO Sink current @ out put L 10 mA VOUT = 1V
IOUTHI Leakage current @ output off - 10 10 µA VOUT = 5V

IINLO Input current @ VIN = 1V - 5 - 20 µA 1
VSCHLT Input threshold voltage 1.5 3.5 V 2
VIN Acceptable input voltage @ out -

- 0.3 40 V

put off

tNOTM PSTBn L-phase width, not trig -

35 µs

gering testmode

tTM PSTBn L-phase width, triggering

50 µs

testmode

CPINEXT Stray capacitance 20 pF

Notes:
1 PSTBn is equipped with an on-chip pull-up current sour ce, which ensures

a sufficiently fast LH-edge upon output switch-off in open-pin condit ion, t o prevent
erroneous testmode triggering.
If PSTBn has an external load connected to it, an additional external pull-up resistor
may be needed to prevent erroneous testmode trig gering upon output switch-off

2 No hysteresis implemented

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Pins LED1 and LED2 are both equipped with a low-side open-drain output switch plus a pas­sive high-side current source with a nom. 10 µ A pull-up current capability. They will each have
an LED load connected to UOUT, which will flag the operation st atus of the slave device, ac­cording to the following t able:

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off off Supply voltage off No supply voltage
on off Regular operation
off on 4 No Data

Communication

Regular, non-zero
slave address coded;
data comm. watchdog
triggered

blinks on 3 No regular slave

address coded

blinks blinks

(alternating with

LED1)

2 Hardware failure in

sensor / acuator
circuitry

off blinks 1 External RESET or

Overload at UOUT
pin

Slave address = de­fault zero
Input PFAULT = L

DSTBn = L to RESET,
or UOUT switched-off
due to overload

5HDVRQ

(LED1 and LED2 both also feature an input stage, to simplify component test and shor ten test
time of the slave device.)
The dc- and timing parameters of pins LED1 and LED2 are specified as follows:

Rev. C, January 2001 Page 12 of 18

AS-Interface Slave IC
AS2702 (SAP4.1)

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ILED Sink current @ output L 10 mA VOUT = 1V
IOUTHI Leackage current @ output off - 10 10 µA VOUT = 5V

VIN Acceptable input voltage @ out-

put off

fBLINK Blinking fr equency 2 3 Hz

- 0.3 40 V

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AS2702 is equipped with a watchdog timer to supervise data communication by monitoring
the strobe signals at pins DSTBn and PSTBn.
If a parameter or dat a st r obe is not followed by a consecutive strobe within a time period of
50 … 100 ms, the watchdog is trigg er ed and initiates a ‘soft’ reset, see section ‘Reset ’

5(6(7

There are 2 categories of r eset - events, leading to 2 slightly different reset-conditions of the
slave device:

1) a ‘hard’ reset taking place at power-up and power-down of supply-voltag es U5R and
UOUT.
At power-up the slave device leaves reset-condition as soon as U5R has passed 3.75V
and UOUT has passed VCOMOFF = nom. 10V.
At power-down the slave device is forced into reset-condition as soon as U5R drops below

3.75V.
(Tolerance of the threshold voltages referred to is -/+ 5%. )

2) a ‘soft’ reset, resulting from one of the f ollowing events:

2.1) Data strobe pin DSTBn is kept L for more than 100 ms;

2.2) Master command ‘RESET SLAVE’ is received;

2.3) Master command ‘RESET BROADCAST ’ is r eceived;

2.4) The communication watchdog is triggered.

A ‘hard’ reset event conditions the slave device as follows:

• Internal states (counters, f lag s, …) ar e r eset

• The slave device’s receiver is desynchronized from the AS-interface bus

• The low-side open-drain output stages at port s D3, …, D0 and ports P3, …, P0 are

switched off

• Any test-mode will be cancelled.

A ‘soft’ reset has the following conseq uences:

• A regular, nominal 6µs L-phase strobe is generated on both the DSTBn and PST Bn pin

• The low-side open-drain output stages at port s D3, …, D0 and ports P3, …, P0 are

switched off

• Internal states (counters, f lags, …) are reset, however the following states and operations
are not affected:

• the timer function which controls blinking of LED1 and LED2

• the data comm unicat ion watchdog

• any testmode

• any EEPROM write operation.

Remark:

Rev. C, January 2001 Page 13 of 18

AS-Interface Slave IC
AS2702 (SAP4.1)

If UOUT drops below VCOMOFF = nom. 10V data comm unication with the AS-interface bus is
aborted by the receiver or transmitter of the slave device. As long as U5R does not drop be-

low 3.75V in this situation, no ‘hard’ reset tak es place; however the data com m unicat ion
watchdog will be triggered (unless disabled) and a ‘soft’ reset will result.

((3520

AS2702 has a 16 x 8 Bits serial interface EEPROM on board to store the slave unit’s address
and set-up data in a non-volatile fashion.

The EEPROM stores the following data:

((3520

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0, 1 Slave Address 5 + 1 Master (Initialization) 1

2 Settings (EID1) 4 Master (Initialization)
3 Sett ings (IO-Conf.) 5 Slave unit manufacturer
4 Settings (ID) 5 Slave unit manufacturer
5 Settings (EID2) 5 Slave unit manufacturer
6 Settings (Control-

5 Slave unit manufacturer

Code)

Note
1 6 Bits (A4, …, A0 + Sel- bit ) in extended address mode: 62 slaves addressable;

5 Bits (A4, …, A0) in non-extended address mode: 31 slaves addressable
Obviously the capacity of the EEPROM is only partially used.
Reading and writing of the EEPRO M is perf ormed bytewise and trough temporary, volatile

registers.
Writing of data from t he volatile r egister into the EEPROM takes about 10 ms per byte,
whereas reading takes less than 1 ms per byte.

Upon RESET the EEPROM info is read into temporar y registers, including the slave’s address
which has been written redundantly into EEPROM locations 0 and 1 before.
The temporary registers receiving t he addr ess are compared for similarity; in case of non­similarity – which e.g. may have been caused by a supply voltage dip during address writing –
the slave will flag non-regular operation status / slave address zero.

Rev. C, January 2001 Page 14 of 18

AS-Interface Slave IC
AS2702 (SAP4.1)

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All slaves connected to an AS-interface bus are sequent ially and cyclicly called by the master
in a string of individual transactions between the master and each slave unit.

A transaction consists of a 14 bits mast er request, typically containing the slave’s address as
well as data or parameter info, and an imm ediat e acknowledging slave response of 7 bits.

The 14 bits master request - apar t from Start Bit ST = 0 and End Bit EB = 1 – has the follow­ing contents:

• 1 Control Bit CB: CB = 0 stands for data transfer (typ. data or par ameters)

CB = 1 identifies command-type request s

• 5 Address Bits: A4, …, A0

• 5 Information Bits: I4, …, I0 (typ. data or parameters)

• 1 Parity Bit PB.

AS2702 allows for up to 62 slaves on the same AS-interface bus; this requires a slave ad­dress extended to 6 bits, hence an extra bit beyond A4, …, A0.
Information bit I3 is used as t he 6
called Sel-bit, as it is perceived as to select between A-slave (Sel = 0) and B-slave (Sel = 1) at
address location A4, …, A0.
In non-extended address mode AS2702 is addressed with A4, …, A0 only - for a max. total of
31 slaves per AS-interface bus system, and is system compat ible with existing slave device
AS2701A.

th

address bit in this so-called extended address mode. It is

The 7 bits slave response – apart from Start Bit ST = 0 and End Bit EB = 1 – has the f ollowing
contents:

• 4 Information Bits: I4, …, I0 (typ. data or parameters)

• 1 Parity Bit PB.

Detailed descriptions of all types of mast er requests and corresponding slave responses can
be found in AS-Interface Specification V2.11, obtainable from the AS-Internat ional Association
(D) or its local representative, see section “Applicat ion Support”.

Rev. C, January 2001 Page 15 of 18

AS-Interface Slave IC
AS2702 (SAP4.1)

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Sensor/actuator circuit supplied by the ASI Slave IC (UOUT) for supply current needs

≤ 50 mA.

C2

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C4

C1 = 100 nF / 35 V
C2 = 100 nF / 6 V

C3 = 10...470 µF / 30 V
C4 = 22...100 nF / 30 V
V1 = 1N4002 or equivalent
V2 = TGL 41-39A or equivalent
G1 = AS-Interface Crystal 5. 333 MHz

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AS2702 works fine with the following crystal types:
CitizenCM 309

Philips SQ 4849
AS-Interface quartz crystals are available from:
Endrich GmbH Geyer electronic

Contact: Axel Gensler Contact: Jürgen Blank
Hauptstr. 56 Camerloher st r. 71
D-72202 Nagold D-80689 München
Tel.: [phone] Tel.: [phone]
Fax: [phone] Fax: [phone]
Email: [e-mail]

Rev. C, January 2001 Page 16 of 18

AS-Interface Slave IC
AS2702 (SAP4.1)

Kinseki Europe GmbH Rutronik Elektronische Bauelem ente GmbH
Contact: Dirk Holstein Contact: Jürgen Tischhauser

Schirmer Str. 76 Indust r iestrasse 2
D-40211 Düsseldorf D-75228 Ispringen / Pf or zheim
Tel.: [phone] Tel.: [phone]
Fax: [phone] Fax: [phone]
Email: [e-mail] Email: [e-mail]

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For general information and docum ent ation on the AS-Interface concept you may contact one
of the following AS-Inter face Associations:

AS-International Association

Contact: Rolf Becker
Zum Taubengarten 52
D-63571 Gelnhausen
Tel.: [phone]
Fax: [phone]
Email: as-interface@t - online.de

AS-Interface Switzerland AS-Interface France

Contact: Rainer Schnaidt Contact: Gilles Mazet
Bittertenstraße 15 5 rue Nadar
CH-4702 Oensingen F-92566 Rueil Malmaison cedex
Tel.: [phone] Tel.: [phone]
Fax: [phone] Fax: [phone]
Email: [e-mail] Email: [e-mail]

AS-Interface Italy AS-Interface The Nederlands

Contact: Maurizio Ghizzoni Contact: Andre Braakman
Via G.B. Barinetti, 1 Boerhaavelaan 40
I-20145 Milano NL-2700 AD Zoetermeer
Tel.: [phone] Tel.: [phone]
Fax: [phone] Fax: [phone]
Email: [e-mail] Email: [e-mail]

AS-Interface Gr eat Britain AS-Interface USA

Contact: Geoff Hodgkinson Contact: Michael Bryant
1 West St r eet 16101 N. 82
GB-PO 14 4DH Titchfield, Hampshire USA-85260 Scottsdale, Arizona
Tel.: [phone] Tel.: [phone]
Fax: [phone] Fax: [phone]
Email: [e-mail] Email: mbryant@g oodnet.com

AS-Interface Belgium AS-Interface Sweden

Contact: Maurice de Smedt Contact: Lars Mattsson
Avenue Paul Hymanslaan 47 Karl Nordströms väg 31
B-1200 Bruxelles-Brussel SE-43253 Varberg
Tel.: [phone] Tel.: [phone]
Fax: [phone] Fax: [phone]
Email: [e-mail] Email: lars-m attsson@marknadspartnerm o l. se

nd

Street, Suite 3B

Rev. C, January 2001 Page 17 of 18

AS-Interface Slave IC
AS2702 (SAP4.1)

%LEOLRJUDSK\

ASI: The Actuator-Sensor- I nt erface for Automation
Edts.: Werner Kriesel, Otto W. Madelung
Carl Hanser Verlag, Munich and Vienna, 1995
ISBN: 3-446-18265-9

2UGHULQJ,QIRUPDWLRQ

AS2702-20T Package: SOIC 20; delivery: tape & reel
AS2702-16T Package: SOIC 16 W; delivery: tape & reel; no paramet er por t available
AS2702-20 Package: SOIC 20; delivery: tubes
AS2702-16 Package: SOIC 16 W; delivery: tubes; no parameter port available

Copyright  2000, Austria Mikro S ysteme International AG, Schloß Premstät t en, 8141 Unterpremstätten, Austria.

Tel. [phone], Fax [phone], E-Mail info@amsi nt.com
All rights reserved. No part of this publication m ay be reproduced, stored in a retrieval syst em, or transmitt ed, in any form or by
any means, without the prior permission in writing by the copyright hol der. To the best of its knowledge, A ustria Mikro Systeme
International asserts that the information contained in this publication i s accurate and correct.

Rev. C, January 2001 Page 18 of 18