• Transmission of both power and signal on the AS-Interface line
• Decoupling of power and signal by the IC without additional external devices
• Transmitting protocol for using the IC and the AS-Interface master in the trans-
mit/receive modes
• Switching of max. 31 AS-Interface slave ICs on one bus possible
• Power supply of peripheral devices from the AS-Interface slave IC of up to 35mA@24V
• Only few external devices necessary for operation (quartz, 4 capacitors, E2PROM)
• Storing of the configuration data and the slave address in one E2PROM
• Quartz oscillator for 5.333 MHz without external capacitances
• Standards: AS-Interface–Spec V2.0 and EN 50295
General Description
The signal transmission between the master and the slaves in the AS-Interface system is
performed by a parallel two-line wire (AS-Interface line) to which the IC is connected only via a
polarity protection diode and a suppressor diode. The line is powered by a direct dc voltage of
up to 33.1 V, on which data pulses with signal amplitudes of (3...8) Vpp are superimposed.
The IC extracts its own power and the power for peripherals from the line and detects the bus
signals.
The AS-Interface slave IC consists of the following blocks:
• Receive Block
• Transmit Block
• Digital Logic Block
• Emergency Control Block
• Internal and External Power Supply with Signal decoupling
• Oscillator
• Power on Reset
• High Voltage I/O
Block Diagram
TEST
LTGP
Emergency and
Control Block
LTGN
switch
Temperature
Transmit Block
Receive Block
Power-On
Reset
Internal Power
Supply
imp_pos, imp_neg
Oscillator
OSC1
OSC2
Signal Decoupling
Ext. Power Supply
E2-Interface
Digital
Block
HV-
I/O
Rev. C, October 2000Page 2 of 16
CDC
UOUT
U5R
SCL
SDA
D0...D3
DSTBn
P0...P3
PSTBn
Page 3
AS-Interface Slave IC
AS2701A (ISA3+)
Package
SOIC20
Pin Description
D3
D2
D1
D0
DSTBn
U5R
TEST
SCL
SDA
LTGN
1
2
3
4
5
6
7
8
9
10
20
P3
19
P2
18
P1
17
P0
16
PSTBn
15
14
13
12
11
OSC2
OSC1
UOUT
CDC
LTGP
PinNameTypeDescription
1D3I/OData input/output 3, configurable
2D2I/OData input/output 2, configurable
3D1I/OData input/output 1, configurable
4D0I/OData input/output 0, configurable
5DSTBnI/OStrobe output for the data port,
input for a reset signal (active low)
6U5RVoltage OUTSupply voltage of the E2PROM,
Blocking capacitor CU5R
7TESTINConnection to the capacitor CTEST
8SCLOUTSerial two-wire bus, puls wire
9SDAI/OSerial two-wire bus, address and data wire
10LTGNSUPPLYAS-Interface wire, negative supply
11LTGPSUPPLYAS-Interface wire, positive supply
12CDCVoltage OUTBlocking capacitor CCDC
13UOUTVoltage OUTPeripherals
14OSC1INQuartz connection
15OSC2OUTQuartz connection
16PSTBnOUTStrobe output for the parameter port, test mode
The IC identifies and decodes the supply voltage overlapping signals of the master telegram. If
the slave address contained within the master telegram coincides with the stored information
in the E2PROM of the slave address, the corresponding master command of the addressed
AS-Interface slave IC is executed.
After decoding of the master telegram the addressed AS-Interface slave IC responds with a
corresponding slave answer on the AS-Interface line.
The AS-Interface slave IC extracts its own supply voltage and the supply voltage for the
E2PROM from the AS-Interface line. At the same time, the IC provides a direct voltage for the
peripheral UOUT which results from U
LTGP-UDROP
The receive block detects the signal on the AS-Interface wire LTGP. The reference voltages of
the signal comparators are (52.5 ± 5) % of the maximum signal value and are controlled by a
peak value detector in the following mode: The comparator level is set to its default value by
Reset or if a non-correct signal is received.
for a maximum current of 35 mA.
If a line pause is detected, the level reset is released and the IC is able to adapt itself to
different signal levels. If the IC is not synchronized yet, the level adaption is faster (smaller
attack and decay time constants) as in the synchronous case.
The output information of the receive blocks are the signals: "imp_pos" and "imp_neg".
The transmit block drives the output level for the modulated transmit signal edges. The
transmit block consists of the NMOS transistor (transmit transistor), DAC for transmit signal
formation and a Jabber-Inhibit Circuitry. The DAC is addressed by the digital block. If the
transmitter is active more than typ. 300µs the Jabber-Inhibit circuit separates the IC from the
AS-Interface line. This condition can only be left by a Power-On-Reset.
In the digital block the received signal is analyzed, the transmit signal is generated and the
data and parameter ports as well as the E2PROM interface are driven. The E2PROM interface
acts as a serial two-wire interface with the following transmission streams:
SDA S
1100 A2 A1 A0 0
Byte Write Cycle
1100 A2 A1 A0 0
Byte Read Cycle
Device-AddressByte-Address
ACK
R/W
Device-AddressByte-Address
ACK
R/W
ACK
ACK
Data
Device-Address
1100 A2 A1 A0 1
ACK
R/W
P
ACK
Data
PSSDA S
ACK
After the AS-Interface slave IC has sent the START condition, the device address is
transmitted. This address would allow the selection of a maximum of 8 possible E2PROM ICs,
is however fixed to 000 by the AS-Interface slave IC. Therefore in the application pins AO...A2
of the E2PROM are connected to Uss.
Rev. C, October 2000Page 4 of 16
Page 5
AS-Interface Slave IC
AS2701A (ISA3+)
Write Cycle
After the device address, the write cycle R/W-Bit=0, necessary for the identification of the write
cycle, is sent. The E2PROM acknowledges the correct receipt with the acknowledge bit ACK.
Then the data byte which should be written into the E2PROM reacknowledges with an ACK
signal of the E2PROM. The STOP condition ends the cycle.
Read Cycle
The read cycle is similar to the herein described write cycle. In this case the R/W-Bit = 1 which
causes the E2PROM to place read data for the received Byte address on the bus after the
acknowledge.
SDA
SCL
START
Condition
STOP
Condition
The START condition is recognized by the E2PROM when a H/L edge arises on the dataline
SDA during the high phase of the clock.
The STOP condition is present when a L/H edge arises on the dataline SDA during the high
phase of the clock SCL. The timing of the E2PROM interface is derived from the AS-Interface
quartz frequency of 5.333 MHz.
Rev. C, October 2000Page 5 of 16
Page 6
AS-Interface Slave IC
AS2701A (ISA3+)
Functional, electrical and timing characteristics
All voltages are referenced to LTGN = 0V, timing is valid for a clock frequency of 5.333 MHz.
a) Absolute Maximum Ratings
SymbolParameterMinMaxUnitNote
VLTGPPositive Voltage- 0.340V1
VLTGPOVPositive Impulse Voltage50V2
Vin1Voltage at D0…D3, P0…P3,
DSTBn, PSTBn, CDC, UOUT,
TEST
Vin2Voltage at OSC1, OSC2, SDA,
SCL, U5R
IinInput Current on every Pin-2525mA
HNon-Condensated Humidity3
ESDElectrostatic Discharge1000V4
θSTG
θlead
PtotPower Dissipation1W6
Notes:
1 A polarity protection diode is to be used externally
2 Impulse width: ≤ 50 µs; repetition rate: ≤ 0.5 Hz
3 Defined in DIN 40040 cond. F
4 HBM; R = 1.5 kΩ; C = 100pF
5 260 °C for 10 s (reflow and wave soldering), 360 °C for 3 s (manual soldering)
6 SOIC 20: Rthja = 64.5 °K/W typ.
d) Data and Parameter Ports (D0...D3, DSTBn; P0...P3, PSTBn)
These pins are equipped with both an input and output channel as well as a current source
based pull-up structure; the I/O-circuit at these pins and their DC-characteristics @ output
channel 'Off' are described below.
The AS-Interface slave system concept requires D0...D3 and DSTBn to be bidirectional pins
and P0...P3 and PSTBn to be outputs.
The input channel on pins P0...P3 and PSTBn is only implemented to simplify the AS-Interface
Slave IC's device test, and is not intended to be used in AS-Interface Slave system applications.
U5R
11 µA typ
II[µA]
0
-5
-10
-15
D0..D3
DSTBn
P0..P3
PSTBn
LTGN
-20
4010203040
VI[V]
Rev. C, October 2000Page 7 of 16
Page 8
AS-Interface Slave IC
AS2701A (ISA3+)
SymbolParameterminmaxUnitNote
VILInput Voltage “Low”01.5V
VIHInput Voltage “High”3.5VUOUTV
VHYSTInput Hysteresis0.250.5V1
VOL11Output Voltage01VIOL11 = 10mA
on DSTBn
Notes:
1 Switching points approx. 2.5 V, i.e. 2.5 V ± VHYST
2 For larger capacitive loads an external Pull-Up-Resistor to UOUT must be used, so that
the beginning of the DSTB = LOW impulse of VIH ≤ 3.5 V to DSTBn is reached in less than
35 µs, otherwise a reset is the result.
Timing characteristics
SymbolParameterminmaxUnitNote
t
DSTBL
t
DSTBH
t
DATA
t
DSTB
t
DINon
t
DINoff
t
CYCLE
t
ALM1
t
ALM2
Note 1: Data valid until DSTBn L/H-edge
DSTBn to D0…D3, Direction OUT,
1µs
Output Data LOW
DSTBn to D0…D3, Direction OUT,
1.5µs
Output Data HIGH
DSTBn to D0…D3, High Resistive6.27µs1
DSTBn Pulse Width66.8µs
DSTBn to D0…D3, Direction IN, Valid
6.57.7µs
Input Data
DSTBn to D0…D3, End of Direction IN12.5t CYCLEµs
Next Cycle150µs
Extension DSTBn to D0…D3, High
44µs
Resistive
Extension DSTBn (No Reset)35µs
Rev. C, October 2000Page 8 of 16
Page 9
AS-Interface Slave IC
AS2701A (ISA3+)
D0..D3
D0..D3
D0..D3
D0..D3
D0..D3
t
DINoff
data in
t
DINon
t
DSTBL
data out LOW
data out HIGH
t
DSTBH
t
DSTBL
data outdata in
t
DATA
t
DINon
t
DINoff
t
DSTBH
data outdata in
HI-Z
HI-Z
HI-Z
Direction of Input
HI-Z
Direction of Output
HI-Z
HI-Z
Bidirectional
HI-Z
DSTBn
DSTB
(ext. LOW)
t
DSTB
t
ALM2
t
ALM1
t
CYCLE
(t
RESET1
)
Rev. C, October 2000Page 9 of 16
Page 10
AS-Interface Slave IC
AS2701A (ISA3+)
e) Interface to the ext. E2PROM (U5R, SCL, SDA) / functional,
electrical and timing characteristics
SymbolParameterminmaxUnitNote
VU5ROutput Voltage to E2PROM4.55.5V
IU5R ≤ 3 mA
CU5RLoad Capacity to U5R10220nFCeramics capacitor
IU5ROutput Current to U5R3mA
VOLOutput Voltage “Low”00.2 * VU5RVIOL = 10 µA
VOHOutput Voltage “High”0.8 * VU5RVU5RV-IOH = 10 µA
VILInput Voltage “Low” (only SDA)-0.30.3 * VU5RV-IIL = 1.5…0.2mA
VIHInput Voltage “High” (only SDA)0.7 * VU5RVU5R + 0.3VIIH = -1…1 µA
t
DATAinSU
t
DATAinHO
t
AA
Set-up Time for Data Input0.25µs
Hold Time for Data Input0µs
Time from SCK Low to SDA
3.5µs
Data Out and ACK Out
t
DATAoutHO
t
STARTSU
t
STARTHO
t
STOPSU
t
BUF
Hold Time for Data Output0.3µs
Set-up Time for Start Condition4.7µs
Hold Time for Start Condition4µs
Set-up Time for Stop Condition4.7µs
Time which has to be Free for
4.7µs
Bus: Before Next Transmission
t
R
t
F
t
LOW
t
HIGH
t
SCL
Rise Time1000ns
Fall Time300ns
Impulse LOW Time4700ns
Impuls HIGH Time4000ns
Clock Frequency for E2PROM100kHzfc = 5.333 MHz
t
F
LOW
t
AA
t
HIGH
t
t
DATAinHO
R
t
DATAoutHO
t
DATAinSU
t
STOPSU
t
R
t
BUF
SCL
SDA in
SDA out
t
STARTSU
t
F
t
STARTHO
t
The U5R supply pin provides a typically 5V supply voltage to the external E2PROM, and has a
biasing capability only for this purpose.
Programming of the E2PROM is possible with the E2PROM soldered-in into the AS-Interface
Slave unit's pc-board by accessing the SCL / SDA serial bus with an external programming
hardware.
Rev. C, October 2000Page 10 of 16
Page 11
AS-Interface Slave IC
AS2701A (ISA3+)
For successful programming the programmer hardware must have sink/source capability of at
least 5 mA, and the AS-Interface Slave IC's supply voltage LTGP has to be in the range of
26.65 V ...33.35 V.
The only E2PROM address locations which can be programmed through the AS-Interface
Slave IC (hence over the AS-Interface Bus and by the AS-Interface Master), are locations 0
and 1, which both have been reserved for the AS-Interface Slave unit's address.
The E2PROM has to be programmed in the following way:
E2PROM
Address
0000AS-Interface address0
1000AS-Interface address0
2ID CodeIO ConfigurationCustom Specific Data
3ID CodeIO ConfigurationCustom Specific Data
VDROPVoltage Drop from LTGP
IUOUTOutput Current UOUT035mA11.0 V < VUOUT < 27.6 V
Overswing Impulse Width2.ms
5.56.7V
to UOUT
VLTGP –
VDROPmin
1.5VCUOUT = 10 µF:
VIUOUT = 35 mA
Switching 0-35 mA - 0
CUOUTLoad Capacity UOUT10470µF
The interface is intended for the supply voltage to actuators, sensors as well as external
circuits with a power supply of <35mA without overloading the AS-Interface line in the range of
the signal frequency. The AS-Interface slave IC has an internal circuit protector which limits the
current during the charging of the load capacitor and which effects a power down at thermal
overload, e.g. at too high output currents.
In the case of a current break down on the AS-Interface line of less than 1ms, the internally
stored information is retained. The supply voltage of the IC during this time is extracted from
the capacitor Pin UOUT which is disconnected from the AS-Interface line.
Rev. C, October 2000Page 11 of 16
Page 12
AS-Interface Slave IC
AS2701A (ISA3+)
Reset Behaviour
The AS-Interface Slave IC can be in reset condition or reset by the following events:
•at power-up of VLTGP: as long as VUOUT has not yet reached the treshold voltage
9 V ≤ VCOMOFF ≤ 11 V;
•at power-down of VLTGP: as soon as U5R drops below the treshold voltage
3.5 V ≤ VPOR ≤ 4 V;
• by a 'L' input level to DSTBn for more than 44 µs;
• resulting from a “Reset AS-Interface Slave“- command by the AS-Interface Master
over the AS-Interface BUS.
The different levels of VCOMOFF and VPOR as per a) and b) and the fact that the U5R supply
voltage results from a down-regulation of the VUOUT supply assure a desirable hysteresis in
the order of several volts between the VUOUT power-on-reset and power-down-reset
threshold. Whereas at power-up the AS-Interface Slave IC is released from reset by VUOUT
reaching a level of between 9 V and 11 V, at power-down VUOUT has to come down to a level
in the order of 5 V for U5R to drop into the reset-triggering window between 3.5 V and 4 V.
Some different power-down events are illustrated below:
t
VLTGP
18 V
POR
(internal signal)
1
0 V
Loff
VUOUT
VCOMOFF
(no reset)
2
neither receive
nor transmit
VUOUT
VCOMOFF
VU5R
VPOR
3
(reset)
Notes:
as to (1):No reset will be triggered, if VLTGP is lower than 18 V for less than 1 ms
as to (2):If VUOUT < VCOMOFF but still U5R > VPOR, communication over the Data
Port is inhibited, but no reset triggered
as to (3):If U5R < VPOR (resulting from VUOUT << VCOMOFF), a reset is triggered.
Reset is overcome as soon as VUOUT > VCOMOFF (implying U5R > VPOR)
In reset condition internal registers are cleared and data port D0...D3 is switched into highimpedant condition. After release from reset the AS-Interface Slave automatically performs a
first read cycle to clear the E2PROM from any previously interrupted communication state and
a second one to load the AS-Interface address, IO Configuration and ID Code into its internal
registers.
SymbolParameterminmaxUnitNote
t resetReset Time after the Master
2ms
Command “Reset AS-Interface Slave”
or DSTBn = ext. L/H-Edge
t reset2Reset Time after Power On30ms
t reset3Reset Time after Power On with great
1000msCUOUT = 470 µF
Load Capacity
t LoffVoltage Breakdown Time1msCUOUT > 10 µF
VCOMMoffVoltage for “Communication OFF”911V
VPORVoltage for Internal Reset3.54V
Rev. C, October 2000Page 12 of 16
Page 13
AS-Interface Slave IC
AS2701A (ISA3+)
Application Example 1:
Sensor/actuator circuit supplied by the AS-Interface Slave IC (UOUT) for supply current needs
≤35 mA.
1
A2
A1
SCL
TEST
C2
A0
U5R
VSS
E2PROM
SDA
ASI-N
ASI Line
LTGN
V2
LTGP
V1
C4
SCL
SDA
ASI-Slave-IC
CDC
UOUT
TEST
OSC1
U5R
OSC2
D0
DSTBn
PSTBnP0P1
1
D1
D2
D3
P2
P3
Customer Interface
ASI-P
C1
C3
C5
G1
C1 = 22...470 nF / max. AS-Interface BUS DC voltage
C2 = 10...220 nF / max VU5R = 5.5 V
C3 = 10...470 µF / max. (VUOUT + VUOUTp) = 29.1 V
C4 = 22...100 nF / max. (VUOUT + VUOUTp + 1.4 V) = 30.5 V
C5 = 10...100 nF (close to the IC) / max. (VUOUT + VUOUTp) = 29.1 V
V1 = 1N4002 or equivalent
V2 = TGL 41-39A or equivalent
G1 = AS-Interface Crystal 5.333 MHz
For V2 a limiter diode with a small capacitance value should be selected, to ensure that the
AS-Interface Bus can be operated with the maximum number of Slave units connected.
In a more general sense care should be taken that the pc board tracks and the external
components between the AS-Interface Bus and LTGP / LTGN contribute to the AS-Interface
Slave unit's input impedance inductively and highly resistively, rather than capacitively.
Rev. C, October 2000Page 13 of 16
Page 14
AS-Interface Slave IC
ASI-Slave-IC
E
2
AS2701A (ISA3+)
Application Example 2:
Sensor / actuator circuit supplied from the AS-Interface Bus for supply current needs > 35 mA.
It is recommended to protect the AS-Interface Bus by a fuse in this set-up, if there is a high risk
of excessive current extraction due to component failure (e.g.: MC1747 or other components in
the sensor / actuator circuitry).
4
ASI-P
ASI-N
100n
2,2mH 2,2mH
100n 100n
ST24C01
8
VCC
4
VSS
5
100n100n
10
LTGN
11
LTGP
12
CDC
5
DSTBn
16
PSTBn
14
OSC1
15
OSC2
17
P0
18
P1
19
P2
20
P3
SDA
SCL
TEST
U5R
UOUT
9
8
7
6
13
4
D0
3
D1
2
D2
1
D3
SDA
PROM
7
MODE
6
SCL
1
E0
2
E1
3
E2
A
K
C
E
U+
5
-
7
+
8
U-
MC1747
11
RF
10
U1
130k
12k
100n
100n10µ
130k
2,2mH 2,2mH
AS-Interface Quartz 5.333 MHz
AS2701A works fine with the following crystal types:
Citizen CM 309
PhilipsSQ 4849
AS-Interface quartz crystals are available from:
Endrich GmbHGeyer electronic
Contact: Axel GenslerContact: Jürgen Blank
Hauptstr. 56Camerloherstr. 71
D-72202 NagoldD-80689 München
Tel.: +49-7452-6007-31Tel.: +49-89-546868-13
Fax: +49-7452-6007-70Fax: +49-89-546868-90
Email: a.gensler@endrich.com
Rev. C, October 2000Page 14 of 16
Page 15
AS-Interface Slave IC
AS2701A (ISA3+)
Kinseki Europe GmbHRutronik Elektronische Bauelemente GmbH
Contact: Dirk HolsteinContact: Jürgen Tischhauser
Schirmer Str. 76Industriestraße 2
D-40211 DüsseldorfD-75228 Ispringen / Pforzheim
Tel.: +49-211-36815-33Tel.: +49-7231-801543
Fax: +49-211-36815-10Fax: +49-7231-801633
Email: dholstein@kinseki.deEmail: juergen_tischhauser@rutronik.com
Application Support
a) For general information and documentation on the AS-Interface concept you may contact
AS-Interface ItalyAS-Interface The NederlandsContact: Maurizio GhizzoniContact: Andre BraakmanVia G.B. Barinetti, 1Boerhaavelaan 40I-20145 MilanoNL-2700 AD ZoetermeerTel.: +39-02-66761Tel.: +31-79-353-1269Fax: +39-02-6676-3491Fax: +31-79-353-1365Email: maurizio.ghizzoni@siemens.itEmail: ABA@FME.NL
AS-Interface Great BritainAS-Interface USAContact: Geoff HodgkinsonContact: Michael Bryant1 West Street16101 N. 82GB-PO 14 4DH Titchfield, HampshireUSA-85260 Scottsdale, ArizonaTel.: +44-1329-511882Tel.: +1-480-368-9091Fax: +44-1329-512063Fax: +1-480-483-7202Email: asi_uk@gghcomms.demon.co.ukEmail: mbryant@goodnet.com
nd
Street, Suite 3B
Rev. C, October 2000Page 15 of 16
Page 16
AS-Interface Slave IC
AS2701A (ISA3+)
AS-Interface BelgiumAS-Interface SwedenContact: Maurice de SmedtContact: Lars MattssonAvenue Paul Hymanslaan 47Karl Nordströms väg 31B-1200 Bruxelles-BrusselSE-43253 VarbergTel.: +32-2-771-3912Tel.: +46-3406-29270Fax: +32-2-771-1264Fax: +46-3406-77190Email: m.desmedt@udias.beEmail: lars-mattsson@marknadspartnermol.se
b) A demoboard, equipped with AS2701A and supporting discrete components, is available
from:
Bihl & Wiedemann GmbHLeuze electronic GmbHMr. BihlMr. KellerKäfertaler Straße 164In der Braike 1D-68167 MannheimD-73277 Owen/TeckTel.: +49-621-339-2723Tel.: +49-7021-573-248Fax: +49-621-339-2239Fax: +49-8021-573-200
c) Technical hotline assistance is provided by:
Bihl & Wiedemann GmbH (see above)
Bibliography
ASI: The Actuator-Sensor-Interface for Automation
Edts.: Werner Kriesel, Otto W. Madelung
Carl Hanser Verlag, Munich and Vienna, 1995
ISBN: 3-446-18265-9
Copyright 2000, Austria Mikro Systeme International AG, Schloß Premstätten, 8141 Unterpremstätten, Austria.
Telefon +43-(0)3136-500-0, Telefax +43-(0)3136-52501, E-Mail info@amsint.com
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any
means, without the prior permission in writing by the copyright holder. To the best of its knowledge, Austria Mikro Systeme International
asserts that the information contained in this publication is accurate and correct.
Rev. C, October 2000Page 16 of 16
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