Datasheet AS2350N, AS2350D, AS2333N, AS2333D, AS2316N Datasheet (ASTEC)

AS23xx

Secondary Side Housekeeping Circuit

Features

Standard PC Power Good:

•

UV Detection on 4 rails
UV Detection of AC/Bulk supply
OV Detection on 4 rails
Open collector PG out

Pogrammable Fault output:

•

OV
OV plus UV
OV plus UV after startup delay

OV Crow Bar Driver

•

Digital ON/OFF input

•

2.5V Voltage Reference

•

Operates from 5V or 12V rail

•

Pin Configuration

1V

CC

2+12V V

3+5V UVB

4+3.3V DELAY

5-5V POK

6-12V PGCAP

7GND AC

HYST OFF

8

AS2316 SOIC

16

FAULT

15

REF

14

13

12

11

10

9

1V

CC

2+12V V

3+5V UVB

4+3.3V DELAY

5-5V POK

6-12V PGCAP

7GND AC

HYST OFF

8

AS2316 PDIP

—

16

15

14

13

12

11

10

9

Top view

CC

OFF AC

FAULT

AS2333 SOIC

REF

Description

The AS23xx is a housekeeping circuit for monitoring the outputs of power
supplies. It directly senses all the output rails without the need for external dividers
and detects undervoltage and overvoltage. It also provides an additional
undervoltage comparator which may be configured with any arbitrary hysteresis
to sense a divided down representation of the AC bulk voltage. The housekeeping
section provides all the features necessary to allow external caps to set the
common timing features of PC type power supplies. In addition, negative rails may
be sensed without the necessity of a VEE connection, and negative sensing may
be disabled without affecting operation of the positive sense section. The 2.5 V
series reference is available and can source up to 5 mA. This IC is available in
16 lead packages. Outputs include a POK (Power OK) and a fault signal.

The AS2333 includes sensing for ±12 V, 5 V, and 3.3V. The AS2350 exchanges
a -5 V sense capability for the 3.3 V input. The AS2316 monitors all supply
voltages, but lacks CBD (Crow-Bar Driver).

16

1V

2+12V FAULT

3+5V V

4-5V UVB

5-12V DELAY

6GND POK

7HYST PGCAP

8

16

CBD

15

14

REF

13

12

11

10

9

1V

CC

2+12V FAULT

3+5V V

4+3.3V UVB

5-12V DELAY

6GND POK

7HYST PGCAP

OFF AC

8

16

15

14

13

12

11

10

9

AS2333 PDIP

1V

CC

2+12V FAULT

3+5V V

4+3.3V UVB

5-12V DELAY

6GND POK

7HYST PGCAP

OFF AC

8

CBD

AS2350 SOIC

REF

CBD

15

14

REF

13

12

11

10

9

CC

OFF AC

AS2350 PDIP

1V

2+12V FAULT

3+5V V

4-5V UVB

5-12V DELAY

6GND POK

7HYST PGCAP

8

16

CBD

15

14

REF

13

12

11

10

9

Ordering Information

Package Temperature Range Order Code

16-Pin Plastic SOIC 0 to 105° C AS2316D
16-Pin Plastic SOIC 0 to 105° C AS2333D
16-Pin Plastic SOIC 0 to 105° C AS2350D
16-Pin Plastic DIP 0 to 105° C AS2316N
16-Pin Plastic DIP 0 to 105° C AS2333N
16-Pin Plastic DIP 0 to 105° C AS2350N

© ASTEC Semiconductor

91

AS23xx

Functional Block Diagram

V

REF

nUV

nOV

+12V

UV

OV

t

20 µs delay

Secondary Side Housekeeping Circuit

V

V

nOVLat ch

CC

nRESET

CC

nUV Latch

R
Latch
S

GND

Q

V

CC

FAULT

+5V

+3.3V

- 5V

- 12V

AC

HYST

OFF

UV

OV

UV

UV

Disable

OV

UV

nOV

nUV

nOV

t

20 µs delay

nUV

OV

V

REF

nFAU LT

nRESET

nUVLatch

CBD La tch powers up

in RESET state.

SRQ
Latch

nPOK

V

V

REF

V

REF

Disable

nAC WARNING

nFAU LT

REF

HYST

V

REF

Latch

SRQ

V

CC

CBD

500

V

CC

1µAOV

V

REF

V

CC

1µA

UVB

V

CC

PGCAP

V

CC

POK

V

CC

1µA

DELAY

V

CC

nRESET
nOFF WARNING

V

REF

2.5V

chip b ias

V

REF

ASTEC Semiconductor

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Secondary Side Housekeeping Circuit

AS23xx

Pin Function Description (For AS2333 / AS2350)

Pin Number Function Description

1VCCPower input to the chip.
2 +12 V Input for overvoltage and undervoltage for the +12 V rail.
3 +5 V Input for overvoltage and undervoltage for the +5 V rail.
4 +3.3/–5 V Input for overvoltage and undervoltage for the +3.3V rail or –5 V rail, depending on

product option.

5 –12 V Input for overvoltage and undervoltage for the –12 V rail. This function may

disabled by tying this pin to a positive voltage above 2.4 V.
6 GND Signal ground and silicon substrate.
7 HYST Open collector output of the AC undervoltage comparator. A resistor between this pin

and AC will provide hysteresis to the AC undervoltage sensing.
8 OFF Pulling this pin low will reset the FAULT latch and discharge the start-up timing

capacitors, UVB and PG CAP, allowing normal start-up for the system. Pulling this pin

high will send the FAULT signal high, prompting a system shutdown.
9 AC Non-inverting input to the AC undervoltage sensing comparator. If the AC pin is

less than 2.5 V, POK goes low and UVB cap discharges.

10 PG CAP A cap to ground provides a delay between undervoltage sensing becoming good

and the POK output going high. Cap discharges whenever an output or AC

undervoltage is detected.

11 POK Open collector output of the undervoltage sensing comparators. This pin goes low

upon an undervoltage condition. Except for the delay set by the PG CAP, this pin

always reflects the actual state of the undervoltage sensing.

12 DELAY A cap to ground will delay the FAULT signal when the OFF pin is used to shut down

the system. The POK will signal a power fail warning immediately, but the FAULT

shutdown of the power supply will be delayed.

13 UVB A cap to ground provides start-up blanking of the undervoltage sensing portion of the

FAULT signal. This pin may also be grounded to prevent undervoltage conditions from

triggering the FAULT signal. This pin discharges the cap whenever AC goes low or

FAULT pin goes high.

14 V
15 FAULT Open collector output of the overvoltage and undervoltage comparators.
16 CBD Crow bar drive output of the overvoltage faults only.

ASTEC Semiconductor

REF

2.5 V Voltage reference. This is a series regulator type reference.

93

AS23xx

Secondary Side Housekeeping Circuit

Pin Function Description (For AS2316)

Pin Number Function Description

1VCCPower input to the chip.
2 +12 V Input for overvoltage and undervoltage for the +12 V rail.
3 +5 V Input for overvoltage and undervoltage for the +5 V rail.
4 +3.3 Input for overvoltage and undervoltage for the +3.3V rail.
5 –5 V Input for overvoltage and undervoltage for the –5 V rail.
6 –12 V Input for overvoltage and undervoltage for the –12 V rail. This function may

disabled by tying this pin to a positive voltage above 2.4 V.
7 GND Signal ground and silicon substrate.
8 HYST Open collector output of the AC undervoltage comparator. A resistor between this pin

and AC will provide hysteresis to the AC undervoltage sensing.
9 OFF Pulling this pin low will reset the FAULT latch and discharge the start-up timing

capacitors, UVB and PG CAP, allowing normal start-up for the system. Pulling this pin

high will send the FAULT signal high, prompting a system shutdown.

10 AC Non-inverting input to the AC undervoltage sensing comparator. If the AC pin is

less than 2.5 V, POK goes low and UVB cap discharges.

11 PG CAP A cap to ground provides a delay between undervoltage sensing becoming good

and the POK output going high. Cap discharges whenever an output or AC

undervoltage is detected.

12 POK Open collector output of the undervoltage sensing comparators. This pin goes low

upon an undervoltage condition. Except for the delay set by the PG CAP, this pin

always reflects the actual state of the undervoltage sensing.

13 DELAY A cap to ground will delay the FAULT signal when the OFF pin is used to shut down

the system. The POK will signal a power fail warning immediately, but the FAULT

shutdown of the power supply will be delayed.

14 UVB A cap to ground provides start-up blanking of the undervoltage sensing portion of the

FAULT signal. This pin may also be grounded to prevent undervoltage conditions from

triggering the FAULT signal. This pin discharges the cap whenever AC goes low or

FAULT pin goes high.

15 V
16 FAULT Open collector output of the overvoltage and undervoltage comparators.

REF

2.5 V Voltage reference. This is a series regulator type reference.

ASTEC Semiconductor

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Secondary Side Housekeeping Circuit

AS23xx

Absolute Maximum Ratings

Parameter Symbol Rating Unit

Supply Voltage V
Continuous Power Dissipation at 25° CP
Junction Temperature T
Storage Temperature Range T
Lead Temperature, Soldering 10 Seconds T

Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

CC

D

J

STG

L

20 V

1000 mW

150 °C

–65 to 150 °C

300 °C

Recommended Conditions

Parameter Symbol Rating Unit

Supply Voltage V

CC

5 - 12 V

Typical Thermal Resistance

Package θJA θJC Typical Derating

16L SOIC 65° C/W 45° C/W 10.0 mW/°C
16L PDIP 80° C/W 35° C/W 12.5 mW/°C

Electrical Characteristics

Electrical Characteristics are guaranteed over full junction temperature range (0 to 105° C). Ambient temperature must be derated
based on power dissipation and package thermal characteristics. Unless otherwise specified, the conditions of test are V
+3.3 V = 3.3 V; +5 V = 5V; +12 V = 12 V; –12 V = –12 V; –5 V = –5 V; OFF = low.

Parameter Symbol Test Condition Min Typ Max Unit
Bias

Supply Current I
Min. VCC for operation V

Undervoltage, Overvoltage
+3.3 V (Not available on AS2350)

+3.3 V Undervoltage UV 2.87 2.95 3.03 V
+3.3 V Overvoltage OV 3.76 3.86 3.96 V
+3.3 V Input Current I

+5 V

+5 V Undervoltage UV 4.40 4.50 4.60 V
+5 V Overvoltage OV 5.74 5.89 6.04 V
+5 V Input Current I

+12 V

+12 V Undervoltage UV 10.25 10.50 10.60 V
+12 V Overvoltage OV 14.53 14.90 15.27 V
+12 V Input Current I

CC

CC

no faults 8 12 mA

Min. V

B

B

B

= 2.5 V, no faults 4.2 V

REF

V

=+3.3V, V

+3.3

V

=+5.0V, V

+5

V

=+12.0V 0.8 1.5 mA

+12

=+5.0V -0.1 0 0.1 mA

+5

=+3.3V 1.6 2.5 mA

+3.3

= 12 V;

CC

ASTEC Semiconductor

95

AS23xx

Secondary Side Housekeeping Circuit

Electrical Characteristics (cont’d)

Electrical Characteristics are guaranteed over full junction temperature range (0 to 105° C). Ambient temperature must be derated
based on power dissipation and package thermal characteristics. Unless otherwise specified, the conditions of test are V
+3.3 V = 3.3 V; +5 V = 5V; +12 V = 12 V; –12 V = –12 V; –5 V = –5 V.

Parameter Symbol Test Condition Min Typ Max Unit
–5 V (Not available on AS2333)

–5 V Undervoltage UV –3.80 –4.00 –4.20 V
–5 V Overvoltage OV –6.00 –6.25 –6.55 V
–5 V Input Current I
–5 V Disable Voltage V

V

B

D

=-5.0V –80 –150 µA

-5

Minimum voltage to disable 2.3 2.4 V

–12 V

–12 V Undervoltage UV –9.20 –9.55 –9.80 V
–12 V Overvoltage OV –14.55 –15.04 –15.60 V
–12 V Input Current I
–12 V Disable Voltage V

V

B

D

=-12.0V –100 –200 µA

-12

Minimum voltage to disable 2.0 2.2 V

AC/HYST

AC Undervoltage UV TJ = 25° C 2.460 2.520 2.540 V
AC Input Current I
HYST High State Leakage I
HYST Output Current I
HYST Low Voltage V

B

V

L

OL

OL

= 5 V; AC > 2.5 V 0.01 1 µA

HYST

V

= 0.3 V; AC < 2.5 V 1 3 mA

HYST

I

= 1 mA; AC < 2.5 V 0.3 V

HYST

–0.5 –1 µA

Outputs

POK High State Leakage I
POK Output Current I

OL

V

L

= 12 V; no faults 100 200 µA

POK

V

= 0.4 V; V

POK

= 7 V undervoltage 5 10 mA

CC

condition
FAULT High State Leakage I
FAULT Output Current V

OL

V

L

= 12 V; OFF = High 0.01 1 µA

FAULT

V

= 0.4 V; no faults

FAULT

VCC = 12 V 3 10 mA

VCC = 5 V 1.3 4 mA
CBD (Crow Bar Drive) I

OH

overvoltage condition –25 –35 mA
Minimum Output Current

CBD Output High Voltage V

OH

I

= 0 mA; T = 25 ° C 2.0 2.5 3.0 V

CBD

I

= 0 mA; T = 105 ° C; overvoltage 1.4 3.3 V

CBD

condition
CBD Pulldown Resistance R

OUT

I

= 1 mA; no faults 300 500 1000 1000

CBD

= 12 V;

CC

ASTEC Semiconductor

96

Secondary Side Housekeeping Circuit

AS23xx

Electrical Characteristics (cont’d)

Electrical Characteristics are guaranteed over full junction temperature range (0 to 105° C). Ambient temperature must be derated
based on power dissipation and package thermal characteristics. Unless otherwise specified, the conditions of test are V
+3.3 V = 3.3 V; +5 V = 5V; +12 V = 12 V; –12 V = –12 V; –5 V = –5 V.

Parameter Symbol Test Condition Min Typ Max Unit
Voltage Reference

Output Voltage V
Line Regulation ∆V
Load Regulation ∆V
Temperature Deviation* ∆V

REF

I

= 0 mA, TJ = 25° C 2.488 2.500 2.525 V

REF

VCC = 5 V to 15 V 10 15 mV

REF

I

REF

REF

= 0 V to –5 mA 10 15 mV

REF

0 < TJ < 105° C1015mV

Start-Up Functions

UVB Pull-up Current Source I
UVB Clamp V
UVB Discharge Current I

OH

OH MAXIUVB

UVB

V

= 2.0 V; no faults –0.4 –1 –1.9 µA

UVB

= 10 µA; no faults 2.9 3.1 3.3 V

V

= 2.0 V; FAULT = low; 3 8 mA

UVB

(AC shutdown) AC < 2.5 V
UVB Discharge Current I

OL

V

= 2.0 V; FAULT = high; 2.5 10 mA

UVB

(FAULT shutdown) AC > 2.5 V
UVB Low Output Voltage V
PG CAP Pull-up Current Source I
PG CAP Clamp V
PG CAP Discharge Current I

OL

OH

OH MAXIPGCAP

OL

I

= 100 µA; FAULT = low; AC < 2.5 V 0.2 V

UVB

V

= 2.0 V; no faults –0.5 –1 –1.4 µA

PGCAP

= 10 µA; no faults; AC > 2.5 V 2.9 3.1 3.3 V

V

= 2.0 V; undervoltage 2 6 mA

PGCAP

condition
PG CAP Low Output Voltage V
OFF Input High Voltage V
OFF Input Low Voltage V
OFF Pull-up to V

CC

DELAY Pull-up Current Source I
DELAY Clamp V

OH MAXIDELAY

DELAY Discharge Current I
DELAY Low Output Voltage V

OL

RV

OH

OL

OL

I

= 100µA; undervoltage condition 0.2 V

PGCAP

IH

IL

= 0 V 25 50 100 kΩ

OFF

V

= 0 V; OFF = high –0.5 –1 –2.0 µA

DELAY

2.0 V

0.8 V

= 10 µA; OFF = high 2.9 3.1 3.3 V

V

= 2.0 V; OFF = low 2.5 10 mA

DELAY

I

= 100µA; OFF = low 0.2 V

DELAY

*Temperature deviation is defined as the maximum deviation of the reference over the given temperature range and does not imply an
incremental deviation at any given temperature.

= 12 V;

CC

Typical Performance Curves

Not Available at Time of Publishing

ASTEC Semiconductor

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AS23xx

Secondary Side Housekeeping Circuit

Theory of Operation

the outputs of the PSU. Usually, just one or the

other output is used depending on the PSU’s cost
The AS23xx performs housekeeping functions
for power supplies, especially switching power
supplies for personal computers. The chip re­sides on the secondary side of the power supply
(PSU), and it performs three primary functions:

1) monitors the output voltages and reports
faults

2) sequences the start-up of the PSU

3) sequences the shutdown of the PSU

and system definition. Both methods are in-

tended to protect the customer’s system, and the

customer, as the first priority.

1.2 Undervoltage Faults: POK and FAULT

An undervoltage condition is sometimes not con-

sidered a catastrophic or dangerous condition,

but always one which the customer should be

warned about. The POK signal is a logic line to

the customer’s system that is specified in most

PC type power supply systems. The AS23xx will

pull the POK signal low when a UV fault is

Section 1 - Output Voltages and Faults

detected. A UV fault may or may not require the

system to shut down, so an undervoltage blank-

1.0 Output Voltage Monitoring

The AS23xx monitors the standard voltage out­puts for PC type power supplies. It has inputs for
+12 V, +5 V, +3.3 V, -5 V and -12 V. These inputs

ing pin is provided (UVB). Grounding this pin will

prevent UV faults from propogating to the FAULT

pin. CBD does not react to UV faults.

1.3 Input Undervoltage: AC and HYST

are tied directly to the outputs of the PSU, and
therefore do not require external dividers to set
the error thresholds. These pins are monitored
for both overvoltage (OV) and undervoltage (UV)
conditions. The spec’s for these thresholds are
listed in the data sheet.

In addition, there is a special undervoltage detec-

tion input for sensing the input voltage to the

power supply, designated as the AC pin. This pin

will cause the POK pin to go low if there is

insufficient voltage to run the PSU outputs. Since

power supplies must maintain high voltage isola-

1.1 Overvoltage Faults: FAULT and CBD

An overvoltage condition in a power supply is
considered to be a catastrophic and dangerous
condition which must result in a safe, complete
and near-instantaneous shutdown of the sys­tem. Overvoltages most often result from a
break in the system feedback and control cir­cuitry or from a short between outputs. When the

tion between the primary and secondary sides of

the system, the AC pin is usually tied to a divided

down and filtered representation of the second-

ary side switching waveform. Hysteresis for this

function, to provide immunity from line ripple, is

configured by the PSU designer and is imple-

mented with the HYST pin, which is an open

collector output of the AC comparator.
AS23xx detects an overvoltage, the fault is

latched internally, and the FAULT and CBD pins
go high. The FAULT pin is an open collector
NPN output which is intended to drive an
optocoupler LED for feedback to the primary
side controller of the PSU. The CBD pin is an
NPN Darlington output which is intended to drive
an SCR crowbar circuit which will short circuit

Section 2 - PSU Start-up Sequences

2.0 System Start-up Sequence

When the power supply starts up, the AS23xx

must not erroneously report a FAULT. In addi-

tion, most PC type power supply specifications

ASTEC Semiconductor

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Secondary Side Housekeeping Circuit

AS23xx

require a specific timing sequence for the POK
signal. Some PSU systems also require an
isolated, low voltage, low power remote turn-on
switch, rather than a large line cord switch.

2.1 VREF Enable of Chip Bias

Since the VCC of the AS23xx comes up in a finite
amount of time, and since the VREF of the chip
and the bias for the comparators are not within
specification until approximately 4.2 V of VCC is
available, the comparators for OV and UV and
most other functions are disabled until VREF is
within spec. This prevents the false detection of
a FAULT due to an erroneous VREF. Similarly,
if VREF is too heavily loaded and gets pulled low
out of spec, these functions will also shut off.

2.2 Blanking UV’s During Start-up: UVB

As the power supply outputs come up, the
undervoltage FAULTs must be blanked to allow
the supply to complete its start-up. Putting a
capacitor to ground on the UVB pin will allow the
PSU designer to set a specific period of time
during which undervoltages will not propogate to
the FAULT pin. The UVB pin provides a 1 µA
current source to charge the cap, and once the
UVB pin charges above 2.5 V, the undervoltage
sensing is enabled. UVB does not blank
undervoltages to the POK pin. The UVB pin is
clamped one diode above VREF, or about 3.1 V,
allowing fast discharge of the capacitor when the
system resets.

2.3 POK Bias

V if the VCC of the AS23xx is tied to the 12 V
output or an auxilliary rail.

2.4 POK Start-up Timing: PGCAP

In addition to 2.3 above, most PC power supplies
require the POK pin to remain low until all outputs
have been good for at least 100 ms but not more
than 500 ms. A cap to ground on the PGCAP pin
allows to the PSU designer to set the timing
delay between the PSU outputs becoming good
and the POK pin going high. The PGCAP pin
provides a 1 µA current source to charge the cap,
and when the cap charges above 2.5 V, the POK
pin goes high. When an undervoltage occurs,
the PGCAP pin discharges rapidly and the POK
pin goes low. The POK pin does not respond to
overvoltages.

2.5 Isolated Remote On/Off Switching: OFF
and FAULT

A low voltage, isolated remote on/off switch may
be implemented with the AS23xx OFF pin. If the
chip VCC is run off an auxilliary rail, the FAULT
signal may be used to start and stop the PSU.
When the OFF pin is pulled from high to low or
grounded, the FAULT pin resets to a low state,
which may be used to drive an optocoupler to
enable the primary side PWM controller. Allow­ing the OFF pin to go open circuit or high causes
the POK pin to go low immediately, and the
FAULT pin will go high after a time delay set by
a cap to ground on the DELAY pin. This allows
the customer’s system to receive a POK warning
before the PSU actually shuts down.

The POK pin has some specific requirements
based on industry standard PC power supply
specifications. At start-up, the POK pin must not
rise above 0.4 V. The POK pin is an NPN open
collector whose base is tied to VCC via a simple
resistor. Therefore, once VCC pulls above one
diode or about 0.6 V, the POK pin will go low and
saturate. If the POK pin external pull-up is to the
5 V output, the POK signal will not go above 0.4

Section 3 - PSU Shutdown Sequences

3.0 Shutdown Sequence

For normal shutdowns, the primary requirement
is that the POK signal should go low some
minimum time before the PSU outputs fall out of
spec.

ASTEC Semiconductor

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AS23xx

Secondary Side Housekeeping Circuit

3.1 Delaying Remote OFF: DELAY

In systems which use the OFF and FAULT pins
to provide remote on/off switching, the delay
between the OFF pin going high and the FAULT
signal going high is programmable with a capaci­tor to ground on the DELAY pin as described in

2.5 above. The POK pin, on the other hand will
go high immediately after the OFF pin is open
circuited or pulled high, giving the system warn­ing of the impending shutdown. The DELAY pin
provides a 1 µA current source to charge the
cap, and when the cap charges above 2.5 V, the
FAULT pin will go high.

3.2 AC Warning Prior to Primary Drop-out

In systems where the input line voltage is

switched, the AC pin threshold should be set so

that it causes POK to go low before the primary

bulk voltage reaches drop-out and the primary

PWM shuts off. The output of the AC comparator

also causes the UVB pin to pull low, so that the

undervoltage sensing does not trip the FAULT

latch as the outputs fall below spec. Recall that

the AC pin senses a divided down and filtered

representation of the secondary side switching

waveform, which will provide a proportional rep-

resentation of the primary voltage via the turns

ratio of the transformer.

ASTEC reserves the right to make changes without further notice to any products described herein to improve reliability, function, or
design. ASTEC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does
it convey any license under its patent rights or the rights of others. ASTEC products are not authorized for use as components in life
support devices or systems intended for surgical implant into the body or intended to support or sustain life. Buyer agrees to notify
ASTEC of any such intended end use whereupon ASTEC will determine availability and suitability of its products for the intended use.
ASTEC and the ASTEC logo are trademarks of ASTEC (BSR) PLC.

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ASTEC Semiconductor

100