The AS2214 is a full featured, pulse width modulation
controller. Based on an improved AS3842, the AS2214
provides additional features that reduce component count
and improve specifications in a wide range of power supply
designs. The added functionality includes AC power and
bulk voltage sensing, over-voltage input, as well as the ability
to latch off or bounce through different fault conditions.
The PWM function is controlled by the current sense comparator for normal current mode control and a second
comparator for voltage mode soft start. A buffered RAMP
signal is available for slope compensation without loading
the oscillator. The output stage is a high current totem pole
output that sees only 85 ns delay from the PWM comparator.
The AS2214 requires less than 10µA of startup current. The
undervoltage lockout (UVLO) thresholds are nominally 13.8V
for turn on and 8 V for turn off. A precision 2.5 V bandgap
reference serves as an input for the error amplifier. The
oscillator discharge current is trimmed to provide guaranteed duty cycle clamping.
Pin Configuration
—
Top view
1V
CC
2V
REG
3COMPBOK
4V
FB
5ISNSACP
6SSOV
7RAMPRT/CT
14
OUT
13
GND
12
11
LEN
10
9
8
Ordering Information
Package Temperature Range Order Code
14-Pin Plastic DIP 0 to 105° C AS2214N
ASTEC Semiconductor
83
Page 2
AS2214
Functional Block Diagram
2V 5
AC
DETE C T
V
REG
50µA
3V 95
2V 5
ACP
LEN
BOK
OV
ISNS
(LEN)
6V
(BULK_UV )
(CLR)
(OV )
Primary Side PWM Controller
5V enable
SS LOGIC
(RUN)
UVLO
5V R eg.
V
REG
6µA
V
V
SS
CC
REG
COMP
V
FB
2V 5
RT/CT
ASTEC Semiconductor
2R
1V
R
OSC
x1RAMP
CM PWM
SS P W M
(BLA NK)
(PWM)
V
CC
OUT
GND
84
Page 3
Primary Side PWM Controller
AS2214 Soft Start Logic
AS2214
ENBL
SS
Q
•Q
ENBL
S
PRESET
R
Started
Q
•Q
ENBL
R
PRESET
S
Faulted
Q
•Q
R
PRESET
S
VOV
PWM_Disable
6µA
REG
V
2V7
Latch_bias
REG
V
PresetSRQ•Q
0---00
ENABL
ASTEC Semiconductor
10010
00001
1- 1010
1- 0101
1- 00Q•Q
1- 1100
LEN
OV
Q
•Q
ENBL
REG
V
2V5
1V7
OV
PRESET
S
R
3V9
2V5
BOK
85
Page 4
AS2214
Primary Side PWM Controller
Pin Function Description
Pin NumberFunctionDescription
1VCCPositive supply voltage for the IC.
2V
REG
Output of 5V series regulator.
3COMPThis pin is the error amplifier output. Typically used to provide loop compensation to
maintain VFB at 2.5 V.
4V
FB
Inverting input of the error amplifier. The non-inverting input is a trimmed 2.5 V
bandgap reference.
5ISNSA voltage proportional to inductor current is connected to this pin. The PWM uses this
information to terminate the gate drive of the output.
6SSThis pin provides a 6µA current source to linearly charge an external capacitor. This pin
is compared to the RAMP pin in the soft start comparator, terminating output pulses when
RAMP goes above the SS voltage.
7RAMPThis pin is a level-shifted and buffered oscillator signal used to provide slope compensa-
tion to the current sense signal. The pin also serves as the non-inverting input of the softstart comparator.
8RT/CTOscillator frequency and maximum duty cycle are set by connecting a resistor (R
T
) to
VREG and a capacitor (CT) to ground.
9OVThis pin latches SS low when pulled above 2.5 V. The latch can be reset by pulling
OV above 4 V then back to ground.
10ACPThis pin detects the presence of AC signal and drives LEN high.
11LENThis pin must be high to enable starting. The pin can also clear all latches by going low
then high.
12BOKThis pin monitors the bulk voltage through a resistor divider and, when BOK exceeds
2.5 V, provides a 50µA current source for hysteresis. When BOK drops below 2.5V, SS
is pulled low and the hysteresis current is turned off. Auto-restart after a brown-out is
possible.
13GNDCircuit common ground.
14OUTThis totem pole output is designed to directly drive a power MOSFET switch capable of
sourcing and sinking peak currents up to 1 A.
ASTEC Semiconductor
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Page 5
Primary Side PWM Controller
AS2214
Absolute Maximum Ratings
ParameterSymbolRatingUnit
Reference CurrentI
Output CurrentI
Supply VoltageV
Output VoltageV
Continuous Power Dissipation at 25° CP
Junction TemperatureT
Storage Temperature RangeT
Lead Temperature, Soldering 10 SecondsT
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
REF
OUT
CC
OUT
D
J
STG
L
200mA
1A
20V
20V
500mW
150°C
–65 to 150°C
300°C
Recommended Conditions
Parameter Symbol Rating Unit
Supply VoltageV
OscillatorF
CC
OSC
10 - 15V
50 - 250kHz
Typical Thermal Resistance
Package θJA θJC Typical Derating
14L PDIP 85° C/W 40° C/W 11.7 mW/°C
Electrical Characteristics
Electrical Characteristics are guaranteed over full junction temperature range (0 to 105° C). Ambient temperature must be derated
based on power dissipation and package thermal characteristics. Unless otherwise specified, the conditions of test are V
BOK = 3 V; OV = 0V; RT = 680 Ω; CT = 10 nF. To override UVLO, V
VFB = 2.7 V; V
VFB = 2.3 V; V
VFB = 2.3 V; RL = 15 Ω to GND55.5V
VFB = 2.7 V; RL = 15 Ω to V
≤ 4 V6590dB
COMP
COMP
COMP
should be raised above 18 V prior to test.
CC
-0.1-1µA
1mA/mV
= 1.1 V26mA
= 5 V0.51.0mA
REG
0.71.1V
= 15 V;
CC
ASTEC Semiconductor
87
Page 6
AS2214
Primary Side PWM Controller
Electrical Characteristics (cont’d)
Electrical Characteristics are guaranteed over full junction temperature range (0 to 105° C). Ambient temperature must be derated
based on power dissipation and package thermal characteristics. Unless otherwise specified, the conditions of test are V
BOK = 3 V; OV = 0V; RT = 680 Ω; CT = 10 nF. To override UVLO, V
should be raised above 18 V prior to test.
CC
ParameterSymbolTest ConditionMinTypMaxUnit
5 V Regulator
Output VoltageV
REG
Line Regulation PSRR12 ≤ V
Load Regulation1≤ I
Temperature StabilityTC
REG
I
= 1 mA, TJ= 25° C4.905.005.10V
REG
≤ 18 V515mV
CC
≤ 20mA515mV
REG
0.20.4mV/°C
Total Output VariationLine, Load,Temperature4.855.15V
Long-Term StabilityOver 1,000 hrs at 25°C525mV
Output Noise Voltage V
Maximum Source Current I
NOISE
MAX
10 ≤ f ≤ 100kHz, TJ = 25°C50µV
V
= 4.8 V30120180mA
REG
Oscillator
Initial AccuracyF
OSC
Voltage Stability12 ≤ V
Temperature StabilityTC
AmplitudeV
SS Charge CurrentI
SS Discharge CurrentI
SS Lower ClampV
RAMP High LevelV
RAMP Low LevelV
SS
Dsc
SS Low
RAMPHTJ
RAMPLTJ
SSV
V
≤ V
SS
= 1 V, V
SS
RAMP
> 2.5V28mA
OV
-4-6-10µA
0.6V
=25°C2.15V
=25°C0.6V
RAMP Levels TCNote: RAMP wavefrom is the same as-2mV/°C
the RT/CT wavefrom, but level shifted
down one diode drop
RAMP Sink CurrentI
RAMP Source CurrentI
Propagation Delay to Outputt
RAMPL
RAMPH
PB
TJ =25°C–0.1–0.2mA
TJ =25°C1mA
85150ns
= 15 V;
CC
ASTEC Semiconductor
88
Page 7
Primary Side PWM Controller
AS2214
Electrical Characteristics (cont’d)
Electrical Characteristics are guaranteed over full junction temperature range (0 to 105° C). Ambient temperature must be derated
based on power dissipation and package thermal characteristics. Unless otherwise specified, the conditions of test are V
BOK = 3 V; OV = 0V; RT = 680 Ω; CT = 10 nF. To override UVLO, V
see characteristic curve
ACP VoltageV
ACP VoltageV
LEN Charge CurrentI
LEN Charge CurrentI
Minimum Voltage for LENV
ACP
ACP
LEN
LEN
LEN MIN
I
= 10 µA1.3V
ACP
I
= -10 µA-1.2V
ACP
I
= 10 µA; V
ACP
I
= -10 µA; V
ACP
= 0 V-30-45-65µA
LEN
= 0 V-30-50-65µA
LEN
3.64.5V
Functionality
LEN Logic Reset VoltageV
LEN Regeneration CurrentI
LEN ClampV
LEN Bias CurrentI
BIAS LENVLEN
LEN
LENrgn
LEN
This level reflects one diode drop of3.0V
hysteresis from V
LEN min
-10µA
I
= 5 µA5.25.96.6V
ACP
= 5 V, I
= 0 µA8µA
ACP
* For LEN input current over full
range, see characteristic curve.
Current Sense Comparator
Transfer GainAV
I
Level ShiftV
SNS
Maximum Input SignalV
Power Supply Rejection RatioPSRR12 ≤ V
Input Bias CurrentI
Propagation Delay to Outputt
BIAS
PB
ISNS
LS
-0.2 ≤ V
V
ISNS
COMP
≤ 0.8 V2.853.003.15V/V
ISNS
= 0 V1.50V
=+5 V1.001.081.20V
≤ 18 V70dB
CC
-1-10µA
85150ns
= 15 V;
CC
ASTEC Semiconductor
89
Page 8
AS2214
Primary Side PWM Controller
Electrical Characteristics (cont’d)
Electrical Characteristics are guaranteed over full junction temperature range (0 to 105° C). Ambient temperature must be derated
based on power dissipation and package thermal characteristics. Unless otherwise specified, the conditions of test are V
BOK = 3 V; OV = 0V; RT = 680 Ω; CT = 10 nF. To override UVLO, V
should be raised above 18 V prior to test.
CC
ParameterSymbolTest ConditionMinTypMaxUnit
Under Voltage Lockout
Startup ThresholdV
Minimum Operating VoltageV
(ON)12.514.015.8V
CC
(OFF)7.38.08.5V
CC
after Trun-on
Startup CurrentI
Startup CurrentI
Operating Supply CurrentI
Maximum Operating SupplyV
CC
CC
CC
CC Max
VCC = 12 V; V
VCC = 12V; I
ACP
= V
ACP
= 0 V210µA
LEN
= 5 µA225300µA
1220mA
18V
Voltage
Output Impedance to GND inZ
OUT
VCC = 6 V22.0kΩ
UVLO State
Output
Output Low LevelV
Output Low LevelV
Output High LevelV
Output High LevelV
Rise Timet
Fall Timet
Maximum Duty CycleD
Minimum Duty CycleD
MAX
MIN
I
OL
OL
OH
OH
R
F
= 20 mA0.10.4V
SINK
I
= 150 mA1.52.2V
SINK
I
= 20 mA1313.5V
SOURCE
I
= 150 mA1213V
SOURCE
CL = 1 nF50150ns
CL = 1 nF50150ns
9497100%
0%
= 15 V;
CC
ASTEC reserves the right to make changes without further notice to any products described herein to improve reliability, function, or
design. ASTEC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does
it convey any license under its patent rights or the rights of others. ASTEC products are not authorized for use as components in life
support devices or systems intended for surgical implant into the body or intended to support or sustain life. Buyer agrees to notify
ASTEC of any such intended end use whereupon ASTEC will determine availability and suitability of its products for the intended use.
ASTEC and the ASTEC logo are trademarks of ASTEC (BSR) PLC.