Datasheet APU0071-002WE-TY, APU0071-001WE-TY Datasheet (ANPEC)

80 Segment / 16 Common Controller

for Dot Matrix LCD

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0071

www.anpec.com.tw1

ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.

FEATURES DOT MATRIX LCD CONTROL-

LER & DRIVER

APU0071 is a dot matrix LCD driver & controller
LSI that is fabricated by low power CMOS
technology. It is capable of displaying 1-line 16

characters or 2 line 16 characters with 5 × 8 dots
format.

FUNCTIONS

Character type dot matrix LCD driver & controller.

• Easy interface with 4-bit or 8-bit MPU.

• Internal driver : 16 common and 80 segment

signal output.

• Display character pattern : 5 × 7 dots format

(224 kinds)

• Direct programming of the special character

patterns by character Generator RAM.

• Mask open for programming customer charac-

ter patterns

• V arious instructions function.

• Automatic power on reset.

ORDERING INFORMATION

Internal Memory

- Character Generator ROM (CGROM) : 7840bits
(224 characters × 5 × 7dot)

- Character Generator RAM (CGRAM) : 160 bit (4­characters × 5 × 8 dot)

- Display Data RAM (DDRAM) : 256bits (32
characters × 8bits)

• Low power operation

- Power supply voltage range : 2.7 ~ 5.5V (VDD)

- LCD drive voltage range : 3.0 ~ 7.0 (VDD-V5)

• CMOS process

• Duty cycle : 1/16

• Built-in oscillator

• Low power consumption

• Internal divide resistor for LCD driving voltage

• Available for COG

APU0071

ROM Code

Package Type

Handling Code

ROM Code
001 : Standard
002 : Customer

Package Type
W : C O G

Handling Code
TY : Tray

E

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0071

www.anpec.com.tw2

BLOCK DIAGRAM

Oscillator

Power On Reset

(POR)

RESETB

16-bit

shift

register

Common

driver

Input

buffer

Timing generator

EXTCLK

TEST

EXT_INT

C1 ~ C16

Segment

driver

80-bit

latch

circuit

80-bit

shift

register

(Bidir.)

Display

data

RAM

(DDRAM)

32*8 bits

Instruction

Decoder

Address

counter

Instruction

register

(IR)

8

Data

register

(IR)

8

8

DB0

~DB7

RS
RW
E

Character
generator

RAM

(CGRAM)

160 bits

Character
generator

RAM

(CGROM)

7840 bits

Cursor

blink

control

circuit

Parallel to Serial converter

V

DD

V

1

V

2

V

3

V

4

V

5

8

8

V

DD

GND
(V

SS)

S1 ~ S80

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0071

www.anpec.com.tw3

PAD DIAGRAM

APU0071

PAD Diagram

AP

93
94
95
96
97
98
99

89
90
91
92

56

55

54

53

52

51

50

59

58

57

49

47

46

45

44

71

70

69

68

67

66

65

74

73

72

64

63

62

61

60

86

85

84

83

82

81

80

88

87

79

78

77

76

75

111
112
113
114

104
105
106
107
108
109
110

100
101
102
103

115
116
117
118

48

39
40
41
42
43

120

121

122

123

124

125

126

119

31

38373635343332

PAD NO. : 1 ~ 30

PAD PITCH :

≥

120

AL PAD SIZE : 96

×

96

AL PAD WINDOW: 70

×

70

AU PAD SIZE : 84

×

84

UNIT :

µ

m

C8C7C6C5C4C3C2

C1

7
6
5
4

9
8

26

27

28

24

25

29

30

18

19

20

21

17

22

23

11

12

13

10

14

15

16

1

3
2

C16

C15

C14

C13

C12

C11

C10

C9

S22

S21

S30

S29

S28

S27

S26

S25

S24

S23

S40

S39

S38

S37

S36

S35

S34

S33

S32

S31

S50

S49

S48

S47

S46

S45

S44

S43

S42

S41

S60

S59

S58

S57

S56

S55

S54

S53

S52

S51

S20

S19

S18

S17

S16

S15

S14

S13

S12

S11

S10

S9

S8

S7

S6

S75

S74

S73

S72

S71

S70

S69

S68

S67

S66

S65

S64

S63

S62

S61

S80

S79

S78

S77

S76

S5

S4

S3

S2

S1

V

SS

DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
E
R_NW
RS

EXTCLK

EXT_INT

OSC_TS
POR_TS

EXT_RST

M_TS

CLK1_TS

Dummy

Chip size

¡G

6500 x 1140

( 0 , 0 )

V

SS

V

SS

V

5

V

5

V

5

V

3

V

2

V

DD

V

DD

V

DD

PAD NO. : 31 ~ 126

PAD PITCH : 80

AL PAD SIZE : 62

×

102

AL PAD WINDOW: 36

×

76

AU PAD SIZE : 50

×

90

UNIT :

µ

m

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0071

www.anpec.com.tw4

PAD LOCATION

Pad Name X Y Pad Name X Y Pad Name X Y

1 POR_TS -2650.9 -429.84 43 S5 2843.35 404.67 85 S47 -516.65 404.67
2 OSC_TS -2530.9 -429.84 44 S6 2763.35 404.67 86 S48 -596.65 404.67
3 EXTCLK -2410.9 -429.84 45 S7 2683.35 404.67 87 S49 -676.65 404.67
4 EXT_INT -2290.9 -429.84 46 S8 2603.35 404.67 88 S50 -756.65 404.67
5VSS-2158.65 -480.84 47 S9 2523.35 404.67 89 S51 -836.65 404.67
6VSS-2038.65 -480.84 48 S10 2443.35 404.67 90 S52 -916.65 404.67
7VSS-1918.65 -480.84 49 S11 2363.35 404.67 91 S53 -996.65 404.67
8V5-1728.70 -480.84 50 S12 2283.35 404.67 92 S54 -1076.65 404.67
9V5-1608.70 -480.84 51 S13 2203.35 404.67 93 S55 -1156.65 404.67

10 V

5

-1488.70 -480.84 52 S14 2123.35 404.67 94 S56 -1236.65 404.67

11 V

3

-1305.75 -480.84 53 S15 2043.35 404.67 95 S57 -1316.65 404.67
12 DUMMY -1119.15 -480.84 54 S16 1963.35 404.67 96 S58 -1396.65 404.67
13 V

2

-940.20 -480.84 55 S17 1883.35 404.67 97 S59 -1476.65 404.67

14 V

DD

-749.60 -480.84 56 S18 1803.35 404.67 98 S60 -1556.65 404.67

15 V

DD

-629.60 -480.84 57 S19 1723.35 404.67 99 S61 -1636.65 404.67

16 V

DD

-509.60 -480.84 58 S20 1643.35 404.67 100 S62 -1716.65 404.67
17 M_TS -333.50 -480.84 59 S21 1563.35 404.67 101 S63 -1796.65 404.67
18 CLK1_TS -102.10 -480.84 60 S22 1483.35 404.67 102 S64 -1876.65 404.67
19 EXT_RST 131.70 -480.84 61 S23 1403.35 404.67 103 S65 -1956.65 404.67
20 RS 358.80 -480.84 62 S24 1323.35 404.67 104 S66 -2036.65 404.67
21 R_NW 594.20 -480.84 63 S25 1243.35 404.67 105 S67 -2116.65 404.67
22 E 821.30 -480.84 64 S26 1163.35 404.67 106 S68 -2196.65 404.67
23 DB0 1054.80 -480.84 65 S27 1083.35 404.67 107 S69 -2276.65 404.67
24 DB1 1286.80 -480.84 66 S28 1003.35 404.67 108 S70 -2356.65 404.67
25 DB2 1518.40 -480.84 67 S29 923.35 404.67 109 S71 -2436.65 404.67
26 DB3 1750.40 -480.84 68 S30 843.35 404.67 110 S72 -2516.65 404.67
27 DB4 1982.00 -480.84 69 S31 763.35 404.67 111 S73 -2596.65 404.67
28 DB5 2214.00 -480.84 70 S32 683.35 404.67 112 S74 -2676.65 404.67
29 DB6 2445.60 -480.84 71 S33 603.35 404.67 113 S75 -2756.65 404.67
30 DB7 2631.91 -429.84 72 S34 523.35 404.67 114 S76 -2836.65 404.67
31 C1 3149.01 -475.85 73 S35 443.35 404.67 115 S77 -2916.65 404.67
32 C2 3149.01 -395.85 74 S36 363.35 404.67 116 S78 -2996.65 404.67
33 C3 3149.01 -315.85 75 S37 283.35 404.67 117 S79 -3076.65 404.67
34 C4 3149.01 -235.85 76 S38 203.35 404.67 118 S80 -3156.65 404.67
35 C5 3149.01 -155.85 77 S39 123.35 404.67 119 C16 -3137.66 95.82
36 C6 3149.01 -75.85 78 S40 43.35 404.67 120 C15 -3137.66 15.82
37 C7 3149.01 4.15.00 79 S41 -36.65 404.67 121 C14 -3137.66 -64.18
38 C8 3149.01 84.15 80 S42 -116.65 404.67 122 C13 -3137.66 -144.18
39 S1 3163.35 404.67 81 S43 -196.65 404.67 123 C12 -3137.66 -224.18
40 S2 3083.35 404.67 82 S44 -276.65 404.67 124 C11 -3137.66 -304.18
41 S3 3003.35 404.67 83 S45 -356.65 404.67 125 C10 -3137.66 -384.18
42 S4 2923.35 404.67 84 S46 -436.65 404.67 126 C9 -3137.66 -464.18

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0071

www.anpec.com.tw5

PIN DESCRIPTION

PIN

Inp u t /

Output

Name Description Interface

V

DD

For logical circuit (+3v,+5v)

VSS (GND)

0V (GND)

V2,V3,V

5

P

Power supply & LCD
Bias pin

Bias voltage level for LCD driving

Power
Supply

S1 ~ S80 Output Segment output Segment signal output for LCD driving LCD
C1 ~ C16 Output Common output Comm on signal output for LCD driving LCD

EXTCLK Input External clock Input

When using external clock, used as clock input pin.
When using internal oscillator, connect to V

DD

or VSS.

External

clock

EXT_INT Input

Ex ternal / Internal
oscillator clock select

When EX T_INT = “High”, external clock is used.
Wh en “L o w”, ins tru c tio n o sc illa to r is us e d .

MPU

RS Inpu t Re g is ter select

Used as register selection input.
When RS = “High”, data register is selected.
When RS = “Low”, instruction register is selected.

R_NW Input Read / Write

Used as read / write selection input.
When R W = “High”, read operation.
When RW = “Low”, write operation.

E Input Read / Write enable Used as read / write enable signal.
DB0 ~ DB3

When 8-bit bus mode, used as low order bi-directional
data bus.
During 4-bit bus mode open these pins.

DB4 ~ DB7

Inpu t /

Output

Da ta Bus 0 ~ 7

When 8-bit bus mode, used as high order bi-directional
data bus. In case of 4-bit bus mode, used as both high
and low order.
DB7 is used for Busy Flag output during read
instruction operation.

EXT_RST Input Reset

If it is necessary to initialize the system by hardware,
force “Low”, level signal to this terminal about 1.2 ms.

MPU

OSC_TS Output T est Pin Internal oscillator test pin. Open this pin.
POR_TS Output T est Pin Internal test pin. Open this pin.
M_TS Output T est Pin Internal test pin. Open this pin.
CLK1_TS Output T est Pin Internal test pin. Open this pin.

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0071

www.anpec.com.tw6

FUNCTION DESCRIPTION

1. SYSTEM INTERFACE

This chip consists of two kinds of interface type with MPU : 4-bit bus and 8-bit bus.
4-bit bus and 8-bit bus is selected by DL bit of function set in the instruction register.

During read or write operation, two 8-bit registers are used. One is the data register (DR); the other is the
instruction register (IR) .

The data register (DR) is used as a temporary data storage place for being written into or read from
DDRAM / CGRAM, target RAM is selected by RAM address setting instruction. Each internal operation,
reading from or writing into RAM, is done automatically.
Thus, after MPU reads DR data, the data in the next DDRAM / CGRAM address is transferred into DR
automatically. Also after MPU writes data to DR, the data in DR is transferred into DDRAM / CGRAM
automatically.

The Instruction register (IR) is used only to store instruction code transferred from MPU.
MPU cannot read data from instruction register.
Table 1. Various kinds of operation according to RS and R / W bits.

RS R / L Operation

0 0 Instruction Write operation (MPU W rites Instruction into IR)
0 1 Read Bus y flag (DB7) a nd address counter (DB 0 ~ DB6)
1 0 Data Write operation (MPU Writes data into DR)
1 1 Data Read op eration (MP U Writes data into DR)

The register selection depends on RS input pin setting in both 4-bit bus mode.

2. BUSY FLAG (BF)

BF = “High” it indicates that the internal operation is being processed. So during this time the next instruc­tion cannot be accepted. BF can be read, when RS = Low and R / W = High (Read instruction Operation) ,
through DB7 port.
Before exciting the next instruction, be sure that BF is not High.

3. ADDRESS COUNTER (AC)

Address Counter (AC) stores the address of DDRAM / CGRAM that are transferred from IR.
After writing into (reading from) DDRAM / CGRAM data, AC is increased (decreased) by 1 automatically.
When RS = “Low”, and R / W = “High”, AC value can be read through DB0 ~ DB6 ports.

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0071

www.anpec.com.tw7

4. DISPLAY DATA RAM (DDRAM)

DDRAM stores 8bits character code in CGROM / CGRAM and its maximum number is 32 (32 Characters)
. DDRAM address is set by the address counter (AC) as a hexadecimal number.

AC6 AC5 AC4 AC3 AC2 AC1 AC0

MSB LSB

HEX HEX

4-1. DDRAM addressing mode 0 (A = 0) (1 Line)

In this addressing mode, the address range of DDRAM is 00H ~ 0FH.

01 02 03 04 05 06 07 0A 0B 0C 0 D 0E0F

12345678910111213141516

08 0900

01 02 03 04 05 06 07 08 0A 0B 0C 0D 0E 0F

12345678910111213141516

09 00

00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

COM1~COM8

COM9~COM16

COM1~COM8

COM9~COM16

COM1~COM8

COM9~COM16

DDRAM Address

Display Position

After shift left

After shift right

4-2. DDRAM addressing mode 1 (A = 1) (2 Line)

In this addressing mode, the address range of DDRAM is 00H ~ 0FH and 40H ~ 4FH.

After shift right

41 42 43 44 45 46 47 48 49 4A 4B 4 C 4D 4E

12345678910111213141516

COM9

COM16

40

00 01 02 03 04 05 06 07 08 09 0A 0 B 0C 0D 0E 0F

12345678910111213141516

COM1
COM8

40 41 42 43 44 45 46 47 48 49 4A 4 B 4C 4D 4E 4F

12345678910111213141516

COM9

COM16

DDRAM Address

Display Position

DDRAM Address

Display Position

After shift left

01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0 E 0F

12345678910111213141516

COM1
COM8

40

41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F

12345678910111213141516

COM9

COM16

00

01 02 03 04 05 06 07 08 09 0A 0B 0 C 0D 0E

12345678910111213141516

COM1
COM8

4F

00

0F

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0071

www.anpec.com.tw8

5. CHARACTER GENERATOR RAM (CGRAM)

CGRAM is used for user defined character pattern. The format of the character pattern is 5 × 7 dots
except for the cursor position and has a maximum of 4 characters. To use the character pattern in
CGRAM write the character code into DDRAM as shown in table 2.
Table 2. Relationship between character Code (DDRAM) and Character Pattern (CGRAM)

Character Code ( DDRAM data )

765432104321043210

CGRAM address CGRAM data

0000

∗∗

000000001110

000011

0 0 01

00010

10001

00011

11111

00100

1 0 0 0 1

00101

10001

00110

10001

00111

00000

Pattern

Number

Pattern 1

cursor position

.................

0000

∗∗

0011

11
11
11
11
11
11
11

000
001
010
011
100
101
110
111

1
1
1
1
1
1
1
0

1
0

1
00

0

1

1

1

1

1

0

1 1

00
0
0
0
0

1

0

0

0

0

0

1
0

0
0
0
0

Pattern 4

Note : The asterisk means "don't care".

.................

.................

.................

.................

cursor position

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0071

www.anpec.com.tw9

6. CHARACTER GENERATOR ROM (CGROM)

CGROM generates 5 × 5 × 7 character pattern from character generate code in DDRAM. CGROM has 5 ×
7-dot 224-character pattern excluding cursor position. The relationship between character code and
character pattern can be referred to Table 5.

7. TIMING GENERATION CIRCUIT

Timing generation circuit generates clock signals for the internal operations.

8. LCD DRIVER CIRCUIT

LCD driver circuit has 16 common and 80 segment output signals for LCD driving.
Data from CGRAM / CGROM is transferred to 80-bit segment shift register in a serially, which is then it is
stored to 80-bit segment output latch. When each COM is selected by a 16-bit common register, the
segment data also outputs through segment driver from 40-bit segment output latch.

9. CURSOR / BLINK CONTROL CIRCUIT

It controls cursor / blink ON / OFF at the cursor position.

INSTRUCTION DESCRIPTION

1. OUTLINE

To overcome the speed difference between the internal clock of APU0071 and the MPU clock, the
APU0071 per-forms an internal operation by storing control information to IR or DR. The internal operation
is determined according to the signal from MPU, composed of read / write and data bytes.
Instruction can be divided into four types :

1-1. APU0071 function set instructions (set display methods, set data length, etc.)
1-2. Address set instructions to internal RAM
1-3. Data transfer instructions with internal RAM
1-4. Others
The address of internal RAM is automatically increased or increased by 1.

Note : During an internal operation, the Busy Flag (DB7) is High. Busy Flag check must precede the next

instruction.

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0071

www.anpec.com.tw10

Table 3. Instruction Table

Instruction Code

Instruction

RS R / W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Description

Execution

time

(f

OSC

=270

kHz)

Clear Display 0 0 00000001

Write “20H” to DDRAM and
set DDRAM address to
“00H” from AC .

629µs

Return Home 0 0 0000001

∗

Set DDRAM address to
“00H” from AC and return
cursor to its original
position if shifted. The
contents of DDRAM are not
changed.

629µs

Entry Mode Set 0 0 000001I / DS

Assign cursor moving
direction and enable entire
display shift.

37µs

Display ON / OFF
Control

0 0 00001DCB

All display (D) , cursor (C) ,
and blinking of cursor
position character on / off
control bit (B) .

37µs

Cursor or Display
Shift

0 0 0001

S /

C

R / L

∗∗

Cursor and Display shift
and their direction control
without changing DDRAM
data.

37µs

Function Set 0 0 0 0 1 DL A

∗

M1 M0

Set interface da ta length
(DL) , DDRAM addressing
mode (A) and COM / SEG
output pattern (M0, M1) .

37µs

Set CG RAM A ddress 0 0 0 1

∗

AC4 AC3 AC2 AC1 AC0

Set CGRAM address in
address counter.

37µs

S e t D D R A M A d dr e s s 0 0 1 AC6 AC5 AC4 AC3 AC2 AC1 AC0

Set DDRAM address in
address counter.

37µs

DDRAM

AC6 AC5 AC4 AC3 AC2 AC1 AC0

Read Busty
Flag and
Address

CGRAM

01BF

∗∗

AC4 AC3 AC2 AC1 AC0

Whether in internal
operation or not can be
known by reading BF. The
contents of address
counter can also be read.

0µs

DDRAM

D7 D6 D5 D4 D3 D2 D1 D0

Write Data
to RAM

CGRAM

10

∗∗∗

D4 D3 D2 D1 D0

Write data into internal
RAM (DDRAM / CGRAM) .

43µs

DDRAM

D7 D6 D5 D4 D3 D2 D1 D0

Read Data
from R A M

CGRAM

11

∗∗∗

D4 D3 D2 D1 D0

Read data from internal
RAM (DDRAM / CGRAM) .

43µs

I / D = 1 : Increment,
S = 1 : Shift enable,
S / C = 1 : Display shift,
R / L = 1 : Shift right,
D / L = 1 : 8 bit interface,
A = 0 : DDRAM addressing mode 0,
M0 = 0 : Bottom view,
M1 = 0 : No Rotate,
BF = 1 : System is in operation

I / D = 0 : Decrement
S = 0 : Shift disable
S / C = 0 : Move cursor
R / L = 0 : Shift left
D / L = 0 : 4-bit interface
A = 1 : DDRAM addressing mode1
M0 = 1 : Top view
M1 = 1 : Rotate
BF = 0 : System is ready

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0071

www.anpec.com.tw11

1-1. Clear Display

Clear all the display data by writing “20H” (space code of CGROM) to all DDRAM address, and set
DDRAM address to “00H” into AC (Address Counter) . For this instruction, the CGROM address ”20H” has
to be set to space code. Shifting of the display position returns it to the original position. Namely, when
display data is disappeared and cursor or blinking is displayed, bring the cursor to the left edge on first line
of the display. It makes entry mode to increment (I / D = 1)

1-2. Return Home

Set DDRAM address to ”00H” into the address counter. Shifting of the display position returns it to the
original position. When cursor or blinking is displayed, bring the cursor to the left edge on first line of the
display. The data in DDRAM does not change.

1-3. Entry Mode Set

RS R/ W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0000000001

Code

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

000000001

∗

Code

"

∗

" : Don't care

RS R/ W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

00000001I / DS

Code

Set the moving direction of cursor and display.
I / D : Increment / decrement of DDRAM / CGRAM address (cursor or blink)

When I / D = “High”, cursor / blink moves to right and DDRAM address is increased by 1.

When I / D = “Low”, cursor / blink moves to left and DDRAM address is decreased by 1.
S : Shift of entire display
When DDRAM read (CGRAM read / write) operation or S = “Low”, entire display is not shifting.

If S = “High”, and DDRAM write operation, entire display is sifted according to I / D value (I / D = “1” :
shift left, I / D = “0” : shift right) .

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0071

www.anpec.com.tw12

1-4. Display ON / OFF Control

Control display / cursor / blink ON / OFF 1 bit register.
D : Display ON / OFF control bit
When D = “High”, entire display is turned on.

When D = “Low”, entire display is turned off, but display data is remains in DDRAM.
C : Cursor ON / OFF control bit
When C = “High”, cursor is turned on.

When C = “Low”, cursor is disappeared in current display, but I / D register preserves its data.
B : Cursor Blink ON / OFF control bit
When B = “High”, cursor blink is on, performs alternately between all high data (black pattern) and
display character at the cursor position.
When B = “Low”, blink is off.

1-5. Cursor or Display Shift

RS R/ W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0000001DCB

Code

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 1 S / C R / L

∗∗

Code

"

∗

" : Don't care

Without writing or reading of display data, shift right / left the cursor position or display.
This instruction is used to correct or search display data.
During 2-line mode display, cursor moves to the 2nd line after 16th digit of 1st line.
Note that display shift is performed simultaneously in all the line.
When displayed data is shifted repeatedly, each line is shifted individually.
When display shift is performed, the contents of address counter are not changed.
Table 4. Shift patterns according to S / C and R / L bits

0

S / C R / L

10
0

0

1
11

Operation

Shift cursor to the left, AC is decreased by 1

Shift all the display to the left, cursor moves according to the display

Shift cursor to the right, AC is increased by 1

Shift all the display to the right, cursor moves according to the display

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0071

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1-6. Function Set

DL : Interface data length control bit
When DL = “High”, 8-bit bus mode with MPU.
When DL = “Low”, 4-bit bus mode with MPU. Thus, DL is a signal to select 8-bit or 4-bit bus mode.
In 4-bit bus mode, the 4-bit data is transferred twice.
A : Set the display data-addressing mode
When A = “Low”, DDRAM addressing mode 0. (1 Line)
When A = “High”, DDRAM addressing mode 1. (2 Line)
M0 : Set COM / SEG output rotation
When M0 = “Low”, Bottom view.
When M0 = “High”, Top view.
M1 : Set display line and character mode
When M1 = “Low”, LCD module Rotation mode A.
When M1 = “High”, LCD module Rotation mode B.
(Refer to Application information)

1-7. Set CGRAM Address

Set CGRAM address to AC.
This instruction allows the MPU to access CGRAM data for user defined character pattern.
Available CGRAM Address is lower 5 bits (DB4 ~ DB0) .

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

00001DLA M1M0

Code

"

∗

" : Don't care

∗

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 1 AC4 AC3 AC1 AC0

Code

"

∗

" : Don't care

AC2

∗

MSB LSB

Copyright  ANPEC Electronics Corp.
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1-8. Set DDRAM Address

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 AC6 AC5 AC4 AC3 AC1 AC0

Code AC2

RS R/W DB7 DB6 DB5

DB4 DB3 DB2 DB1 DB0

0 0 BF AC4 AC3 AC1 AC0

Code

AC2

∗

MSB LSB

RS R/W DB7 DB6 DB5

DB4 DB3 DB2 DB1 DB0

0 0 BF AC6

AC5

AC4 AC3 AC1 AC0

Code

AC2

MSB

LSB

DDRAM

CGRAM

∗

" ∗ " : Don't care

Set DDRAM address to AC. This instruction allows the MPU to access DDRAM data.
When DDRAM addressing mode 1 (A = 0) , DDRAM address is from “00H” to “0FH”.
In DDRAM addressing mode 2 (A = 1) , DDRAM address range of the 1st 16 character is “00H” to “0FH”,
and DDRAM address range of the 2nd 16 character is “40H” to “4FH”.

1-9. Read Busy Flag & Address

This instruction shows whether APU0071 is in internal operation or not. If the resultant BF is High, The
internal operation is in progress and should wait until BF to be Low, which by then the next instruction can
be performed. In the instruction you can read also the value of address counter.

1-10. Write data to RAM

Write binary 8/5 bit data to DDRAM / CGRAM. The selection of RAM from DDRAM / CGRAM is set by the
previous address set instruction (DDRAM address set, CGRAM address set) . After writing operation, the
address is automatically increased / decreased by 1, according to the entry mode.

RS R/W DB7 DB6 DB5

DB4 DB3 DB2 DB1 DB0

1 0 D4 D3 D1 D0

Code

D2

∗

MSB LSB

RS R/W DB7 DB6 DB5

DB4 DB3 DB2 DB1 DB0

1 0 D7 D6

D5

D4 D3 D1 D0

Code

D2

MSB

LSB

DDRAM

CGRAM

∗

∗

" ∗ " : Don't care

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0071

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1-11. Read data from RAM

Read BINARY 8 / 5 bit from DDRAM / CGRAM. The selection of RAM is set by the previous address set
instruction. If the address set instruction of RAM is not performed before this instruction, data that was
read first becomes invalid, as the direction of AC is not determined. If RAM data is read several times
without RAM address set instruction before read operation, the correct RAM data can be detained from
the second, but the first data would be incorrect, as there is no time margin to transfer the RAM data. In
case of DDRAM reading operation, the cursor shift instruction plays the same role as DDRAM address set
instruction also transfers RAM data to output data register. After read operation address counter is auto­matically increased / decreased by 1 according to the entry mode. After CGRAM read operation is, the
display shift may not be executed correctly.
∗ In case of RAM write operation, AC is increased / decreased by 1 like read operation (after this
operation) . In this time, AC indicates the next address position, but only the previous data can be read by
read instruction.

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1 0 D4 D3 D1 D0

Code D2

∗

MSB LSB

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1 0 D7 D6

D5

D4 D3 D1 D0

Code D2

MSB

LSB

DDRAM

CGRAM

∗

∗

" ∗ " : Don't care

2. INTERFACE with MPU

2-1. Interface with 8-bit MPU

With 8-bit interfacing data length transfer is performed at a time through 8 ports, from DB0 to DB7.
Example of timing sequence is shown below.

Copyright  ANPEC Electronics Corp.
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Fig 1. Example of 8-bit Bus Mode Timing Diagram

RS

R / W

E

Internal
signal

Internal operation

DB7 DATA

Busy

Busy

No

Busy

DATA

INSTRUCTION

Busy Flag Check

Busy Flag Check

Busy Flag Check

INSTRUCTION

2-2. Interface with 4-bit MPU

When interfacing data lengths are 4-bit, only 4 ports, from DB4 to DB7, are used as data bus.
At first higher 4-bit (in case of 8-bit bus mode, the contents of DB4-DB7) are transferred, then the lower 4­bit (in case of 8-bit bus mode, the contents of DB0-DB3) are transferred. So transfer is performed twice.
Busy Flag outputs “High” after the second transfer are ended.
Example of timing sequence is shown below.

RS
R/W

E
Internal

signal
DB7

Internal operation

INSTRUCTION

INSTRUCTIONBusy Flag Check

Busy Flag Check

D7 D3 AC3

Busy

AC3

No

Busy

D3D7

Fig 2. Example of 4-bit Bus Mode Timing Diagram

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0071

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APPLICATION INFORMATION

1. COM / SEG output rotation mode A

1-1. DDRAM address mode 1 (A = 1) (2 Line)

APU0071

BOTTOM VIEW

S20 S1S80 S21

C1

C8

C9

C16

S1

S20S21S80

(M0 = 0, M1 = 0)

..................................................... .....................................................

................

................

APU0071

BOTTOM VIEW

S1 S20 S21 S80

C8

C1

C16

C9

(M0 = 0, M1 = 1)

S1 S20 S21 S80

....................

....................

...................................................... ......................................................

1-2. DDRAM address mode 1 (A = 1) (2 Line)

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0071

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2. COM / SEG output rotation mode B

2-1. DDRAM address mode 1 (A = 1) (2 Line)

APU0071

TOP VIEW

S21 S80

S1 S20

C9

C16

C1

C8

S80S21S20S1

(M0 = 1, M1 = 0)

................

................

........................................................ .......................................................

APU0071

TOP VIEW

S80 S21S20 S1

C16

C9

C8

C1

(M0 = 1, M1 = 1)

S80 S21 S20 S1

.................

.................

..................................................... ........................................................

2-2. DDRAM address mode 1 (A = 1) (2 Line)

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0071

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3. POWER SUPPLY for DRIVING LCD PANEL

R

R

R

R

R

V

DD

V

2

APU0071

∗

R = 1.5KΩ(Typ) ± 50%

V

1

V

3

V

4

V

5

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0071

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INTIALIZING

1. INITIALIZE BY INTERNAL POWER-ON-RESET CIRCUIT

When the power is turned on, APU0071 is initialized automatically by power on reset circuit.
During the initialization, the following instructions are executed, and BF (Busy Flag) is kept “High” (busy
state) up to the end of initialization.

2. POWER ON INITIALIZE FLOW

2-1 . Display Clear

Write “20H” to all DDRAM

2-2 . Set Functions

DL = 1 : 8-bit bus mode
A = 1 : 2 Line
M0 = 0 : No Rotation
M1 = 1 : Bottom view mode

2-3 . Control Display ON / OFF instruction

D = 0 : Display OFF
C = 0 : Cursor OFF
B = 0 : Blink OFF

2-4 . Set Entry Mode

I / D = 1 : Increment by 1
S = 0 : No entire display shift

3. INITIALIZE BY EXTERNAL HARDWARE RESET

If the “Low” signal is forced to reset terminal over a period of 1.2 ms then system will be initialized. And BF
(Busy Flag) is kept “High” (busy state) for 629 us after releasing the initializing sequence.

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0071

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4. INITIALIZING BY INSTRUCTION

4-1. 8-bit interface mode

Power on

Wait for more than 20ms

after V

DD

rises to 4.5V

Wait for more than 37µs

Display ON/OFF Control

Wait for more than 37µs

Display Clear

Entry Mode Set

Initialization End

4-bit interface

COM / SEG output rotation mode A
COM / SEG output rotation mode B
1line 16 character display mode
2line 8 character display mode

8-bit interface
DDRAM Addressing mode 1
DDRAM Addressing mode 2

0

0

0

0

1

1

1

1

DL

A

M0

M1

Condition : f

OSC

= 270kHz

D

C

B

0
1
0
1
0
1

display off
display on
cursor off
cursor on
blink off
blink on

I / D

S

0
1
0
1

decrement mode
increment mode
entire shift off
entire shift on

Function set

00001DL

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

A∗M1 M0

000000

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1DCB

000000

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0001

000000

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

01

I / D

S

Wait for more than 629µs

Copyright  ANPEC Electronics Corp.
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Function set

Power on

Wait for more than 20ms

after V

DD

rises to 4.5V

Wait for more than 37µs

Display ON/OFF Control

000
001

00

DC0B

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

XXXXXXX

X

Wait for more than 37µs

Display Clear

000
000

00
0001

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

XXXXXXX

X

Entry Mode Set

000
000

00
1

I / D

0

SH

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

XXXXXXX

X

Initialization End

4-bit interface

COM / SEG output rotation mode A
COM / SEG output rotation mode B
1line 16 character display mode
2line 8 character display mode

8-bit interface
DDRAM Addressing mode 1
DDRAM Addressing mode 2

0

0

0

0

1

1

1

1

DL

A

M0

M1

Condition : f

OSC

= 270kHz

D

C

B

0
1
0
1
0
1

display off
display on
cursor off
cursor on
blink off
blink on

000010

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

XXXX

Wait for more than 37µs

Function set

000010

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

XXXX

00A M1M0XXXX

I / D

S

0
1
0
1

decrement mode
increment mode
entire shift off
entire shift on

X

4-2. 4-bit interface mode

Copyright  ANPEC Electronics Corp.
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APU0071

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Frame frequency

1/16 duty cycle

1 234

1-line selection period

15 16

123 1516

V

CC

COM1

.......

1 FRAME 1 FRAME

V

1

V

4

V

5

.............

.............

1-Line selection period = 160 clocks
One Frame = 40 × 16 × 3.7µs × 4 = 9.472ms (1 CLOCK = 3.7µs at f

osc

=270KHz)

Frame frequency = 1 / 9.472ms = 105.6Hz

Maximum absolute limit

Maximum absolute Power Ratings
∗Voltage greater than above may damage to the circuit (VDD ≥ V2 ≥ V3 ≥ V5 , V

LCD

= VDD - V5)

Item

Power supply voltage (1)
Power supply voltage (2)

Input voltage

Symbol

V

DD

V

LCD

V

IN

Unit

V
V
V

Value

-0.3 to +7.0

-0.3 to +7.0

-0.3 to V

DD

+0.3

Item

Operation temperature

Storage temperature

Symbol

Topr

Tstg

Unit Value

-30 to +85

-55 to +125

o

C

o

C

Temperature Characteristics

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0071

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Electrical characteristics

DC Characteristics

(V

DD

= 4.5V to 5.5V, Ta = -30 to +85°C)

Item Symbol Con d itio n Min Ty p Ma x Unit

Operating Voltage

V

DD



4.5



5.5 V

Supply Cu rrent

I

DD

Internal oscillat io n

(V

DD

= 5.0V, f

OSC

= 270KHz )



1.0 1.8 mA

V

IH1



0.7V

DD



V

DD

Input Voltage (1) (EXTCLK)

V

IL1



-0.3



0.8

V

V

IH2



VDD -1.0



V

DD

Input Voltage (2) (EXTCLK)

V

IL2



-0.2



1.0

V

V

IH3



0.8 V

DD



V

DD

Input Voltage (2) (E pin)

V

IL3



¡V



0.2 V

DD

V

V

OH1

I

OH

= -0.205 (mA)

2.4



Output Voltage (1)
(DB0 to D B 7 )

V

OL1

I

OL

= 1.6 (mA)

¡V



0.4

V

V

OH2

IO = -40 (µA)

0.9 V

DD



¡V

Output Voltage (2)
(except DB0 to DB7)

V

OL2

IO = 40 (µA)



0.1 V

DD

V

Vd

COM



1

Voltage Drop

Vd

SEG

IO = ±0.1 (mA)



1

V

Input Leakage Current

I

IL

V

IN

= 0V to V

DD

-1



1

µ

A

Low Input Current

I

IN

V

IN

= 0V , V

DD

= 5V

(PULL UP)

-50 -125 -250

µ

A

V

2

2.7 3.0 3.3

LCD Driving Voltage

V

3

V

DD

= 5V , V5 = 0V

SEG o u tput po rt

1.7 2.0 2.3

V

Divide Resistor

R

B

V

DD

- V5 = 5V

R

B

= (V

DD

- V5) / I

B

IB = Divide Resistor Current

3.7 7.5 11.5

K

Ω

Internal Clock (internal Rf)

f

IC

V

DD

= 5V

190 270 350 KHz

LCD Driving Voltage

V

LCD

V

DD

- 5V

3.0



7.0 V

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0071

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(V

DD

= 2.7V to 4.5V, Ta = -30 to +85oC)

Item Sym bol Condition Min Typ Max Unit

Operating Voltage

V

DD



2.7



4.5 V

Supply C u r ren t

I

DD

Internal oscillation

(V

DD

= 3.0V , f

OSC

= 270KHz)



0.5 1.2 mA

V

IH1



0.7V

DD



V

DD

Input Voltage (1)
(except OSC1)

V

IL1



-0.3



0.4

V

V

IH2



VDD -1.0



V

DD

Input Voltage (2)
(OSC1)

V

IL2



-0.2



0.2 V

DD

V

V

IH3



0.8 V

DD



V

DD

Input Voltage (2)
(E pin)

V

IL3



0.4

V

V

OH1

I

OH

= -0.1 (mA )

0.75 V

DD



Output Voltage (1)
(DB0 to DB7)

V

OH1

I

OL

= 1.1 (mA)



0.2 V

DD

V

V

OH2

IO = -40 (µA)

0.8 V

DD



Output Voltage (2)
(except DB 0 to D B7)

V

OH2

IO = 40 (µA)



0.2 V

DD

V

Vd

COM



1

V oltage Drop

Vd

SEG

IO = ±0.1 (mA)

V

LCD

= 5V



1

V

Input Leakage Current

I

IL

V

IN

= 0V to V

DD

-1



1

µ

A

Low Input Current

I

IN

V

IN

= 0V , V

DD

= 3V

(PULL UP)

-10 -50 -120

µ

A

V

2

0.7 1.0 1.3

LCD Driving Voltag e

V

3

V

DD

= 3V , V5 = -2V

SEG output port

-1.7 0 0.3

V

Divide Resisto r

R

B

V

DD

- V5 = 5V

R

B

= (V

DD

- V5) / I

B

IB = Divide Re sistor C u rren t

3.7 7.5 11.5

K

Ω

Internal Clock (internal Rf)

f

IC

V

DD

= 3V

190 270 350 KHz

LCD Driving Voltag e

V

LCD

V

DD

- 5V

3.0



7.0 V

Anpec Electronics Corp.

Head Office :

5F, No. 2 Li-Hsin Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : [phone]
Fax : [phone]

Taipei Branch :

7F, No. 137, Lane 235, Pac Chiao Rd.,
Hsin Tien City, Taipei Hsien, Taiwan, R. O. C.
Tel : [phone]
Fax : [phone]

Customer Service

Copyright  ANPEC Electronics Corp.
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APU0071

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AC Characteristics

(V

DD

= 4.5V to 5.5V, Ta = -30 to +85°C)

Mode Item Symbol Min Typ Max Unit

E Cycle Time

t

C

500



E Rise / Fall Time

t

r

, t

f



20

E Pules Width (High, Low)

t

W

230



R / W and RS Setup Time

t

SU1

40



R / W and RS Hold Time

t

h1

10



Data Setup Time

t

SU2

80



Write Mode
(Refer to Fig-3)

Data Hold Time

t

h2

10



ns

E Cycle Time

t

C

500



E Rise / Fall Time

tr, t

f



20

E Pules Width (High, Low)

t

W

230



R / W and RS Setup Time

t

SU

40



R / W and RS Hold Time

t

h

10



Data Setup Time

t

D



120

Read Mode
(Refer to Fig-4)

Data Hold Time

t

DH

20



ns

Mode Item Symbol Min Typ Max Unit

E Cycle Time

t

C

1000



E Rise / F all Time

tr, t

f



25

E Pules Width (High , Low)

t

W

450



R / W and RS Setup Time

t

SU1

60



R / W and RS Hold Time

t

h1

20



Data Setup Time

t

SU2

195



Write Mode
(Refer to Fig-3)

Data Hold Time

t

h2

10



ns

E Cycle Time

t

C

1000



E Rise / F all Time

tr, t

f



25

E Pules Width (High , Low)

t

W

450



R / W and RS Setup Time

t

SU

60



R / W and RS Hold Time

t

h

20



Data Setup Time

t

D



360

Read Mode
(Refer to Fig-4)

Data Hold Time

t

DH

5



ns

(V

DD

= 2.7V to 4.5V, Ta = -30 to +85°C)

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0071

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Fig-3. Write Mode Timing Diagram

Fig-4. Read Mode Timing Diagram

V

IH1

Valid DataDB0 ~ DB7

E

R / W

RS

V

IH1

V

IH1

V

IH1

V

IL1

V

IL1

V

IL1

V

IL1

V

IL1

V

IL1

V

IL1

V

IH1

V

IL1

t

SU1

t

W

t

h1

t

h1

t

f

t

r

t

h2

t

SU2

t

C

V

IH1

Valid DataDB0 ~ DB7

E

R / W

RS

V

IL1

V

IH1

V

IL1

V

IH1

V

IH1

V

IL1

t

W

t

h

t

h

V

IH1

t

f

t

DH

t

D

t

r

V

OH1

V

OL1

t

C

V

OH1

V

OL1

V

IL1

t

SU

Copyright  ANPEC Electronics Corp.
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APU0071

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