Datasheet APU0065YE-TY Datasheet (ANPEC)

40 CH Driver for Dot Matrix LCD

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0065

www.anpec.com.tw1

PRELIMINARY

ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.

FEATURES

GENERAL DESCRIPTION

The APU0065 is a LCD driver LSI that is fabricated
by low power CMOS technology. Basically this LSI

consists of 20 × 2bit bi-directional shift register, 20 ×
2bit data latch and 20 × 2bit driver. This LSI can be

CMOS Process used a Common or Segment driver.

APPLICATIONS

••

••

• Dot matrix LCD driver with 40 channel

output.

••

••

• Selectable function to use Common / Segment

drivers simultaneously.

••

••

• Input / Output signal

••

••

• Output ; 20 × 2 channel waveform for LCD

driving

••

••

• Input ; - Serial display data and control pulse

from the controller LSI .

••

••

• Bias voltage (V1 - V6)

••

••

• QFP64 and bare chip available

ORDERING INFORMATION

Driver (cascade connection) Controller

Other APU0065 APU0066

••

••

• Display driving bias ; static-1/5

••

••

• Power supply voltage ; VDD= +5V ± 10%
VDD= +3V ± 10%

••

••

• Supply voltage range for display : ≤ 10V

••

••

• Negative display voltage :

0 ≥ V

EE

≥ V

DD

- 10V

••

••

• Interface

APU0065

Package Type

Handling Code

Package Type
Q : QFP
Y : Chip

Handling Code
TY : Tray

E

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0065

www.anpec.com.tw2

PRELIMINARY

Figure 1. Block diagram of APU0065

LATCH Part 2

LATCH Part1

End Stage

Output Voltage

Multiplexor

Part1

SHIFT Part 1

Pre-Stage

Output

Voltage

Multiplexor

Part1

SC1~SC20

DL1

DR1

Common/Segment Mode

Control Signal Convert

Part

latch

clock_1_20

register

clock_1_20

SHL1 FCSCL1 CL2

V

1S

End Stage

Output Voltage

Multiplexor

Part2

SHIFT Part 2

SC21~SC40

DR2

SHL2

Pre-Stage

Output

Voltage

Multiplexor

Part2

DL2

V

3

latch

clock_21_40

register

clock_21_40

M_1_20 M_21_40

PART 1

PART 2

M

V

4

V5V

6

V1V

2

V

2S

V

3S

V

4S

Figure 2. QFP 64 Top View

51 50 49 48 47 46 45 44 43 42 41 40 38 37 36 35 34 3339

APU0065

32

31

30

29

28

27
26

25

24

23

22

21

20

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

SC29

64

63

62

61

60

59

58

57

56

55

54

53

52

SC28 SC27 SC26 SC25 SC24 SC23 SC22 SC21 SC20 SC19 SC18 SC17 SC16 SC15 SC14 SC13 SC12

SC9

SC10

SC11

SC8

SC7

V

DD

SC6

SC5

SC4

SC3

SC2

SC1

V

EE

CL1CL2

V

SS

DL1DR1DL2DR2MSHL1SHL2FCS

V

1V2V3V4V5V6

SC40

SC39

SC38

SC37

SC36

SC35

SC30

SC31

SC32

SC33

SC34

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0065

www.anpec.com.tw3

PRELIMINARY

PIN DESCRIPTION-QFP100

Note : Input pin can not be floated, or it will cause large leakage current.

PAD (NO.)

INPUT/

OUTPUT

NAME

DESCRIPTION INTERFACE

VEE(33) Power

Operating Voltage For logical circuit (+5V 10%, +3V 10%)

Power Supply

V

DD

(25) Power

Power Operating Voltage

Power Supply
Power SupplyV

SS

(36)

Negative Supply Voltage For LCD driver circuit(0 V

EE

VDD-10V)

0V (GND)

V

1

~ V

6

(46 ~ 51)

Input Bias Voltage Bias Voltage level for LCD driveInput

M (42)

Input

Altemated signal for LCD
driver output

CL1, CL2

(34, 35)

Input Data shift / latch clock

Controller

Controller

Input

FCS (45)

Mode selection

Controller

If FCS equals to V

SS

, Part1 and Part2 both are segment mode.

If FCS equals to V

DD

, Part1 is segment mode but Part2 is

common mode .

DL1, DR1

(37, 38)

Data interface

SHL1 (43) Input

Shifting direction control
signal of Part1

Controller

or

APU0063

SC1 ~ SC20 Output LCD driver

LCD driver output of Part1

Selection of the shift directon of Part 1 shift register

LCD

DL2, DR2

(39, 40)

Input

Output

Data interface

SHL2 (44) Input

Controller

or

APU0063

SC21 ~ SC40 Output LCD driver

Selection of the shift directon of Part 2 shift register

Data input / output of Part1 shift register

Data input / output of Part 2 shift register

SHL1 DL1

DR1

V

DD

output

inputV

DD

V

SS

input output

SHL2 DL2 DR2

V

DD

output InputV

DD

V

SS

Input output

Input

Output

Power Supply

This is the signal for LCD twisting

These signal control the shift and latch of
driver. More detail scription in next line

FCS

.

Shifting direction control
signal of Part2

LCD driver output of Part2 LC D

Controller

Controller

Mode CL1 CL2 M

Segment

Common

M

M

latchshift

shiftlatch

≥

≥

±

±

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0065

www.anpec.com.tw4

PRELIMINARY

SEGMENT MODE

When Part1 or Part2 be selected to work in seg­ment mode (FCS pin = VSS), these are the liquid
crystal segment drive outputs. A signal of driving pin
in segment mode is the one of V1, V2, V3 or V4.
These selecting are following.

COMMON MODE

Only Part2 can be selected to work in common
mode (FCS pin = VDD). These are the liquid crystal
common drive outputs signal of driving pin in
segment mode is the one of V1, V2,, V5 or V6. These
selecting are following.

Part1

When Part1 shift direction control signal,
SHL1, is set to VSS.
Now the Part1 register shift direction is
DL1 → SC1 → SC2 → . . . → SC19 → SC20
→ DR1
Otherwise,when SHL1 is set to VDD.Its
direction is
DL1 ← SC1 ← SC2 ← . . . ← SC19 ← SC20
← DR1

Data o f la tch M Outp ut vo lta g e

High High

V

1

High Low

V

2

Low High

V

3

Low Low

V

4

Data o f la tch M Ou tp u t vo lta ge

High High

V

2

High Low

V

1

Low High

V

6

Low Low

V

5

Part2

When Part2 shift direction control signal,
SHL2, is set to VSS.
Now the Part1 register shift direction is
DL2 → SC21 → SC22 → . . . → SC39 →
SC40 → DR2
Otherwise,when SHL2 is set to VDD.Its
direction is
DL2 ← SC21 ← SC22 ← . . . ← SC39 ←
SC40 ← DR2

MAXIMUM ABSOLUTE LIMIT (Ta = 25 °C)

Characteristic Symbol Value

Unit

Operating Voltage
Driver Supply Voltage

Input Voltage 1

Input Voltage 2 (V1 ~ V6)

Operating Temperature
Storage Temperature

V

DD

V

LCD

V

IN1

V

IN2

T

OPR

T

STG

-0.3 ~ +7.0

V

DD

-13.5 ~ VDD+0.3

-0.3 ~ V

DD

+0.3

V

DD

+0.3 ~ VEE-0.3

-30 ~ +85

-55 ~ +125

V
V
V
V

o

C

o

C

SHIFT DIRECTION SPECIFICATION

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0065

www.anpec.com.tw5

PRELIMINARY

ELECTRICAL CHARACTERISTICS

DC characteristics (V

DD

= 2.7 ~ 5.5V, 0 ≥ VEE ≥ V

DD

- 10V, V

SS

= 0V, Ta = -30 ~ +85 °C)

AC characteristics (V

DD

= 2.7 ~ 5.5V, 0 ≥ VEE ≥ V

DD

- 10V, V

SS

= 0V, Ta = -30 ~ +85 °C)

Characteristic Symbol Unit

Operating Current*
Supply Current*
Input High Voltage

I

DD

I

LKC

V

IH

V

IL

V

OH

Input Low Voltage

Test condition

f

CL2

= 400KHz

f

CL1

= 1KHz

Input Leakage Current
Output High Voltage

Output Low Voltage

Min Ma x

1

10

_
_

Voltage Descending

Leakage Current

I

EE

V

OL

V

D1

V

D2

I

V

I

ON

= 0.1mA for one of SC1 ~ SC40

I

ON

= 0.05mA for each SC1 ~ SC40

_

V

IN

= 0 - V

DD

I

OH

= -0.4mA

I

OL

= +0.4mA

0.7 V

DD

V

DD

0.2 V

DD

0

mA

µ

A

V

µ

A

V

µ

A

-5

5

V

DD

- 0.4

_
_
_
_

0.4

1.1

1.5

10-10

V

IN

= V

DD

~ V

EE

(Output SC1 ~ SC40 : floating)

Applicable pin

V ( V1 ~ V6 ) -

SC ( SC1 ~ SC40 )

V

1

~ V

6

DL1, DL2, DR1, DR2

CL1, CL2, DR1, DR2,

DR1, DR2, SHL1, SHL2,

M, FCS

_

Characteristic Symbol Unit

Data shift Frequency
Clock High Level Width

f

CL

t

LS

t

WCKL

t

SL

tR / t

F

Test condition

Min M ax

_

t

WCKH

t

SU

t

DH

t

D

KHz

ns

_

_

Applicable pin

DL1,DL2,DR1,DR2

CL2

Clock Low Level Width

Clock Set-up Time

Clock Rise / Fall Time
Data Set-up Time
Data Hold Time
Data Delay Time

_

_

_

_

_

_

_

_

_

_

_

_

from CL2 to CL1
from CL1 to CL2

800
800
500
500

300
300

600

400

200

DL1,DL2,DR1,DR2,FLM

CL2

CL1,CL2

CL1,CL2

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0065

www.anpec.com.tw6

PRELIMINARY

TIMING CHARACTERISTICS

Figure 3. Timing diagram of signals

CL2

Data in

(DL1,DL2)

(DR1,DR2)

Data out

(DL1,DL2)

(DR1,DR2)

CL1

FLM

V

IL

V

IH

V

IH

V

IL

V

OH

V

OL

t

D

t

R

t

WCKH

t

WCKL

t

F

t

DH

t

SU

V

IL

V

IH

t

SL

t

LS

t

LS

t

WCKH

V

IL

t

F

t

SU

t

R

V

IL

V

IH

V

IH

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0065

www.anpec.com.tw7

PRELIMINARY

FUNCTIONAL DESCRIPTION

1) Segent mode

CL1

CL2

DL1 / DR1
DL2 / DR2

M

OUTPUT OF

LATCH (SC)

Latch

Shift

SC1 SC2 SC40SC39

SC1~SC40

When the FCS is connected to VSS, APU0065 (SC1 ~ SC40) is operated as segment driver.
(refer to figure 5)
Figure 4. timing diagram of Segment mode

2) Common mode

When the FCS is connected to VDD, only part2 (SC21 ~ SC40) of APU0065is operated as common driver.
(refer to figure 6.)
Figure 5. timing diagram of Common mode

OUTPUT OF

LATCH (SC)

CL1

CL2

M

DL2 / DR2

Latch

Shift

SC21~SC40

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0065

www.anpec.com.tw8

PRELIMINARY

Figure 6. SC1 ~ SC40 output waveform

V

1

FCS

OUTPUT OF

LATCH (DATA)

M

PART 1

(SC1 ~ SC20)

PART 2

(SC21 ~ SC40)

V

1

V

1

V

1

V

2

V

2

V

2

V

2

V

3

V

3

V

4

V

4

V

6

V

5

V

5

V

6

Note : When fcs equals to high voltage, P ART 2 (SC21 ~ SC40) is operated as LCD Common driver.
P AR T 1 (SC1 ~ SC20) always be operated as LCD segment driver, no matter fcs equals to high or low

Anpec Electronics Corp.

Head Office :

5F, No. 2 Li-Hsin Road, SBIP,
Hsin-Chu, T aiwan, R.O.C.
T el : 886-3-5642000
Fax : [phone]

Taipei Branch :

7F, No. 137, Lane 235, Pac Chiao Rd.,
Hsin Tien City, Taipei Hsien, Taiwan, R. O. C.
T el : 886-2-89191368
Fax : [phone]

Customer Service

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0065

www.anpec.com.tw9

PRELIMINARY

APPLICATION CIRCUIT

1. Segment driver

APU0066

(controller)

COM1

~

COM16

M CLK2 CLK1 D

common signal

LCD

SHL1
SHL2
FCS

DL2 CL1 CL2 M

DR1

DL1

APU0065

(Seg driver)

SC1~SC40

DR2

SHL1
SHL2

FCS

DL2 CL1 CL2 M

DR1

DL1

APU0065

(Seg driver)

SC1~SC40

DR2

OPEN

2. Segment / Common driver

Common signal

Controller

M CL1 CL2

D

LCD

DL1
DL2

SHL2 CL2 CL1 M

SHL1

FCS

APU0065

(Seg / Com driver)

SC1~SC20

DR1

SHL1
SHL2

FCS

DL2 CL2 CL1 M

DR1

DL1

APU0065

(Seg driver)

SC1~SC40

DR2

OPEN

FLM

SC21~SC40

V

DD

Segment signal

Figure 7. Connection between APU0065 and Controller

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0065

www.anpec.com.tw10

PRELIMINARY

Figure 8. Chip pad arrangement

9

10

7

8

5

6

3

4

17

18

15

16

13

14

11

12

2

1

42

41

44

43

46

45

484733

32

35

34

37

36

40

38

49

60

59

58

57

56

55

54

53

52

51

50

SC29

SC34

SC28

SC27

SC26

SC25

SC33

SC32

SC31

SC30

SC35

SC36

SC37

SC38

SC39

SC40

SC24

SC23

SC22

SC21

SC20

SC19

SC18

SC17

SC16

SC15

SC14

SC13

SC12

CL1

CL2

V

SS

DL1

DR1

DL2

DR2

M

SHL1

SHL2

FCS

V

1

new pad coordinate of

APU0065

Chip size : 2010

×

1670

Pad size : 80

×

80

Pitch length : 100

Unit :

µ

m

(0.0) is the center of the chip

V

2

V

3

V

4

V

5

V

6

V

6

19

20

21

22

23

24

25

26

27

28

29

30

31

SC9

SC10

SC11

SC8

SC7

V

DD

SC6

SC5

SC4

SC3

SC2

SC1

V

EE

(0.0)

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0065

www.anpec.com.tw11

PRELIMINARY

PAD LOCATION

COORDINAT E COORDINAT E

PAD NUMBER PAD NAME

XY

PAD NUMBER PAD NAME

XY

1 SC29 902.5 630.0 31 V

EE

-902.5 -630.0
2 SC28 850.0 732.5 32 CL1 -800.0 -722.5
3 SC27 725.0 732.5 33 CL2 -700.0 -732.5
4 SC26 600.0 732.5 34 V

SS

-600.0 -732.5
5 SC25 500.0 732.5 35 DL1 -500.0 -732.5
6 SC24 400.0 732.5 36 DR1 -400.0 -732.5
7 SC23 300.0 732.5 37 DL2 -300.0 -732.5
8 SC22 200.0 732.5 38 DR2 -200.0 -732.5
9 SC21 100.0 732.5 40 M -100.0 -732.5

10 SC20 0.0 732.5 41 SHL1 0.0 -732.5
11 SC19 -100.0 732.5 42 SHL2 100.0 -732.5
12 SC18 -200.0 732.5 43 FCS 200.0 -732.5
13 SC17 -300.0 732.5 44 V

1

315.0 -732.5

14 SC16 -400.0 732.5 45 V

2

430.0 -732.5

15 SC15 -500.0 732.5 46 V

3

545.0 -732.5

16 SC14 -600.0 732.5 47 V

4

660.0 -732.5

17 SC13 -725.0 732.5 48 V

5

775.0 -732.5

18 SC12 -850.0 732.5 49 V

6

905.0 -632.5
19 SC9 -902.5 630.0 50 SC40 902.5 -525.0
20 SC10 -902.5 525.0 51 SC39 902.5 -420.0
21 SC11 -902.5 420.0 52 SC38 902.5 -315.0
22 SC8 -902.5 315.0 53 SC37 902.5 -210.0
23 SC7 -902.5 210.0. 54 SC36 902.5 -105.0
24 V

DD

-902.5 105.0 55 SC35 902.5 0.0
25 SC6 -902.5 0.0 56 SC30 902.5 105.0
26 SC5 -902.5 -105.0 57 SC31 902.5 210.0
27 SC4 -902.5 -210.0 58 SC32 902.5 315.0
28 SC3 -902.5 -315.0 59 SC33 902.5 420.0
29 SC2 -902.5 -420.0 60 SC34 902.5 525.0
30 SC1 -902.5 -525.0