Datasheet APU0063YE-TY, APU0063QE-TY Datasheet (ANPEC)

80 CH Driver for Dot Matrix LCD

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0063

www.anpec.com.tw1

PRELIMINARY

ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.

FEATURES GENERAL DESCRIPTION

The APU0063 is a LCD driver LSI that is fabricated
by low power CMOS technology. Basically this LSI
consists of 40 × 2bit bi-directional shift register, 40

× 2bit data latch and 40 × 2bit driver.

APPLICATIONS

• Dot matrix LCD driver with 80-channel output.

• Input / Output signal

• Output ; 40 × 2 channel waveform for LCD

driving

• Input ; - Serial display data and control pulse

from controller LSI .

ORDERING INFORMATION

Display driving bias ; static-1/5

• Power supply voltage ; +5V ± 10%

+3V ± 10%

• Supply voltage range for display : ≤ 10V

• Negative display voltage :

0 ≥

V

EE

≥

VDD-10V

• CMOS Process

• Interface

APU0063

Package Type

Handling Code

Package Type
Q : QFP
Y : Chip

Handling Code
TY : Tray

E

Driver (cascade connection) Controller

Other APU0065 APU0066

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0063

www.anpec.com.tw2

PRELIMINARY

Pre-Stage

Output Voltage

Multiplexor

Part1

End Stage

Output Voltage

Multiplexor

Part1

LATCH part1

SHIFT part 1

SC1~SC40

DL1

DR1

latch clock

register clock

SHL1 CL1

CL2

V

1S

V

2S

End Stage

Output Voltage

Multiplexor

Part2

LATCH part 2

SHIFT part 2

SC41~SC80

DR2

SHL2

DL2

V1V

2

PART 1

PART 2

M

V3V

4

V

1S

V

2S

Figure 1.Block diagram of APU0063

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0063

www.anpec.com.tw3

PRELIMINARY

APU0063

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

S30

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51
50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

M

DR2

DL2

DR1

DL1

CL2

V

DD

NC

NC

SHL2

SHL1

CL1

GND

V

1

V

EE

NC

NC

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

100

S72

S73

S74

S75

S76

S77

S78

S79

S80

S40

S39

S38

S37

S36

S35

S34

S33

S32

S31

S71
S41

S29

S28

S27

S26

S25

S24

S23

S22

S21

S20

S19

S18

S17

S16

S15

S14

S13

S12

S11

S10
S9

S8

S7

S6

S5

S4

S3

S2

S1

V

2

V

3

V

4

S42

S43

S44

S45

S46

S47

S48

S49

S50

S51

S52

S53

S54

S55

S56

S57

S58

S59

S60

S61

S62

S63

S64

S65

S66

S67

S68

S69

S70

Figure 2. QFP100 Top View

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0063

www.anpec.com.tw4

PRELIMINARY

PIN DESCRIPTION-QFP100

NOTE : Input pin can not be floated,or it will cause large leakage current.

PIN(NO.)

V1 ~ V4(32 ~ 35)

INPUT

¡þ

OUTPUT

NAME

Negative Supply

Voltage

Altemated Signal for

LCD Driver Output

DESCRIPTION

The signal enable the latch, it is
negative senstive latched.

Power

INTERFACE

Power SupplyVEE(31)

VDD(42) Power

VSS(36) Power

Operating Voltage

Operating Voltage

Bias VoltageInput

Input

M(48)

For LCD driver circuit
(0 V

EE

VDD-10V)

For logic circuit
(+5V 10% ,+3V



10%)

0V(GND)

Bias Voltage level for LCD drive

This is the signal for LCD twisting

Selection of the shift directon of
Part1 shift register

The signal enable the shift
register, it is negative edge-trigger.

SHL1

V

DD

V

SS

DL1

Output

Input

DR1

Input

Output

CL1(37)

CL2(43)

SHL1(38)

DL1, DR1

(44, 45)

Controller

or

APU0066

SC

1

~ SC

40

Selection of the shift directon of
Part2 shift register

SHL2

V

DD

V

SS

DL2

Output

Input

DR2

Input

Output

SHL2(39)

DL2, DR2

(46, 47)

SC

41

~ SC

80

Power Supply

Power Supply

Power Supply

Controller

Controller

Controller

Controller

LCD

Controller

Controller

or

APU0066

LCD

Input

Input

Input

Input

Output

Output

Input

Input

Output

Output

Data Latch Clock

Data Shift Clock

Shifting Direction

Control Signal of

Part1

Shifting Direction

Control Signal of

Part2

Data Interface

LCD Driver

Data Interface

LCD Driver

Data input / output pf Part1 shift
register

Data input / output pf Part2 shift
register

LCD driver output of Part1

LCD driver output of Part2

≥≥

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0063

www.anpec.com.tw5

PRELIMINARY

DRIVER OUTPUT VOLTAGE

A signal of driving pin is the one of V1,V2,V3 or V4.These selecting are following.

SHIFT DRIRECTION SPECIFICATION

Data of latch M O utput voltage

High High V

1

High Low V

2

Low High V

3

Low Low V

4

Part2

When Part2 shift direction control signal,
SHL2, is set to VSS.
Now the Part2 register shift direction is
DL2

→

SC41

→

SC42

→ . . . →

SC79

→

SC80

→

DR2

Otherwise,when SHL2 is set to VDD.Its
direction is
DL2

← SC41 ← SC42 ← . . . ←

SC79 ←

SC80 ← DR2

Part1

When Part1 shift direction control signal ,
SHL1, is set to VSS.
Now the Part1 register shift direction is
DL1

→

SC1

→

SC2

→

. . . →

SC39

→

SC40

→ DR1
Otherwise,when SHL1 is set to VDD.Its
direction is
DL1

←

SC1

←

SC2

← . . . ←

SC39

←

SC40

← DR1

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0063

www.anpec.com.tw6

PRELIMINARY

MAXIMUM ABSOLUTE LIMIT (Ta = 25 °C)

∗ Voltage greater than above may damage to the circuit

ELECTRICAL CHARACTERISTICS
DC characteristics (V

DD

= 2.7 ~ 5.5V, 0 ≥

V

EE

≥ V

DD

- 10V, V

SS

= 0V, Ta = - 30 ~ + 85 °C )

AC CHARACTERISTICS (VDD = 2.7 ~ 5.5V, 0 ≥ VEE ≥ VDD - 10V, VSS = 0V, Ta= - 30 ~ + 85 °C )

Characteristic Symbol Value

Unit

Operating Voltage

Driver Supply Voltage

Input Voltage 1

Input Voltage 2 (V1~V4)

Operating Temperature

Storage Temperature

V

DD

V

LCD

V

IN1

V

IN2

T

OPR

T

STG

- 0.3 ~ + 7.0

V

DD

- 13.5 ~ V

DD

+ 0.3

- 0.3 ~ V

DD

+ 0.3

V

DD

+ 0.3 ~ V

EE

- 0.3

- 30 ~ + 85

- 55 ~ + 125

V
V
V
V

o

C

o

C

Characteristic Symbol

Unit

Operating Current*

Supply Current*

Input High Voltage

I

DD

I

LKC

V

IH

V

IL

V

OH

Input Low Voltage

Test condition

f

CL2

= 400 KHz

f

CL1

= 1 KHz

Input Leakage Current

Output High Voltage
Output Low Voltage

Min Max

1

10

_
_

Voltage Descending

Leakage Current

I

EE

V

OL

V

D1

V

D2

I

V

I

ON

= 0.1mA for one of SC1-SC80

I

ON

= 0.05mA for each SC1-SC80

_

V

IN

= 0 - V

DD

I

OH

= -0.4 mA

I

OL

= +0.4 mA

0.7 V

DD

V

DD

0.3 V

DD

0

mA

µ

A

V

V

-5

5

V

DD

- 0.4

_
_
_
_

0.4

1.1

1.5

10-10

V

IN

= V

DD

~ V

EE

(Output SC1 ~ SC80 : floating)

Applicable pin

V (V1 ~ V4) -

SC (SC1 ~ SC80)

V

1

~ V

4

DL1, DL2, DR1, DR2

CL1, CL2, DR1, DR2,

DR1, DR2, SHL1, SHL2,

M, FCS

_

µ

A

µ

A

Characteristic Symbol

Unit

Data shift Frequency

Clock High Level Width

f

CL

t

LS

t

WCKL

t

SL

tR / t

F

Test condition

Min Max

_

t

WCKH

t

SU

t

DH

t

D

_

KHz

ns

_

_

Applicable pin

DL1, DL2, DR1, DR2

CL2

Clock Low Level Width

Clock Set-up Time

Clock Rise/Fall Time

Data Set-up Time

Data Hold Time

Data Delay Time

_

_

_

_

_

_

_

_

_

_

_

_

from CL2 to CL1
from CL1 to CL2

CL1=15pF

800
800
500
500

300
300

500

400

200

DL1, DL2, DR1, DR2, FLM

CL2

CL1, CL2

CL1, CL2

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0063

www.anpec.com.tw7

PRELIMINARY

Figure 3.Timing diagram of signals

TIMING CHARACTERISTICS

CL2

Data in

(DL1,DL2)

(DR1,DR2)

Data out

(DL1,DL2)

(DR1,DR2)

CL1

FLM

V

IL

V

IH

V

IH

V

IL

V

OH

V

OL

t

D

t

R

t

WCKH

t

WCKL

t

F

t

DH

t

SU

V

IL

V

IH

t

SL

t

LS

t

LS

t

WCKH

V

IL

t

F

t

SU

t

R

V

IL

V

IH

V

IH

CL1

CL2

DL1 / DR1
DL2 / DR2

M

OUTPUT OF

LATCH (SC)

Latch

Shift

SC1 SC2 SC80SC79

SC1~SC80

Figure 4.timing diagram

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0063

www.anpec.com.tw8

PRELIMINARY

V

2

V

1

V

3

V

4

OUTPUT OF

LATCH (DATA)

M

SC

1

~SC

80

Figure 5.SC1~SC80 output waveform

Figure 6.Connection between APU0063 and Controller

APPLCATION CIRCUIT

APU0066

(controller)

COM1

~

COM16

common signal

M CLK2 CLK1 D

APU0063

(seg driver)

SHL1
SHL2
FCS

DL1
DR1

DL2 CL1 CL2 M

DR2

SC

1

~SC

80

APU0063

(seg driver)

SHL1
SHL2
FCS

DL1
DR1

DL2 CL1 CL2 M

DR2

SC

1

~SC

80

OPEN

LCD

Copyright  ANPEC Electronics Corp.

Rev. A.07 - FEB., 2002

APU0063

www.anpec.com.tw9

PRELIMINARY

79

80

81

82

83

84

85

86

87

88

89

90

91

S1

V

EE

V

1

V

2

V

3

V

4

GND

CL1

SHL1

SHL2

V

DD

CL2

DL1

92DR1

93DL2

94DR2

95M

S41

48

47

46

45

44

43

42

41

40

39

38

37

36

S32

S33

S34

S35

S36

S37

S38

S39

S40

S80

S79

S78

S77

35 S76

34 S75

33 S74

32 S73

S72

6970 6768 6566 63647778 7576 7374 7172 62

S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17

61 5960 58

S18 S19 S20 S21

57 5556 54

S22 S23 S24 S2553S26

52 5051 49

S27 S28 S30 S31S29

APU0063

X

Y

( 0 , 0 )

Chip size : 3438 x 2476
Pad size : 80 x 80
Pad Pitch : 100 ~ 125
Unit : µm

109 1211 1413 161521 43 65 87

17

S42

S43 S44 S45 S46 S47

S48 S49 S50

S51 S52 S53

S54

S55

S56

S57 S58

18 2019 21

S59

S60

S61

S62

22 2423 25

S63 S64 S65 S66

26

S67

27 2928 30

S68

S69 S70 S71

96 31

Note : ( 0 , 0 ) is center in the chip

Button left corner coordination is ( -1719 , -1238 )

Top right corner coordination is ( 1719 , 1238 )

Figure 7.Chip pad arrangement

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0063

www.anpec.com.tw10

PRELIMINARY

PAD LOCATION (1/2)

COORDINATE COORDINATE

PAD NUMBER PAD NAME

XY

PAD NUMBER PAD NAME

XY

1 SC42 -1645 -1132 33 SC74 160 9 -680
2 SC43 -1520 -1132 34 SC75 160 9 -560
3 SC44 -1395 -1132 35 SC76 160 9 -450
4 SC45 -1270 -1132 36 SC77 160 9 -350
5 SC46 -1145 -1132 37 SC78 1 609 -250
6 SC47 -1020 -1132 38 SC79 160 9 -150
7 SC48 -900 -1132 39 SC80 1609 -50
8 SC49 -780 -1132 40 SC40 1609 50

9 SC50 -660 -1132 41 SC39 1609 150
10 SC51 -550 -1132 42 SC38 1609 250
11 SC52 -45 0 -1132 43 SC37 1609 350
12 SC53 -350 -1132 44 SC36 1609 450
13 SC54 -250 -1132 45 SC35 1609 560
14 SC55 -150 -1132 46 SC34 1609 680
15 SC56 -50 -1132 47 SC33 1609 800
16 SC57 50 -1132 48 SC32 1609 920
17 SC58 150 -1132 49 SC31 1645 1132
18 SC59 250 -1132 50 SC30 1520 1132
19 SC60 350 -1132 51 SC29 1395 1132
20 SC61 450 -1132 52 SC28 1270 1132
21 SC62 550 -1132 53 SC27 1145 1132
22 SC63 660 -1132 54 SC26 1020 1132
23 SC64 780 -1132 55 SC25 900 1132
24 SC65 900 -1132 56 SC24 780 1132
25 SC66 1020 -1132 57 SC23 660 1132
26 SC67 1145 -1132 58 SC22 550 1132
27 SC68 1270 -1132 59 SC21 450 1132
28 SC69 1395 -1132 60 SC20 350 1132
29 SC70 1520 -1132 61 SC19 250 1132
30 SC71 1645 -1132 62 SC18 150 1132
31 SC72 1609 -920 63 SC17 50 1132
32 SC73 1609 -800 64 SC16 -50 1132

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0063

www.anpec.com.tw11

PRELIMINARY

PAD LOCATION (2/2)

COORDINATE COORDINATE

PAD NUMBER PAD NAME

XY

PAD NUMBER PAD NAME

XY

65 SC15 -150 1132 81

V

1

-1609 680

66 SC14 -250 1132 82

V

2

-1609 560

67 SC13 -350 1132 83

V

3

-1609 450

68 SC12 -450 1132 84

V

4

-1609 350
69 SC11 -550 1132 85 GND -1609 250
70 SC10 -660 1132 86 CL1 -1609 150
71 SC9 -780 1132 87 SHL1 -1609 50
72 SC8 -900 1132 88 SHL2 -1609 -50
73 SC7 -1020 1132 89

V

DD

-1609 -150
74 SC6 -1145 1132 90 CL2 -1609 -250
75 SC5 -1270 1132 91 DL1 -1609 -350
76 SC4 -1395 1132 92 DR1 -1609 -450
77 SC3 -1520 1132 93 DL2 -1609 -560
78 SC2 -1645 1132 94 DR2 -1609 -680
79 SC1 -1609 920 95 M -1609 -800
80

V

EE

-1609 800 96 S41 -1609 -920

Anpec Electronics Corp.

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Tel : [phone]
Fax : [phone]

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