The APT7843 Touch Screen Controller IC provides all
the screen drive , A/D converter and control circuits
to easily interface to 4 wire resistive touch screen.
The IC continually monitors the screen waiting for a
touch. When the screen touched , the IC performs
A/D converter to determine the location of touch.
Also , this device has 2 auxiliary input to A/D converter , allowing for the measurement of other inputs
such as battery voltage.
Applications
•
PDAs
•Handheld computer
•Touch-screen kiosks
Features
•
16 pin SSOP or TSSOP
•Operates with four wire touch screen
•8-bit or 12 bit A/D converter
•Ratiometric Conversion eliminates screen
calibration
•2 auxiliary analog inputs
•4 wire serial interface
•Full power down control
Pin Assignment
+Vcc1
X+
Y+
2
3
DCLK
16
15
CS
14
DIN
4
X-
5
Y-
6
GND
7
IN4V
8
13
12
11
10IN3
9
BUSY
DOUT
PENIRQ
+Vcc
REF
Order Information
APT7843
Temp. Range
Package Code
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
Package Code
N : SSOPO : TSSOP
Temp. Range
I : - 40 to 85 C
The APT7843 is a successive approximation analogto-digital (A/D) converter based around a capacitive
redistribution DAC. Figure 1 show basic operation of
the APT7843.
The APT7843 communicates via a 4-wire serial
interface. The device also requires an external reference voltage Vref. The value of the reference voltage
directly sets the input range of the converter.
The APT7843 primary function is to control resistive
touchscreens. When a touch is detected , pen interrupt pin will go low to wake up extenal microprocess.
The microprocessor writes register to initiate
conversion.
This A/D converter may also be used to measure
voltage presented on the IN3 , IN4 pins.
+2.2V to +5V
Analog Input
The analog input to the converter is provided via a
four-channel multiplexer. Figure 2 shows a simplified
diagram of the APT7843 with the difference input of
the A/D converter , and the converter’s reference.
Table I and Table II also show the relationship between
the A2 , A1 , A0 , SER/ and the configuration of
the APT7843. See the section of single-ended reference mode and differential reference mode for more
details.
Figure 3 shows the diagram of single-ended reference mode.
This application shows the measurement of current
Y poisition is made by connecting the X+ input to the
A/D converter, turning on the Y+ and Y- drivers, and
digitizing the voltage on X+ . For this measurement,
the resistance in the X+ lead does not affect the conversion. However, since the resistance between Y+
and Y- is fairly low, the on-resistance of the Y drivers
does make a small difference. Under the situation outlined so far, it would not be possible to achieve a zero
volt input or a full-scale input regardless of where the
pointing device is on the touch screen because some
voltage is lost across the internal switches. This situation can be remedied if use differential reference mode
As shown in Figure 4,by setting the SER/ bit
LOW, the +REF and -REF inputs are connected directly to Y+ and Y-. This makes the analog-to- digital
conversion ratiometric.
The result of the conversion is always a percentage
of the external resistance, reardless of how it changes
in relation to the on-resistance of the internal switches.
Note that there is an important consideration regarding power dissipation when using the ratiometric mode
of operation,the external device should powered
throughout the acquisition and conversion periods.
Data is written to,and read from , the APT7843 via
the serial port. The serial port has 4 pins - serial
clock (DCLK),chip select ( ) ,data in (DIN) and
data out (DOUT). The DCLK acts on the rising edge.
CS
The acts as a reset for the serial port with goes
low initating a conversion cycle. The cycle consists
of 2 parts - a write followed by a read. Figure 5
shows the typical timing of the APT7843’s serial
interface. A total of 24 clock cycles will complete
one conversion.
Also shown in Figure 5 is the placement and order of
the control bits within the control byte. Tables III and
IV give detailed information about these bits.
The first bit, the ′S′ bit, must always be HIGH and
indicates the start of the control byte. The APT7843
will ignore inputs on the DIN pin until the start bit S
detected.
The next three bits (A2 - A0) select the active input
channel or channels of the input multiplexer (see Tables
I and II and Figure 2).
The MODE bit determines the number of bits for each
conversion, either 12 bits (LOW) or 8 bits (HIGH).
The SER/ bit controls the reference mode: either
DFR
single-ended (HIGH) or differential (LOW). (The differential mode is also referred to as the ratiometric
conversion mode.)
The last two bits (PD1 - PD0) select the power- down
mode as shown in Table V. If both inputs are HIGH,
the device is always powered up. If both inputs are
LOW, the device enters a power-down mode between conversions.
FIGURE 6. Conversion Timing, 16-Clocks per Conversion, 8-bit Bus Interface. No DCLK Delay Required
with Dedicated Serial Port.
16-Clocks or 15-Clocks per Con-
AC Timing
version
Figure 8 and Table VI provide detailed timing of the
The APT7843 will alow a conversion every 16 clock
cycles, as shown in Figure 6. This figure shows
possible serial communication occurring with other
serial peripherals between each byte transfer between
the processor and the converter.
Figure 7 provides the fastest way to clock the
APT7843. This method will not work with the serial
interface of most microcontrollers and digital signal
processors as they are generally not capable of providing 15 clock cycles per serial transfer. However,
this method could be used with field programmable
gate arrays (FPGAs) or application specific integrated
circuits (ASICs). (Note that this effectively increases
the maximum conversion rate of the converter).
APT7843. Table VII provide detailed timing of low power
VCC=2.4V.
Terminal MaterialSolder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb)
Lead SolderabilityMeets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
Reflow Condition (IR/Convection or VPR Reflow)
Peak temperature
temperature
Pre-heat temperature
°
183 C
Time
Classification Reflow Profiles
Convection or IR/
Convection
Average ramp-up rate(183°C to Peak)3°C/second max.10 °C /second max.
Preheat temperature 125 ± 25°C)
Temperature maintained above 183°C
Time within 5°C of actual peak temperature
Peak temperature range
Ramp-down rate
Time 25°C to peak temperature
120 seconds max
60 – 150 seconds
10 –20 seconds60 seconds
220 +5/-0°C or 235 +5/-0°C215-219°C or 235 +5/-0°C
6 °C /second max.10 °C /second max.
6 minutes max.
VPR
Package Reflow Conditions
pkg. thickness ≥≥≥≥ 2.5mm
and all bgas
Convection 220 +5/-0 °CConvection 235 +5/-0 °C
VPR 215-219 °CVPR 235 +5/-0 °C
IR/Convection 220 +5/-0 °CIR/Convection 235 +5/-0 °C