Page 1
APA4801
Stereo 280mW 8Ω Speaker Driver with Mute
Features
••
•
Operating Voltage
••
Single Supply 3V to 7V
Dual Supply ±1.5V to ± 3.5V
••
•
High Signal-to-Noise Ratio 100dB
••
••
•
High Slew Rate 5V/ µs
••
••
•
Low Distortion -65dB
••
••
• Output Power at 10% THD+N
••
into 8Ω 280mW
into 16Ω 160mW
••
• Large Output Voltage Swing
••
••
• Excellent Power Supply Ripple Rejection
••
••
• Flexible Mute Function
••
••
• Integrated Voltage Divider (V
••
nate External Resistors
••
• Low Power Consumption
••
••
• Short-circuit Elimination
••
••
• Wide Temperature Range
••
••
• No Switch ON/OFF Clicks
••
••
• Available in 8 pin SOP or DIP Package
••
/2) to Elimi-
DD
Applications
••
• Portable Digital Audio
••
••
•
Personal Computers
••
••
•
Microphone Preamplifier
••
General Description
The APA4801 is an integrated class AB stereo headphone amplifier contained in an SO-8 or a DIP-8 plastic package with Mute feature . Besides the common
Mute feature , the APA4801 further integrates a voltage divider inside the chip . Thus , the external resistors can be eliminated . The device has been primarily developed for portable digital audio applications .
Block Diagram
Out A
Mute
Input A
1
2
3
MUTE
0dB
0dB
A
+
130k
B
+
Ω
Ω
130k
BIAS
8
7
6
V
DD
Out B
BIAS
V
4
SS
5
Input B
Ordering Information
APA4801
Handling Code
Temp. Range
Package Code
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2001
Package Code
J : PDIP-8 K : SOP-8
Temp. Range
I : - 40 to 85 C
Handling Code
TU : Tube
TR : Tape & Reel
°
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Page 2
APA4801
Function Pin Description
Pin Name I/O Function Description
Out A O A channel output pin
Mute I
Input A I A channel input terminal
V
SS
Input B I B channel input terminal
BIAS I Right channel bias input pin
OUT B O B channel output pin
V
DD
Absolute Maximum Ratings
Symbol Parameter Rating Unit
V
DD
t
SC(O)
T
T
T
STG
T
V
ESD
Note: 1. Human body model : C=100pF, R=1500Ω, 3 positive pulses plus 3 negative pulses
Supply Voltage 8 V
Output Short-circuit Duration, at TA=25°C, P
Operating Ambient Temperature range -40 to 85
A
Maximum Junction Temperature 150
J
Storage Temperature Range -65 to +150
Soldering Temperature,10 seconds 260
S
Electrostatic Discharge -3000 to 3000
Chip disable control input, high active and low for normal
operating
Power ground pin
Power input pin
tot
=1W
20 S
*1
C
°
C
°
C
°
C
°
V
Thermal Characteristics
Symbol Parameter Value Unit
R
THJA
Electrical Characteristics V
V
DD
VDD=5V
I
DD
V
I(OS)
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2001
Thermal Res i stance fr om Jun ction to Ambie n t in Free Air
DIP-8
SO-8
=0dBV, VDD=5V, TA=25°C, f=1kHz (unless otherwise noted)
IN
109
210
APA4801Symbol Parameter Test Conditions
Min. Typ. Max.
Power Supply Voltage 2.7 5.5
Supply Current No Load 2.5 mA
Input Offset Voltage 5 50 mV
www.anpec.com.tw2
K/W
K/W
Unit
V
Page 3
APA4801
Electrical Characteristics Cont.
APA4801Symbol Parameter Test Conditions
Min. Typ. Max.
I
Shunt Current 200
SD
Mu te l Mu te In pu t Volta ge 0.8 V
AV1- AV2Differential Channel
-0.5 0 0.5 dB
Volt ag e G ain
ATT Mute Attenuation fIN=1k, VIN =1 Vrms 75 70 dB
AC Characteristics
(THD+N
)/S
P
O
To tal Har moni c
Distortion plus Noise to
Signal Ratio
=160mW, RL=8Ω, f=1 kHz
P
O
=100mW, RL=16Ω, f=1 k H z
P
O
Output Power (THD+N)/S =0.1%, f=1kHz,
0.05
0.05
BW<80kHz
RL=8
Ω
RL=16
Ω
P
Output Power (THD+N)/S=10%, f=1kHz,
O
170
100
BW<80kHz
280
160
76 dB
PSRR Power Supply
R ejectio n Ratio
S/N Signal to Noise Ratio
RL=8
Ω
RL=16
Ω
C
=4.7 µF,V
B
=200mVrms,
RIPPLE
f=120Hz
R
=8
Ωµ
L
VDD=3V
I
Supply Current No Load 2.2 mA
DD
V
Input Offset Voltage 5 m V
I(OS )
I
SD
200
AC Characteristics
I
Shunt Current 150
SD
Mu te l Mu te Inp u t Voltag e 0.8 V
AV1- AV2Differential Channel
-0.5 0 0.5 dB
Volt ag e G ain
ATT Mute Attenuation fIN=1k ,VIN = 0.5Vrms 70 dB
(THD+
N)/S
To tal Har moni c
Distortion plus Noise to
Signal Ratio
P
=50mW, RL=8Ω, f=1 k H z
O
=25mW, RL=16Ω, f=1 kHz
P
O
0.1
0.1
S/N Signal to Noise Ratio
P
Output Power (THD+N)/S=0.1%, f=1kHz,
O
BW<80kHz
RL=8
Ω
RL=16
Ω
P
Output Power (THD+N)/S=10%, f=1kHz,
O
45
25
BW<80kHz
80
45
76 dB
PSRR Power Supply
R ejectio n Ratio
RL=8
Ω
RL=16
Ω
=4.7µF,V
C
B
f=120Hz
=200m Vrms,
RIPPLE
Unit
µ
mW
mW
Vrm s
µ
µ
Vrm s
µ
mW
mW
A
%
A
A
%
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2001
www.anpec.com.tw3
Page 4
APA4801
Test and Application Circuit
F
1
µ
V
INB
4.7
F
µ
57
4
V
SS
1µF
V
INA
68
BIAS
0dB
+
B
0dB
+
A
32 1
Input A
Mute
1µF
Out BInput B
BIAS
V
APA4801
MUTE
Out A
220µF
V
100µF
DD
V
MUTE
H : Speaker Action
L : Mute on
DD
220µF
100k
Ω
Typical Characteristics
THD+N vs Output Power
10
VDD= 5V
Ω
=8
R
L
1
THD+N (%)
0.1
0.01
10m 500m
f=20Hz
f=20kHz
f=1kHz
200m
Output Power (W)
THD+N vs Output Power
10
VDD= 5V
Ω
=16
R
L
1
f=20Hz
f=20kHz
THD+N (%)
0.1
f=1kHz
0.01
10m 200m
100m
Output Power (W)
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2001
www.anpec.com.tw4
Page 5
APA4801
Typical Characteristics Cont.
THD+N vs Frequency
10
VDD= 5V
=160mW
P
O
Ω
=8
R
L
NO FILTERS
1
THD+N (%)
0.1
0.01
20 20k100 1k 10k
Frequency (Hz)
THD+N vs Frequency
10
VDD= 5V
=100mW
P
O
Ω
=16
R
L
NO FILTERS
1
THD+N (%)
0.1
0.01
20 20k100 1k 10k
Frequency (Hz)
THD+N vs Output Power
10
VDD= 3V
Ω
=8
R
L
1
f=20kHz
THD+N (%)
0.1
0.01
10m 100m50m
f=20Hz
f=1kHz
Output Power (W)
THD+N vs Output Power
10
VDD= 3V
Ω
=16
R
L
1
THD+N (%)
0.1
0.01
10m 100m50m
f=20kHz
f=20Hz
Output Power (W)
f=1kHz
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2001
www.anpec.com.tw5
Page 6
APA4801
Typical Characteristics Cont.
THD+N vs Frequency
10
VDD= 3V
P
=50mW
O
Ω
=8
R
L
NO FILTERS
1
THD+N (%)
0.1
0.01
20 20k100 1k 10k
Frequency (Hz)
Power Dissipation vs Output Power
THD+N vs Frequency
10
VDD= 3V
PO=25mW
Ω
=16
R
L
NO FILTERS
1
THD+N (%)
0.1
0.01
20 20k100 1k 10k
Frequency (Hz)
Power Dissipation vs Output Power
200
Ω
RL= 8
150
100
Power Dissipation (mW)
50
0
0 50 100 150 200
RL= 16
Ω
Output Power (mW)
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2001
VDD= 5V
f=1kHz
THD+N<1%
BW<80kHz
80
70
60
50
40
30
Power Dissipation (mW)
20
10
0
020 4060
RL= 8
RL= 16
Ω
Ω
VDD= 3V
f=1kHz
THD+N<1%
BW<80kHz
Output Power (mW)
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Page 7
APA4801
Typical Characteristics Cont.
Supply Current vs Supply Voltage
5
NO LOAD
4
4.5
3
3.5
2
2.5
Supply Current (mA)
1
1.5
0.5
0
2.5 3 3.5 4 4.5 5 5.5
Supply Voltage (V)
Output Power vs Supply Voltage
Output Voltage (Mute Attenuation)
+0
RL= 8
Ω
VDD=5V
V
-20
-40
-60
-80
Output Voltage (dBV)
-100
=1Vrms
IN
BW<80kHz
(shutdown)
20 100k100 1k 10k
Frequency (Hz)
Output Power vs Supply Voltage
350
f=1kHz
=8
R
Ω
L
300
BW<80kHz
250
200
10% THD+N
1% THD+N
150
Output Power (mW)
100
0.1% THD+N
50
0
2.5 3 3.5 4 4.5 5 5.5
Supply Voltage (V)
250
f=1kHz
R
=16
Ω
L
BW<80kHz
200
150
10% THD+N
100
Output Power (mW)
50
1% THD+N
0.1% THD+N
0
2.5 3 3.5 4 4.5 5 5.5
Supply Voltage (V)
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2001
www.anpec.com.tw7
Page 8
APA4801
Typical Characteristics Cont.
Output Power vs Load Resistance
300
f=1kHz
V
=5V
250
DD
BW<80kHz
200
150
100
Output Power (mW)
10% THD+N
50
1% THD+N
0
816243240485664
Supply Voltage (V)
Output Power vs Load Resistance
100
70
f=1kHz
VDD=3V
BW<80kHz
60
50
10% THD+N
40
30
Output Power (mW)
20
10
0
816243240485664
1% THD+N
Supply Voltage (V)
1m
VDD=5V
Ω
=8
R
L
BW<80kHz
V)
µ
µ
100
µ
10
Output Noise Voltage (
µ
1
20
Noise Floor
Frequency (Hz)
Channel Separation
Ω
RL=8
AV= -1
=160mW
P
O
=5V
V
DD
Channel B to A
Output Level (dB)
20k100 1k
20 20k100 1k 10k
Channel A to B
Frequency (Hz)
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2001
www.anpec.com.tw8
Page 9
APA4801
Typical Characteristics Cont.
Power Supply Rejection Ratio
+0
RL=8
-10
-20
-30
-40
PSRR (dB)
-50
-60
-70
-80
Ω
AV= -1
= 200mVrms
V
Ripple
V
=5V
DD
CB=1µF
CB=2.2µF
CB=4.7µF
10 100k100 1k 10k
Frequency (Hz)
Typical Application vs Frequency Response
Frequency Response vs Output Capacitor Size
+5
+0
-5
-10
Output Level (dB)
-15
-20
20
CO=1000µF
CO=470µF
CO=220µF
CO=100µF
Frequency (Hz)
CI=10µF
V
=5V
DD
Ω
R
=8
L
100k100 1k 10k
+5
VDD=5V RL=8
Ω
+0
CI=0.1µF
-5
-10
Output Level (dB)
CO=470µF
CI=1.0µF
CO=470µF
-15
-20
20 100k100 1k 10k
Frequency (Hz)
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2001
www.anpec.com.tw9
Page 10
APA4801
Application Note
Input Capacitor, Ci
In the typical application an input capacitor , Ci , is
required to allow the amplifier to bias the input signal
to the proper DC level for optimum operation . In this
case , the external capacitor Ci and the internal resistance Ri form a high-pass filter with the corner frequency determined in the follow equation :
fc (highpass)= 1/ (2πRiCi) (1)
The value of Ci is important to consider as it directly
affects the low frequency performance of the circuit .
Consider the APA4801 where Ri is 130kΩ internal
fixed . Equation is reconfigured as follow :
Ci= 1/(2π*130kΩ*fc) (2)
And the ceramic capacitor is recommanded
Bias Capacitor, Cb
As with any power amplifier , proper supply bypassing is critical for low noise performance and high
power supply rejection . The capacitor location on
both the bypass and power supply pins should be as
close to the device as possible . The effect of a larger
half supply bias capacitor is improved PSRR due to
increased half-supply stability . Typical applications
employ a 5V regulator with 10µF and a 0.1µF bias
capacitors which aid in supply filtering . This does
not eliminate the need for bypassing the supply nodes
of the APA4801 . The selection of bias capacitors ,
especially Cb , is thus dependent upon desired PSRR
requirements , click and pop performance . The capacitor is fed from a 50kΩ source inside the amplifier.
To keep the start-up pop as low as possible , the
relationship shown in equation should be maintained.
1/(Cb*50kΩ)≤ 1/{Ci*Ri} (3)
As an example , consider a circuit where Cb is
4.7µF , Ci is 1µF and Ri is 130kΩ . Inserting these
values into the equation we get 4.26≤ 7.69 which
satisfies the rule . Bias capacitor , Cb , values of
2.2µF to 10µF ceramic or tantalum low-ESR capacitors are recommended for the best THD and noise
performance.
Output Coupling Capacitor, Cc
In the typical single-supply SE configuration , an output coupling capacitor (Cc) is required to block the
DC bias at the output of the amplifier thus preventing
DC currents in the load . As with the input coupling
capacitor , the output coupling capacitor and impedance of the load form a high-pass filter governed by
equation .
fc(highpass)= 1/(2πR
Cc) (4)
L
For example , a 220µF capacitor with an 32Ω speaker
would attenuate low frequencies below 22Hz . The
main disadvantage , from a performance standpoint,
is the load impedance is typically small , which drives
the low-frequency corner higher degrading the bass
response . Large values of Cc are required to pass
low frequencies into the load .
Optimizing Depop Circuitry
When the amplifier is in mute mode , both of the output stage and input bypass continues to be biased .
And no pop noise will be heard during the transition
out of mute mode .
Power Supply Decoupling , Cs
APA4801 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling
to ensure the output total harmonic distortion (THD)
is as low as possible . Power supply decoupling also
prevents the oscillations causing by long lead length
between the amplifier and the speaker . The optimum
decoupling is achieved by using two different type
capacitors that target on different type of noise on
the power supply leads . For higher frequency transients , spikes , or digital hash on the line , a good
low equivalent-series-resistance (ESR) ceramic capacitor , typically 0.1µF placed as close as possible
to the device V
frequency noise signals , a large aluminum electro-
lead works best . For filtering lower-
DD
lytic capacitor of 10µF or greater placed near the audio
power amplifier is recommended .
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2001
www.anpec.com.tw10
Page 11
APA4801
φ
Packaging Information
PDIP-8 pin ( Reference JEDEC Registration MS-001)
D
E1
1
A
L
e2
e 3
A1
e 1
A2
Millimeters InchesDim
Min. Max. Min. Max.
A
A1
A2
D
e1
e2
e3
E
E1
0.38 0.015
2.92 3.68 0.115 0.145
9.02 10.16 0.355 0.400
2.54BSC 0.100BSC
0.36 0.56 0.014 0.022
1.14 1.78 0.045 0.070
7.62 BSC 0.300 BSC
6.10 7.11 0.240 0.280
E3
L
115
2.92 3.81 0.115 0.150
°
5.33 0.210
10.92 0.430
E
1
E3
15
°
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2001
www.anpec.com.tw11
Page 12
APA4801
φ
Packaging Information
SOP-8 pin ( Reference JEDE C Reg istration MS-012)
HE
e1 e2
D
0.015X45
e
A1
0.004max.
Millime ters InchesDim
Min. Max. Min. Max.
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
D 4.80 5.00 0.189 0.197
E 3.80 4.00 0.150 0.157
H 5.80 6.20 0.228 0.244
L 0.40 1.27 0.016 0.050
e1 0.33 0.51 0.013 0.0 20
e2 1.27BSC 0.50BSC
10
°
8
°
A
1
L
0
°
8
°
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2001
www.anpec.com.tw12
Page 13
APA4801
Physical Specifications
Terminal Material Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb
Lead Solderability Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
Packaging 2500 devices per reel
Reflow Condition (IR/Convection or VPR Reflow)
Reference JEDEC Standard J-STD-020A APRIL 1999
Peak temperature
temperature
Pre-heat temperature
°
183 C
Time
Classificatio n R e flow Profiles
Convection or IR/
Convection
Average ramp-up rate(183°C to Peak) 3°C/second max. 10 °C /second max.
Preheat temperature 125 ± 25°C)
Temperature maintained above 183°C
Time within 5°C of actual peak temperature
Peak temperature range
Ramp-down rate
Time 25°C to peak temperature
120 seconds max
60 – 150 seconds
10 –20 seconds 60 seconds
220 +5/-0°C or 235 +5/-0°C 215-219°C or 235 +5/-0°C
6 °C /second max. 10 °C /second max.
6 minutes max.
VPR
Package Reflow Conditions
pkg. thickness ≥≥≥≥ 2.5mm
and all bgas
Convection 220 +5/-0 °C Convection 235 +5/-0 °C
VPR 215-219 °C VPR 235 +5/-0 °C
IR/Convection 220 +5/-0 °C IR/Convection 235 +5/-0 °C
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2001
pkg. thickness < 2.5mm and
pkg. volume ≥≥≥≥ 350 mm³
pkg. thickness < 2.5mm and p kg .
volume < 350mm³
www.anpec.com.tw13
Page 14
APA4801
Reliability test pro gram
Test item Method Description
SOLDERAB ILITY M IL-STD-8 83D -2 003
HOLT M IL-STD-883D-1005.7
PCT JESD-22-B, A102
TST MIL-STD-8 83D -1 011.9
ESD MIL-STD-883D-3015.7 VHBM > 2KV, VMM > 200V
Latch-Up JESD 78 10ms , Itr > 100mA
Carrier Tape & Reel Dimensions
245°C , 5 SEC
1000 Hrs Bias @ 125 °C
168 Hrs, 100 % RH , 121°C
-65°C ~ 150°C, 200 C ycles
H
B
C
A
L
Application
SOP 8N
AEBCJKFP1D
12 + 0.3
8.0 ± 0.1 1.75± 0.1 5.5± 0.1 1.55± 0.11.5± 0.25 4.0 ± 0.1 2.0 ± 0.1 6.4 ± 0.1
12 - 0.1
Application
SOP 8N
GIHLVWMT1T2
5.2 ±0.1 2.1 ± 0.1 0.3±0.013 330±1100±1
Cover Tape Dimensions
F
E
P1
D
M
J
G
K
T2
W
V
T1
13+0.5
I
2.2±0.1 12.5± 0.5 2.0 ± 0.2
13 -0.1
(mm)
Carrier Width
Cover Tape Width
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2001
12
9.3
(mm)
www.anpec.com.tw14
Page 15
APA4801
Customer Service
Anpec Electronics Corp.
Head Office :
5F, No. 2 Li-Hsin Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
7F, No. 137, Lane 235, Pac Chiao Rd.,
Hsin Tien City, Taipei Hsien, Taiwan, R. O. C.
Tel : 886-2-89191368
Fax : 886-2-89191369
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2001
www.anpec.com.tw15
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