Datasheet APA2030, APA2031 Datasheet (ANPEC)

APA2030/2031

Stereo 2.6W Audio Amplifier(With Gain Control)

Features General Description

••

• Low operating current with 6mA

••

• Improved depop circuitry to eliminate turn-on

••

transients in outputs

••

• High PSRR

••

• Internal gain control, eliminate external components.

••

• 2.6W per channel output power into 3Ω load at 5V,

••

BTL mode

••

• Multiple input modes allowable selected by HP

••

/LINE pin (APA2030)

••

• Two output modes allowable with BTL and SE

••

modes selected by SE/BTL pin (for APA2030 only)

••

• Low current consumption in shutdown mode (50µ

••

A)

••

• Short Circuit Protection

••

• TSSOP-24-P (APA2030) and TSSOP-20-P

••

(APA2031) with thermal pad package.

Applications

••

• NoteBook PC

••

• LCD Monitor

••

APA2030/1 is a monolithic integrated circuit, which

provides internal gain control, and a stereo bridged

audio power amplifiers capable of producing 2.6W

(1.9W) into 3Ω with less than 10% (1.0%) THD+N.

By control the two gain setting pins, Gain0 and Gain1,

The amplifier can provide 6dB, 10dB, 15.6dB, and

21.6dB gain settings. The advantage of internal gain

setting can be less components and PCB area. Both

of the depop circuitry and the thermal shutdown pro-

tection circuitry are integrated in APA2030/1, that

reduces pops and clicks noise during power up or

shutdown mode operation. It also improved the power

off pop noise and protects the chip from being de-

stroyed by over temperature and short current failure.

To simplify the audio system design APA2030 com-

bines a stereo bridge-tied loads (BTL) mode for

speaker drive and a stereo single-end (SE) mode for

headphone drive into a single chip, where both modes

are easily switched by the SE/BTL input control pin

signal. Besides the multiple input selections is used

for portable audio system. APA2031 eliminates both

input selection and single-end (SE) mode function to

simplifying the design and save the PCB space.

Ordering and Marking Information

APA2030/1

Lead Free Code

Handling Code

Temp. Range

Package Code

APA2030/1 R :

ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders.

Copyright  ANPEC Electronics Corp. Rev. A.2 -Apr., 2004

APA2030/1 XXXXX

Package Code R : TSSOP-P * Temp. Range I : - 40 to 85 C Handling Code TU : Tu be TR : Tape & R eel TY : Tra y Lead Free Code L : Lead Free Device Blank : O riginal Device

XXXXX - Date Code

°

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APA2030/2031

Pin Assignment

GND 1

GA IN0 2

LOUT+ 4

LLINEIN 5

LHPIN 6

PVDD 7

RIN+ 8

LOUT- 9

LIN+ 10

BYPASS 11

GND 12

TOP View (APA2030)

Block Diagram

LLINEIN

LHPIN

LIN+

BYPASS

AP A 2030_P i nOut

24 GND

23 RLINEIN

22 SHUTDOWNGA IN1 3

21 ROUT+

20 RHPIN

19 V

18 PV

17 HP/LINE

16 ROUT-

15 SE/BTL

14 PCB EEP

13 GND

MUX

DD

GND 1

GAIN0 2

LOUT+ 4

LIN- 5

6

PV

DD

LOUT- 8

LIN+ 9

BYPA SS 10

Vbias

TOP View

(APA2031)

LOUT+

20 GND

19 SHUTDO WN

18 ROUT+GAIN1 3

17 RIN-

16 V

DD

15 PV

DD

14 ROUT-RIN+ 7

13 GND

12 NC

11 GND

GAIN0

GIAN1

RLINEIN

RHPIN

RIN+

HP/LINE

SE/BTL

SHUTDO W N

PCB EEP

Copyright  ANPEC Electronics Corp. Rev. A.2 - Apr., 2004

Gain

selectable

MUX

H P/L INE

SE/BTL

Shutdown

ckt

PC- BEEP

ckt

LOUT-

ROUT+

Vbias

ROUT-

AP A2030_B lock

APA2030

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APA2030/2031

Block Diagram

LIN-

LIN+

BYPASS

SHUTDOW N

GAIN0

GAIN1

RIN-

RIN+

Shu tdo wn

ckt

Gain

selectab le

LOUT+

Vbias

LOUT-

ROUT+

Vbias

ROUT-

APA2031_Block

APA2031

Absolute Maximum Ratings

(Over operating free-air temperature range unless otherwise noted.)

Parameter Rating

Supply voltage range, VDD, PVDD -0.3V to 6V Input voltage range at SE/BTL, HP/LINE, SHUTDOWN, -0.3V to VDD

Operating ambient temperature range, TA -40°C to 85°C Maximum junction temperature, TJ Internal Limited

ESD

STG

-65°C to 150°C

-3000 to 3000*1

-200 to 200*2

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Storage temperature range, T Soldering Temperature, 10 seconds, TS 260°C

Electrostatic Discharge, V

Power dissipation, PD Internal Limited

Note:

*1. Human body model: C=100pF, R=1500Ω, 3 positives pulse plus 3 negative pulses

*2. Machine model: C=200pF, L=0.5mH, 3 positive pulses plus 3 negative pulses

Copyright  ANPEC Electronics Corp. Rev. A.2 - Apr., 2004

APA2030/2031

Recommended Operating Conditions

Supply Voltage, VDD………………………………………………………………………….…………..4.5V to 5.5V

Thermal Characteristics

Symbol Parameter Value Unit

Thermal Resistance from Junction to Ambient in Free Air

R

* 5 in2 printed circuit board with 2oz trace and copper pad through 9 25mil diameter vias.

The thermal pad on the TSSOP_P package with solder on the printed circuit board.

THJA

TSSOP-P24* TSSOP-P20*

Electrical Characteristics

(VDD=5V,-20°C<TA<85°C, unless otherwise noted.)

45 48

°C/W

Symbol Parameter Test Condition Min. Typ. Max. Unit

VDD Supply Voltage

IDD Supply current

Supply current in shutdown

ISD

mode

VIH High level threshold Voltage

VIL Low level threshold Voltage

II Input current

ICM

V

Common mode Input voltage

VOS Output differential voltage

PC_beep trigger level

SE/BTL = 0V 6 12 mA

SE/BTL = 5V

SHUTDOWN = 0V 50 300

SHUTDOWN, GAIN0, GAIN1 2 V

SE/BTL, HP/LINE SHUTDOWN, GAIN0, GAIN1 0.8 V

SE/BTL, HP/LINE 3 V

SHUTDOWN, SE/BTL, HP/LINE, GAIN0, GAIN1

3.3 5.5 V

4 8 mA

µA

4 V

5 nA

VDD-1.0 V

5 mV

1 Vp.p

Copyright  ANPEC Electronics Corp. Rev. A.2 - Apr., 2004

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APA2030/2031

Electical Characteristics (Cont.)

Operating Characteristics, BTL mode

Vdd=5V, T

A=25°C, Rl=4

ΩΩ

, Gain=6dB, (Unless otherwise noted)

Ω

ΩΩ

Symbol Parameter Test Condition

THD=10%, Fin=1khz, RL=3Ω

THD=10%, Fin=1khz, RL=4Ω

PO Maximum output power

THD=10%, Fin=1khz, RL=8Ω

THD=1%, Fin=1khz, RL=3Ω

THD=1%, Fin=1khz, RL=4Ω

in

=1khz, RL=8Ω

THD+N

Total harmonic distortion plus noise

PSRR Power ripple rejection ratio

xtalk Channel separation

HP/LINE input separation

S/N Signal to noise ratio

THD=1%, F

Po=1.1W, RL=4Ω Fin=1khz

Po=0.7W, RL=8Ω, Fin=1khz

Vin=0.2Vrms, Rl=8Ω, Cb=0.47µf, f=120Hz

f=1khz, Cb=0.47µf,

Po=1.1W, Rl=8Ω , A_weight

Operating Characteristics, SE mode ( for APA2030 only)

Vdd=5V, T

A=25°C, Rl=32

ΩΩ

Ω, Gain=4, 1dB, (Unless otherwise noted)

ΩΩ

Min. Typ. Max. Unit

2.6 W

2.3 W

1.5 W

1.9 W

1.7 W

1 1.1 W

0.05 %

0.04 %

85 dB

95 dB

80 dB

105 dB

Symbol Parameter Test Condition Min. Typ. Max. Unit

P

THD+N

Maximum output power

O

Total harmonic distortion plus noise

PSRR Power ripple rejection ratio

THD=10%, Fin=1khz, RL=32Ω

THD=1%, Fin=1khz, RL=32Ω

Po=75mW, RL=32Ω .Fin=1khz

Vin=0.2Vrms, Rl=32Ω, Cb=0.47µf, f=120,

110 mW

90 mW

0.03 %

55 dB

SE/BTL attenuation 80 dB

xtalk Channel separation

HP/LINE input separation

S/N Signal to noise ratio

Copyright  ANPEC Electronics Corp. Rev. A.2 - Apr., 2004

f=1khz, Cb=0.47µf,

f=1khz, Cb=0.47µf, BTL

Po=75mW, Rl=32Ω, A_weight,

65 dB

80 dB

100 dB

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APA2030/2031

Pin Descriptions

APA2030

Pin name

GND

GAIN0 2 I/P GAIN1 3 I/P

LOUT+ 4 O/P LLINEIN 5 I/P RLIN EIN 23 I/P

LHPIN 6 O/P

PVDD

RIN+ 8 I/P

LOUT- 9 O/P

LIN+ 10 I/P

BYPASS 11 -

PCBEEP 14 I/P PC-beep signal input

SE/BTL

ROUT- 16 O/P

HP/LINE 17 I/P

VDD 19 -

RHPIN 20 I/P

ROUT+ 21 O/P

SHUTDOWN

RLINEIN

APA2031

Pin name

GND

GAIN0 2 I/P GAIN1 3 I/P

LOUT+ 4 O/P

LIN- 5 I/P

PVDD 6,15 -

RIN+ 7 I/P

LOUT- 8 O/P

LIN+ 9 I/P

BYPASS 10 -

NC 12 -

ROUT- 14 O/P

VDD 16 -

Copyright  ANPEC Electronics Corp. Rev. A.2 - Apr., 2004

Config. Function Description

no.

1, 12, 13,

24

7,

18

15 I/P

22 I/P 23 I/P

Config. Function Description

no.

1, 11,

13, 20

- Ground connection, Connected to thermal pad.

Input signal for internal gain setting Input signal for internal gain setting Left channel positive output in BTL mode and SE mode Left channel line input terminal, selected when HP/LINE is held low. Right channel line input terminal, selected when HP/LINE is held low. Left channel headphone input terminal, selected when HP/LINE is held high.

- Supply voltage only for power amplifier

Right channel positive signal input, when differential signal is accepted. Left channel negative output in BTL mode and high impedance in SE mode Left channel positive signal input, when differential signal is accepted. Bypass voltage

Output mode control input pin, high for SE output mode and low for BTL mode Right channel negative output in BTL mode and high impedance in SE mode Multi-input selection input, headphone mode when held high, line-in mode when held low

Supply voltage for internal circuit excepting power amplifier. Right channel headphone input terminal, selected when HP/LINE is held high. Right channel positive output in BTL mode and SE mode

It will be into shutdown m od e when pull low Right channel line input terminal, selected when HP/LINE is held low

- Ground connection, Connected to thermal pad.

Input signal for internal gain setting Input signal for internal gain setting Left channel positive output Left channel negative audio signal input Supply voltage only for power amplifier Right channel positive audio signal input Left channel negative output Left channel positive audio signal input Bypass voltage No connection Right channel negative output Supply voltage for internal circuit excepting power amplifier

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APA2030/2031

Pin Description

APA2031

Pin name

RIN+ 17 I/P

ROUT+ 18 O/P

SHUTDOWN

Config. Function Description

no.

Right channel negative audio signal input Right channel positive output

19 I/P It will be into shutdown mode when pull low

Control Input Table ( for APA2030 only)

HP/ LINE

X

L

H

L H X

SE/BTL

X L Disable Shutdown mode L H Disable Line input, BTL out L H Disable HP input, BTL out H H Disable Line input, SE out H H Disable HP input, SE out X X Enable PCBEEP input, BTL out

SHUTDOWN

PCBEEP Operating mode

Gain Setting Table (for both APA2030 and APA2031)

GAIN0 GAIN1 Ri Rf Av

0 0

0 1

1 0

1 1

25.7KΩ 154.3KΩ

90KΩ 90KΩ

69KΩ 111KΩ

42KΩ 138KΩ

6dB

10dB

15.6dB

21.6dB

Copyright  ANPEC Electronics Corp. Rev. A.2 - Apr., 2004

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APA2030/2031

Typical Application Circuit

(f

(for APA2030 using SE input signal)

L-LI NE

R-L INE

HP/LINE

Control Signal

SE/BTL Si gnal

L-HP

R-HP

0.47µF

100k

Ω

0.47µF

VDD

100kΩ

LLINEIN

LHPIN

LIN+

BYPASS

GAI N0

GAI N1

RLI NEI N

RHPI N

RIN+

HP/LINE

SE/BTL

DD

V

MUX

Gai n

selectable

MUX

HP/L INE

SE/BTL

VDD

0.1µF

GND

0Ω

100µF

PV

DD

Vbia s

LOUT+

LOUT-

ROUT+

4

4Ω

220µF

Ω

SE/BTL Signal

220µF

1kΩ

Cont r ol

1kΩ

Ri ng

Tip

Headphone

Jack

Sle eve

Shutdown Signal

BEEP Signal

SHUTDOWN

PCBEEP

0.47µF

Copyright  ANPEC Electronics Corp. Rev. A.2 - Apr., 2004

Shutdown

ckt

PC-BEEP

ckt

ROUT-

APA2030AppCkt

APA 2030

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APA2030/2031

Typical Application Circuit

(for APA2031 using SE input signal)

L-INPUT

R-INPUT

0.47µF

LIN-

LIN+

BYPASS

GAIN0

GAIN1

RIN-

RIN+

VDD

µ

0.1

VDD PVDDGND

Gain

selectable

Ω

0

F

100

µ

F

LOUT+

Vbias

Ω

4

LOUT-

ROUT +

Vbias

Ω

4

Shutdown

Signal

SHUTDOWN

Copyright  ANPEC Electronics Corp. Rev. A.2 - Apr., 2004

Shutdown

ckt

ROUT -

APA 2031

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APA2030/2031

Typical Characteristics

10

VDD=5V A

V=6dB

f=1kHz BTL

1

THD+N (%)

0.1

0.01 0

10

1

THD+N vs. Output Power

RL=8Ω

RL=4Ω

11.52

Output Power (W)

VDD=5V AV=6dB RL=3Ω BTL

f=15kHz

RL=3Ω

2.5

THD+N vs. Output Power

10

VDD=5V

V=4.1dB

A f=1kHz C

OUT=330µF

SE

1

THD+N (%)

0.1

30.5

0.01 025050 100 150 200

RL=32Ω

RL=16Ω

Output Power (mW)

THD+N vs. Output PowerTHD+N vs. Output Power

10

f=15kHz

1

THD+N (%)

0.1

f=1kHz

f=30Hz

0.01 10m 5100m 1

Output Power (W) Output Power (W)

Copyright  ANPEC Electronics Corp. Rev. A.2 - Apr., 2004

f=1kHz

0.1

THD+N (%)

f=30Hz VDD=5V AV=15.6dB RL=3Ω BTL

0.01

10m 5100m 1 2

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APA2030/2031

Typical Characteristics (Cont.)

THD+N vs. Output Power

10

VDD=5V

V=6dB

A RL=4Ω BTL

1

THD+N (%)

0.1

f=15kHz

f=1kHz

f=30Hz

0.0 1

10m 5100m 1 2

Output Power (W) Output Power (W)

THD+N vs. Output Power

10

VDD=5V AV=6dB RL=8Ω BTL

1

f=15kHz

THD+N vs. Output Power

10

f=15kHz

1

f=1kHz

0.1

THD+N (%)

VDD=5V AV=15.6dB

f=30Hz

RL=4Ω BTL

0.01 10m 5100m 1 2

THD+N vs. Frequency

10

VDD=5V AV=15.6dB RL=8Ω BTL

1

f=15kHz

THD+N (%)

0.1

f=1kHz

f=30Hz

0.01 10m 5100m 1 2

Output Power (W)

Copyright  ANPEC Electronics Corp. Rev. A.2 - Apr., 2004

f=30Hz

THD+N (%)

0.1

f=1kHz

0.01 10m 5100m 1 2

Output Power (W)

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APA2030/2031

Typical Characteristics (Cont.)

10

VDD=5V AV=4dB RL=16Ω COUT=1000µF SE

1

THD+N (%)

0.1

0.01 10m

THD+N vs. Output Power

f=30Hz

10

1

THD+N vs. Output Power

VDD=5V

V=4.1dB

A R

L=32Ω

COUT=1000µF SE

f=15kHz

THD+N (%)

0.1

f=30Hz

f=1kHz

300m50m 100m 200m

0.01 10m 300m50m 100m 200m

f=1kHz

Output Power (W) Output Power (W)

THD+N vs. Frequency

10

VDD=5V AV=6dB RL=3Ω BTL

1

PO=1.75W

THD+N (%)

0.1

0.01 20 20k100 1k 10k

Frequency (Hz) Frequency (Hz)

Copyright  ANPEC Electronics Corp. Rev. A.2 - Apr., 2004

PO=1W

THD+N vs. Frequency

10

VDD=5V PO=1.75W RL=3Ω BTL

1

AV=15.6dB

THD+N (%)

0.1

0.01 20 20k100 1k 10k

AV=6dB

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APA2030/2031

Typical Characteristics (Cont.)

THD+N vs. Frequency

10

VDD=5V AV=6dB

L=4Ω

R BTL

1

PO=1.5W

0.1

THD+N (%)

0.01 20 20k100 1k 10k

Frequency (Hz) Frequency (Hz)

THD+N vs. Frequency

10

VDD=5V AV=6dB RL=8Ω BTL

1

PO=0.75W

THD+N vs. Frequency

10

VDD=5V PO=1.5W RL=4Ω BTL

1

AV=15.6dB

0.1

THD+N (%)

0.01 20 20k100 1k 10k

AV=6dB

THD+N vs. Frequency

10

VDD=5V PO=1W RL=8Ω BTL

1

PO=1W

THD+N (%)

0.1

PO=0.5W

0.01 20

100 1k 10k

Frequency (Hz)

Copyright  ANPEC Electronics Corp. Rev. A.2 - Apr., 2004

20k

AV=6dB

THD+N (%)

0.1

AV=15.6dB

0.01 20 20k100 1k 10k

Frequency (Hz)

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APA2030/2031

Typical Characteristics (Cont.)

THD+N vs. Frequency

10

VDD=5V

V=4.1dB

A RL=16Ω C

OUT=1000µF

SE

1

THD+N (%)

0.1

PO=75mW

PO=150mW

0.01 20

Frequency Response

+6

+4

+2

-0

-2

Gain (dB)

-4

VDD=5V

-6

RL=4Ω AV=6dB

-8

PO=1W

Gain

Phase

BTL

-10 10 200k100 1k 10k 100k

Frequency (Hz) Frequency (Hz)

20k100 1k 10k

+240

+230

+220

+210

+200

+190

+180

+170

+160

Phase (Degress)

+150

+140

+130

+120

THD+N vs. Frequency

10

VDD=5V AV=4.1dB RL=32Ω COUT=1000µF SE

1

THD+N (%)

0.1

PO=25mW

PO=75mW

0.01 20 20k100 1k 10k

Frequency (Hz)Frequency (Hz)

Frequency Response

+20

+18

+16

+14

+12

+10

+8

Gain (dB)

+6

VDD=5V RL=4Ω

+4

AV=15.6dB PO=1W

+2

BTL

-0 10 200k100 1k 10k 100k

Gain

Phase

+270

+260

+250

+240

+230

+220

+210

+200

+190

+180

+170

Phase (Degress)

+160

+150

+140

+130

+120

Copyright  ANPEC Electronics Corp. Rev. A.2 - Apr., 2004

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APA2030/2031

Typical Characteristics (Cont.)

Frequency Response

+10

+9

+8

+7

+6

+5

+4

Gain (dB)

+3

VDD=5V RL=8Ω

+2

AV=10dB PO=0.5W

+1

BTL

-0 10 200k100 1k 10k 100k

Gain

Phase

Frequency (Hz)

Crosstalk vs. Frequency

+0

666666666666

VDD=5V RL=4Ω

-20

AV=6dB PO=1.5W SE

-40

-60

-80

Crosstalk (dB)

-100

-120

Left to Right

Right to Left

+270

+260

+250

+240

+230

+220

+210

+200

+190

+180

+170

Phase (Degress)

+160

+150

+140

+130

+120

Frequency Response

+5

+4

+3

+2

+1

+0

-1

Gain (dB)

-2

VDD=5V RL=32Ω

-3

AV=4.1dB VIN=1V

-4

SE

-5 10 200k100 1k 10k 100k

Gain

Phase

Frequency (Hz)

Crosstalk vs. Frequency

+0

VDD=5V

-10

RL=32Ω AV=4.1dB

-20

VIN=1V COUT=330µF

-30

SE

-40

-50

-60

-70

Crosstalk (dB)

-80

-90

Left to Right

Right to Left

+300

+280

+260

+240

+220

+200

+180

+160

Phase (Degress)

+140

+120

+100

-140 20 20k100 1k 10k

Frequency (Hz) Frequency (Hz)

Copyright  ANPEC Electronics Corp. Rev. A.2 - Apr., 2004

-100 20 20k100 1k 10k

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APA2030/2031

Typical Characteristics (Cont.)

PSRR vs. Frequency

+0

VDD=5V

-10

L=4Ω

R C

B=0.47µF

-20

BTL

-30

-40

-50

-60

PSRR (dB)

-70

-80

-90

-100 20 20k100 1k 10k

Frequency (Hz)

Output Noise Voltage vs. Frequency

100

PSRR vs. Frequency

+0

VDD=5V

-10

R

L=32Ω

CB=0.47µF

-20

SE

-30

-40

-50

-60

PSRR (dB)

-70

-80

-90

-100 20 20k100 1k 10k

Frequency (Hz)

Output Noise Voltage vs. Frequency

100

50

Filter BW < 22kHz

20

10

A-Weight

5

VDD=5V RL=4Ω

2

AV=6dB

Output Noise Voltage (µV)

BTL

1

20 20k100 1k 10k

Frequency (Hz)

Copyright  ANPEC Electronics Corp. Rev. A.2 - Apr., 2004

50

Filter BW < 22kHz

µV)

20

10

5

VDD=5V RL=32Ω

2

AV=4.1dB

Output Noise Voltage (

SE

1

20 20k100 1k 10k

A-Weight

Frequency (Hz)

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APA2030/2031

Typical Characteristics (Cont.)

Supply Current vs. Supply Voltage

7

No Load

6

5

4

3

2

Supply Current (mA)

1

0

3.0 3.5 4.0 4.5 5.0 5.5 6.0

Supply Voltage (V)

Power Dissipation vs. Output Power

200

VDD=5V

180

SE

160

140

120

100

80

60

40

Power Dissipation (mW)

20

0

0 50 100 150 200 250 300

RL=32Ω

RL=16Ω

RL=8Ω

Output Power (mW)

BTL

SE

Power Dissipation vs. Output Power

2.0

VDD=5V

1.8

BTL

1.6

1.4

1.2

1.0

0.8

0.6

0.4

Power Dissipation (W)

0.2

0.0

0.0 0.5 1.0 1.5 2.0 2.5

RL=8Ω

RL=4Ω

Output Power (W)

RL=3Ω

Copyright  ANPEC Electronics Corp. Rev. A.2 - Apr., 2004

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APA2030/2031

Application Descriptions

BTL Operation

The APA2030/1 has two pairs of operational amplifiers internally, allowed for different amplifier configurations.

INP UT -

INP UT +

-

+

OP1

V

-

+

bias

OP2

OUT+

DIF F _A MP _C ON F IG

OUT-

Figure 1: APA2030 internal configuration (each

channel)

The OP1 and OP2 are all differential drive configuration, The differential drive configuration doubling the voltage swing on the load compare to the single-ending configuration, the differential gain for each channel is 2

X(Gain of SE mode).

By driving the load differentially through outputs OUT+ and OUT-, an amplifier configuration commonly referred to as bridged mode is established. BTL mode operation is different from the classical single-ended SE amplifier configuration where one side of its load is connected to ground.

A BTL amplifier design has a few distinct advantages over the SE configuration, as it provides differential drive to the load, thus doubling the output swing for a specified supply voltage. Four times the output power is possible as compared to a SE amplifier under the same conditions. A BTL configuration, such as the one used in APA2030/1, also creates a second advantage over SE amplifiers. Since the differential outputs, ROUT+, ROUT-, LOUT+, and LOUT-, are biased at half-supply, no need DC voltage exists across the load. This eliminates the need for an output coupling capacitor which is required in a single supply, SE configuration.

Single-Ended Operation (for APA2030 only)

Consider the single-supply SE configuration shown Application Circuit. A coupling capacitor is required to block the DC offset voltage from reaching the load. These capacitors can be quite large (approximately

33µF to 1000µF) so they tend to be expensive, occupy valuable PCB area, and have the additional drawback of limiting low-frequency performance of the system (refer to the Output Coupling Capacitor).

The rules described should be following relationship:

1

≤

Ω×125k Cbypass

CR

1

<<

ii

(1)

CR

L

C

Output SE/BTL Operation (for APA2030 only)

The ability of the APA2030 to easily switch between BTL and SE modes is one of its most important costs saving features. This feature eliminates the requirement for an additional headphone amplifier in applications where internal stereo speakers are driven in BTL mode but external headphone or speakers must be accommodated.

Internal to the APA2030, two separate amplifiers drive OUT+ and OUT- (see Figure 1). The SE/BTL input controls the operation of the follower amplifier that drives LOUT- and ROUT-.

••

• When SE/BTL is held low, the OP2 is actived

••

and the APA2030 is in the BTL mode.

••

• When SE/BTL is held high, the OP2 is in a high

••

output impedance state, which configures the APA2030 as SE driver from OUT+. IDD is reduced by approximately one-half in SE mode.

Control of the SE/BTL input can be a logic-level TTL source or a resistor divider network or the stereo headphone jack with switch pin as shown in Application Circuit.

Copyright  ANPEC Electronics Corp. Rev. A.2 - Apr., 2004

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APA2030/2031

Application Descriptions

SE/BTL

100K

Vdd

Ω

100K

1K

Ω

Control

SE/BT L_ S w i tc h

Ring

Sleeve

Tip

Headphone Jack

Figure 2: SE/BTL input selection by phonejack plug

In Figure 2, input SE/BTL operates as follows:

When the phonejack plug is inserted, the 1kΩ resistor is disconnected and the SE/BTL input is pulled high and enables the SE mode. When the input goes high level, the OUT- amplifier is shutdown causing the speaker to mute. The OUT+ amplifier then drives through the output capacitor (CO) into the headphone jack.

When there is no headphone plugged into the system, the contact pin of the headphone jack is connected from the signal pin, the voltage divider set up by resistors 100kΩ and 1kΩ. Resistor 1kΩ then pulls low the SE/BTL pin, enabling the BTL function.

Input HP/LINE Operation (for APA2030 only)

the HP/LINE pin, enabling the headphone input function.

Differential Input Operation

APA2030/1 can accepted the differential input signal,

and it’s can improve the CMRR (Common Mode Re-

jection ratio). For example: when apply differential in-

put signals to APA2031, connect positive input sig-

nals to the IN+ (LIN+ and RIN+) of APA2031 and nega-

tive input signals to the IN- (LIN- and RIN-) of APA2031.

When input signals are single-end, just connect IN+

(LIN+ and RIN+) to ground via a capacitor.

Input Resistance, Ri

The APA2030/1 provides four gain setting decided by

GAIN0 and GAIN1 input ins in Differential mode and it

become 4.1dB fixed gain when SE mode is selected

(for APA2030). In table 1,internal resistors Ri and Rf

according to BTL operation set the gain for each au-

dio input of the APA2030/1.

GAIN0 GAIN1 Ri Rf SE/BTL Av

0 0 90KΩ 90KΩ 0 6dB

APA2030 amplifier has two separate inputs for each of the left and right stereo channels. An internal multiplexer selects which input will be connected to the amplifier based on the state of the HP/LINE pin on the IC.

••

• To select the line inputs, set HP/LINE pin tied to

••

low level

••

• To enable the headphone inputs, set HP/ LINE

••

pin tied to high level

Refer to the application circuit, the voltage divider of 100kΩ and 1kΩ sets the voltage at the HP/LINE pin

to be approximately 50mV when there are no headphones plugged into the system. This logic low voltage at the HP/LINE pin enables the APA2030 and places it LINE input mode operation.

When a set of headphones is plugged into the system, the contact pin of the headphone jack is disconnected from the signal pin, interrupting the voltage divider set

up by resistors 100kΩ. Resistor 100kΩ then pulls-up

Copyright  ANPEC Electronics Corp. Rev. A.2 - Apr., 2004

0 1 69KΩ 111KΩ 0 10dB

1 0 42KΩ 138KΩ 0 15.6dB

1 1 25.7KΩ 154.3KΩ 0 21.6dB

X X 69KΩ 111KΩ 1 4.1dB

Table 1: The close loop gain setting resistance Ri/Rf

BTL mode operation brings about the factor 2 in the gain equation due to the inverting amplifier mirroring

the voltage swing across the load. The input resis-

tance has wide variation (+/-10%) caused by

manufacture.

Input Capacitor, Ci

In the typical application an input capacitor, Ci, is required to allow the amplifier to bias the input signal to the proper DC level for optimum operation. In this case, Ci and the minimum input impedance Ri form a high-pass filter with the corner frequency determined in the follow equation:

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APA2030/2031

Application Descriptions

(highpass)= (2)

f

C

1

CiRimin2

×π

The value of Ci is important to consider as it directly affects the low frequency performance of the circuit.

Consider the example where Ri is 90kΩ when 6dB gain is setting and the specification calls for a flat

bass response down to 40Hz . Equation is reconfigured as follow:

Ci= (3)

Rifc21π

Consider to input resistance variation, the Ci is 0.04µF so one would likely choose a value in the range of

0.1µF to 1.0µF.

A further consideration for this capacitor is the leakage path from the input source through the input network (Ri+Rf, Ci) to the load. This leakage current creates a DC offset voltage at the input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications as the DC level there is held at V

DD

/2, which is likely higher that the source DC level. Please note that it is important to confirm the capacitor polarity in the application.

Effective Bypass Capacitor, Cbypass

To avoid start-up pop noise occurred, the bypass voltage should be rise slower then the input bias voltage and the relationship shown in equation should be maintained.

1

<<

×

125kȍCbypass

ȍ 180kCi1×

(4)

The capacitor is fed from a 125kΩ source inside the

amplifier. Bypass capacitor, Cb, values of 3.3µF to

10µF ceramic or tantalum low-ESR capacitors are recommended for the best THD and noise performance.

The bypass capacitance also effect to the start up time. It is determined in the follow equation:

Tstart up =5x(Cbypassx125kΩ) (5)

Output Coupling Capacitor, Cc (for APA2030 only)

In the typical single-supply SE configuration, an output coupling capacitor (Cc) is required to block the DC bias at the output of the amplifier thus preventing DC currents in the load. As with the input coupling capacitor, the output coupling capacitor and impedance of the load form a high-pass filter governed by equation.

1

fc(highpass)=

π

(6)

CL

CR2

As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply rejection.

The capacitor location on both the bypass and power supply pins should be as close to the device as possible. The effect of a larger half supply bypass capacitor is improved PSRR due to increased halfsupply stability. Typical applications employ a 5V regu-

lator with 1.0µF and a 0.1µF bypass capacitors which aid in supply filtering. This does not eliminate the need for bypassing the supply nodes of the APA2030/1. The selection of bypass capacitors, especially Cb, is thus dependent upon desired PSRR requirements, click and pop performance.

Copyright  ANPEC Electronics Corp. Rev. A.2 - Apr., 2004

For example, a 330µF capacitor with an 8Ω speaker would attenuate low frequencies below 60.6Hz. The

main disadvantage, from a performance standpoint, is the load impedance is typically small, which drives the low-frequency corner higher degrading the bass response. Large values of CC are required to pass low frequencies into the load.

Power Supply Decoupling, Cs

The APA2030/1 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD) is as low as possible.

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APA2030/2031

Application Descriptions

Power supply decoupling also prevents the oscillations causing by long lead length between the amplifier and the speaker. The optimum decoupling is achieved by using two different type capacitors that target on different type of noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance(ESR) ceramic

capacitor, typically 0.1µF placed as close as possible to the device VDD lead works best. For filtering lowerfrequency noise signals, a large aluminum electrolytic

capacitor of 10µF or greater placed near the audio power amplifier is recommended.

Shutdown Function

In order to reduce power consumption while not in use, the APA2030/1 contains a shutdown pin to externally turn off the amplifier bias circuitry. This shutdown feature turns the amplifier off when a logic low is placed on the SHUTDOWN pin. The trigger point between a logic high and logic low level is typically 2.0V. It is best to switch between ground and the supply VDD to provide maximum device performance.

By switching the SHUTDOWN pin to low, the amplifier enters a low-current state, IDD<50µA. APA2030 is in

shutdown mode, except PC-BEEP detect circuit. On normal operating, SHUTDOWN pin pull to high level to keeping the IC out of the shutdown mode. The SHUTDOWN pin should be tied to a definite voltage to avoid unwanted state changes.

PC-BEEP Detection ( for APA2030 only)

APA2030 integrates a PCBEEP detect circuit for NOTEBOOK PC used. When PC-BEEP signal drive to PCBEEP input pin, and PCBEEP mode is active. APA2030 will force to BTL mode and the internal gain fixed as -10dB. The PCBEEP signal becomes the amplifier input signal and play on the speaker without coupling capacitor. If the amplifier in the shutdown mode, it will out of shutdown mode whenever PCBEEP mode enable. The APA2030 will return to previous setting when it is out of PC-BEEP mode.

The input impedance is 100kΩ on PCBEEP input pin.

Copyright  ANPEC Electronics Corp. Rev. A.2 - Apr., 2004

Optimizing Depop Circuitry

Circuitry has been included in the APA2030/1 to minimize the amount of popping noise at power-up and when coming out of shutdown mode. Popping occurs whenever a voltage step is applied to the speaker. In order to eliminate clicks and pops, all capacitors must be fully discharged before turn-on. Rapid on/off switching of the device or the shutdown function will cause the click and pop circuitry. The value of Ci will also affect turn-on pops. (Refer to Effective Bypass Capacitance) The bypass voltage rise up should be slower than input bias voltage. Although the bypass pin current source cannot be modified, the size of Cb can be changed to alter the device turn-on time and the amount of clicks and pops. By increasing the value of Cb, turn-on pop can be reduced. However, the tradeoff for using a larger bypass capacitor is to increase the turn-on time for this device. There is a linear relationship between the size of Cb and the turn-on time.

In a SE(for APA2030) configuration, the output coupling capacitor, CC, is of particular concern. This ca-

pacitor discharges through the internal 10kΩ resistors. Depending on the size of CC, the time constant can be relatively large. To reduce transients in SE mode,

an external 1kΩ resistor can be placed in parallel

with the internal 10kΩ resistor. The tradeoff for using this resistor is an increase in quiescent current.

In the most cases, choosing a small value of Ci in the range of 0.33µF to 1µF, Cb being equal to 0.47µF and

an external 1kΩ resistor should be placed in parallel

with the internal 10kΩ resistor should produce a virtually clickless and popless turn-on.

A high gain amplifier intensifies the problem as the small delta in voltage is multiplied by the gain. So it

is advantageous to use low-gain configurations.

BTL Amplifier Efficiency

An easy-to-use equation to calculate efficiency starts out as being equal to the ratio of power from the power supply to the power delivered to the load. The following equations are the basis for calculating amplifier efficiency.

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APA2030/2031

Application Descriptions

O

P

Efficiency = (7)

SUP

P

Where:

×

OO

PO = =

rmsVrmsV

L

R

P

V

2R

×

PP

VV

L

VOrms = (8)

2

P

Psup = V

DD

* I

AVG =

DD

2V

π

L

R

Efficiency of a BTL configuration:

O

P

= (

SUP

P

×

PP

VV

2R

) / (V

L

DD

2V

x

π

R

π

P

) =

L

4V

P

V

DD

(10)

Table 2 calculates efficiencies for four different output power levels. Note that the efficiency of the amplifier is quite low for lower power levels and rises sharply as power to the load is increased resulting in a nearly flat internal power dissipation over the normal operating range. Note that the internal dissipation at full output power is less than in the half power range. Calculating the efficiency for a specific system is the key to proper power supply design. For a stereo 1W audio system

with 8Ω loads and a 5V supply, the maximum draw

on the power supply is almost 3W.

Po (W) Efficiency (%) IDD(A) VPP(V) PD (W)

0.25 31.25 0.16 2.00 0.55

0.50 47.62 0.21 2.83 0.55

1.00 66.67 0.30 4.00 0.5

1.25 78.13 0.32 4.47 0.35

**High peak voltages cause the THD to increase.

Table 2. Efficiency Vs Output Power in 5V/8Ω BTL

Systems

A final point to remember about linear amplifiers (either SE or BTL) is how to manipulate the terms in the efficiency equation to utmost advantage whenpossible. Note that in equation, VDD is in the dominator. This indicates that as VDD goes down,efficiency goes up. In other words, use the efficiency analysis to choose the correct supply voltage and speaker impedance for the application.

Power Dissipation

Whether the power amplifier is operated in BTL or SE modes, power dissipation is a major concern. In equation11 states the maximum power dissipation point for a SE mode operating at a given supply voltage and driving a specified load.

2

DD

SE mode : PD,MAX =

V

(11)

2

L

π

R2

In BTL mode operation, the output voltage swing is doubled as in SE mode. Thus the maximum power dissipation point for a BTL mode operating at the same given conditions is 4 times as in SE mode.

2

4V

BTL mode : P

D,MAX

DD

= (12)

2

R2

L

ʌ

Since the APA2030/1 is a dual channel power amplifier, the maximum internal power dissipation is 2 times that both of equations depending on the mode of operation. Even with this substantial increase in power dissipation, the APA2030/1 does not require extra heatsink. The power dissipation from equation12,

assuming a 5V-power supply and an 8Ω load, must not be greater than the power dissipation that results

from the equation13:

AJ.MAX

−

PD,MAX = (13)

TT

θ

JA

For TSSOP-24 (APA2030) and TSSOP-20 (APA2031) package with and without thermal pad, the thermal resistance (θJA) is equal to 45oC/W and 48oC/W, respectively.

Since the maximum junction temperature (T

J,MAX

) of APA2030/1 is 150oC and the ambient temperature (TA) is defined by the power system design, the maximum

Copyright  ANPEC Electronics Corp. Rev. A.2 - Apr., 2004

www.anpec.com.tw22

APA2030/2031

Application Descriptions

power dissipation which the IC package is able to handle can be obtained from equation13. Once the power dissipation is greater than the maximum limit (P

), either the supply voltage (VDD) must

D,MAX

bedecreased, the load impedance (RL) must be increased or the ambient temperature should be reduced.

Thermal Pad Considerations

The thermal pad must be connected to ground. The package with thermal pad of the APA2030/1 requires special attention on thermal design. If the thermal design issues are not properly addressed, the

APA2030/1 4Ω will go into thermal shutdown when

driving a 4Ω load.

The thermal pad on the bottom of the APA2030/1 should be soldered down to a copper pad on the circuit board. Heat can be conducted away from the thermal pad through the copper plane to ambient. If the copper plane is not on the top surface of the circuit board, 8 to 10 vias of 13 mil or smaller in diameter should be used to thermally couple the thermal pad to the bottom plane. For good thermal conduction, the vias must be plated through and solder filled. The copper plane used to conduct heat away from the thermal pad should be as large as practical.

To calculate maximum ambient temperatures, first consideration is that the numbers from the Power Dissipation vs. Output Power graphs (page17) are per channel values, so the dissipation of the IC heat needs to be doubled for two-channel operation. Given

θJA, the maximum allowable junction temperature (T

), and the total internal dissipation (PD), the maxi-

MAX

mum ambient temperature can be calculated with the following equation. The maximum recommended junction temperature for the APA2030/1 is 150°C. The internal dissipation figures are taken from the Power Dissipation vs. Output Power graphs. (Page17)

T

A,Max

= T

-θϑAPD (14)

J,Max

150 - 45(0.8*2) = 78°C (TSSOP-P24)

150 - 48(0.8*2) = 73.2°C (TSSOP-P20)

The APA2030/1 is designed with a thermal shutdown protection that turns the device off when the junction temperature surpasses 150°C to prevent damaging the IC.

J,

If the ambient temperature is higher than 25°C, a larger copper plane or forced-air cooling will be required to keep the APA2030/1 junction temperature below the thermal shutdown temperature (150°C).

In higher ambient temperature, higher airflow rate and/ or larger copper area will be required to keep the IC out of thermal shutdown.

Thermal Considerations

Linear power amplifiers dissipate a significant amount of heat in the package under normal operating conditions.

Copyright  ANPEC Electronics Corp. Rev. A.2 - Apr., 2004

www.anpec.com.tw23

APA2030/2031

0

8

0

8

φ

3

Packaging Information

TSSOP/ TSSOP-P ( Reference JEDEC Registration MO-153)

2 x E / 2

EXPOSED THERMAL

PAD =ONE

(THERMALLY ENHANCED VARIATIONDS ONLY)

Dim

Min. Max. Min. Max.

A 1.2 0.047 A1 0.00 0.15 0.000 0.006 A2 0.80 1.05 0.031 0.041

D

6.4 (N=20PIN)

7.7 (N=24PIN)

9.6 (N=28PIN)

D1

e 0.65 BSC 0.026 BSC

E 6.40 BSC 0.252 BSC E1 4.30 4.50 0.169 0.177 E2

L 0.45 0.75 0.018 0.030

L1 1.0 REF 0.039REF

R 0.09 0.004 R1 0.09 0.004

S 0.2 0.008

1 2 12° REF 12° REF

12° REF 12°REF

e

N

E1 E

12

3

e/2

D

b

D1

BOTTOM VIEW

Millimeters Inches

6.6 (N=20PIN)

7.9 (N=24PIN)

9.8 (N=28PIN)

4.2 BSC (N=20PIN)

4.7 BSC (N=24PIN)

3.8 BSC (N=28PIN)

3.0 BSC (N=20PIN)

3.2 BSC (N=24PIN)

2.8 BSC (N=28PIN)

°

A2

A

A1

E2

0.25

(3)

0.252 (N=20PIN)

0.303 (N=24PIN)

0.378 (N=28PIN)

S

(2)

(L1)

GAUGE

PLANE

L

1

0.260 (N=20PIN)

0.311 (N=24PIN)

0.386 (N=28PIN)

0.165 BSC (N=20PIN)

0.188 BSC (N=24PIN)

0.150 BSC (N=28PIN)

0.118 BSC (N=20PIN)

0.127 BSC (N=24PIN)

0.110 BSC (N=28PIN)

°

Copyright  ANPEC Electronics Corp. Rev. A.2 - Apr., 2004

www.anpec.com.tw24

APA2030/2031

Physical Specifications

Terminal Material Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn Lead Solderability Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.

Reflow Condition

(IR/Convection or VPR Reflow)

T

P

Ramp-up

T

L

Tsmax

Tsmin

Temperature

ts

Preheat

25

°

t 25 C to Peak

Classificatin Reflow Profiles

tp

Ramp-down

Time

Critical =one

T

to T

L

P

t

L

Profile Feature

Average ramp-up rate (T

to TP)

L

Preheat

 Temperature Min (Tsmin)  Temperature Mix (Tsmax)  Time (min to max)(ts)

Tsmax to T

L

Sn-Pb Eutectic Assembly Pb-Free Assembly

Large Body Small Body Large Body Small Body

3°C/second max. 3°C/second max.

100°C 150°C

60-120 seconds

- Ramp-up Rate Tsmax to TL

 Temperature(T  Time (t

)

L

Peak Temperature(Tp) Time within 5°C of actual Peak

Temperature(tp) Ramp-down Rate

Time 25°C to Peak Temperature

Note: All temperatures refer to topside of the package. Measured on the body surface.

Copyright  ANPEC Electronics Corp. Rev. A.2 - Apr., 2004

)

L

60-150 seconds

225 +0/-5°C 240 +0/-5°C 245 +0/-5°C 250 +0/-5°C

10-30 seconds 10-30 seconds 10-30 seconds 20-40 seconds

6°C/second max. 6°C/second max.

6 minutes max. 8 minutes max.

183°C

150°C 200°C

60-180 seconds

3°C/second max

217°C

60-150 seconds

www.anpec.com.tw25

APA2030/2031

Reliability Test Program

Test item Method Description

SOLDERABILITY MIL-STD-883D-2003 HOLT MIL-STD-883D-1005.7 PCT JESD-22-B,A102 TST MIL-STD-883D-1011.9 ESD MIL-STD-883D-3015.7 VHBM ! 2KV, VMM ! 200V Latch-Up JESD 78 10ms, 1tr ! 100mA

Carrier Tape & Reel Dimensions

245°C, 5 SEC 1000 Hrs Bias #125°C 168 Hrs, 100%RH, 121°C

-65°Ca150°C, 200 Cycles

t

D1

D

Bo

Ko

T2

B

T1

E

F

W

A

Po

P

P1

Ao

J

C

Application

TSSOP- 24

Copyright  ANPEC Electronics Corp. Rev. A.2 - Apr., 2004

A B C J T1 T2 W P E

330 ±1 100 ref 13 ±0.5 2 ±0.5 16.4 ±0.2 2 ±0.2 16 ±0.3 12 ±0.1 1.75±0.1

F D D1 Po P1 Ao Bo Ko t

7.5 ±0.1 1.5 +0.1 1.5 min 4.0 ±0.1 2.0 ±0.1 6.9 ±0.1 8.3 ±0.1 1.5 ±0.1 0.3±0.05

(mm)

www.anpec.com.tw26

APA2030/2031

Cover Tape Dimensions

Application Carrier Width Cover Tape Width Devices Per Reel

TSSOP- 24

Customer Service

Anpec Electronics Corp.

Head Office :

5F, No. 2 Li-Hsin Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050

Taipei Branch :

7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369

16 21.3 2000

Copyright  ANPEC Electronics Corp. Rev. A.2 - Apr., 2004

www.anpec.com.tw27

Datasheet APA2030, APA2031 Datasheet (ANPEC)

Specifications and Main Features

Frequently Asked Questions

User Manual