AN-695
APPLICATION NOTE
One Technology Way
9106
www.analog.com
thermistor (3450
TEC+
TEC–
PVDD
GND
TEC
+
POWER
SUPPLY
TEMPSET
AG
ND
THERMIN
ADN8831 DEMO BOARD
R
TH
–
= 3450 thermistor.
T m TEMPSET VREF
SET
= 25 C – ( – / 2) ° ×
is approximately 2.4 V, and
lowers the temperature -to -TEMPSET slope
/2
/2
is the gain constant and
C10
= 10 and
= 3.3 rads.
and
if C10 has been adjusted.
(found from Step 5 in the previous
is different from R
to
= 17.8 k
and
and
recorded from the
recorded from the
= 67 k
= 40 k
and
by replacing
with
is 19.6 k
in terms of
and
results in
The TEC has a heating limit of 0.7 A and a
gives an
and
= 5
OUTPUT
in our design.
in the design.
and R1 = 8 k
–6
COMPOSC
PVDD
SPGATE
SWITCH
SNGATE
PGND
COMPSW
SFB
24
23
22
21
201819
17
VREF
OUT2
IN2M
IN2P
OUT1
INIM
ILIMC
INIP
1
2
3
4
576
8
AVDD
PHASE
TMPGD
AG
ND
FREQ
SS/SB
SYNCIN/SD
SYNCOUT
9
10
11
12
13
15
14
16
ILIMH
VLIM
VTEC
ITEC
CS
LFB
LPGATE
LNGATE
32
31
30
29
28
26
27
25
ADN8831
P10
GND
P9
GND
P8
TEC–
C15
22F
CDE ESRD
L1
3.3
H
COILCRAFT
MOS6020-332MX
C6
0.1F
PVDD
P1
VREF
P2
THERMIN
P3
AGND
P4
OUT1
P5
OUT2
P6
TEMPSET
C9
27nF
R19
10k
R18
2.49k
R17
2.49k
JP1
VREF
R6
20k
R5
20k
C10
10F
R16
30.1k
C17
100nF
R26
10m
P7
TEC+
PVDD
FDW2520C
C2
4.7nF
C3
4.7nF
C16
22F
CDE ESRD
JP2
C18
100
F
C7
0.1
F
PVDD
L2
BEAD
C14
22F
C5
0.1
F
AV
DD
R12
10k
JP3
HEADER2
1
2
PVDD
SHORT JUMPER
TO
SHUTDOWN
TP8
SYNCI
TP7
SYNCO
C4
0.1F
R24
150k
TP6
PHASE
D1
LED(G)
R23
150
PVDD
AV
DD
Q1
FDV301N
R11
10k
C8
NOPOP
R13
0
R10
200k
R8
7.68k
(1%)
R9
17.8k
(1%)
R7
17.8k
(1%)
R4
20k
R3
20k
R2
0
R22
0
VREF
VREF
C1
0.1F
TP5
ILIMC
R20
NOPOP
R21
4.99k
TP1
ILIMH
TP2
VLIM
TP3
VTEC
TP4
ITEC
C11
10nF
PVDD
PVDD
R14
0
R15
0
D2
NOPOP
R25
1k
C13
NOPOP
FDW2520C
Q3
D3
NOPOP
C13
NOPOP
Q2
7
6
2
3
8
5
4
7
6
2
3
8
5
4
JP4
HEADER2
1
2
R1
19.6k
1
2
32
1
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