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AN-694
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APPLICATION NOTE
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106 • Tel: 781/329-4700 • Fax: 781/326-8703 • www.analog.com
Hot Swap and Blocking FET Control Using 2 ⴛ ADM1073 Hot Swap Controllers
by Alan Moloney
INTRODUCTION
In many –48 V hot swap systems, there is a blocking diode in
series with the hot swapping FET. This component ensures
that current can only fl ow into the load in one direction, preventing damage to the board in the case of reverse currents
fl owing. Figure 1 shows this implementation in an ADM1073
controlled system.
This solution can have serious power dissipation implications during normal operation due to the voltage drop
across the blocking diode
PPP P
=+ +
LOSS FET DIODE QUIESCENT
where
P Load Current Diode Voltage Drop
=
DIODE
Note that P
tion
of the total power loss (see Figure 1).
()
will be r e s p onsibl e for a substantial
DIODE
×
()
por-
This is especially evident in applications where the average load current level is high and the total power losses
are calculated across an entire system, which may
con
sist of multiple racks of boards.
PLUG-IN BOARD
48VRTN
As explained in this application note, another solution
for systems where this power loss is unacceptable is to
replace the blocking diode with a blocking FET that
a low on resistance. A second ADM1073 can con
has
trol
this blocking FET. Figure 2 shows this solution on a
plug-in board.
This solution will reduce the power dissipation during
operation to
PP P P
=++
LOSS HSWAP-FET BLK -FET QUIESCENT
where
P Load Current FET On Resistance
Note that P
BLK-FET
=
()
will be much smaller than P
BLK-FET
2
×
()
and
DIODE
will therefore reduce the total power loss signifi cantly.
The AN-694 Application Note should be consulted in
conjunction with the ADM1073 data sheet.
PLUG-IN BOARD
48VRTN
LIVE
BACKPLANE
(ADM1073)
BLOCKING
FET
CONTROLLER
(ADM1073)
HOT SWAP
FET
CONTROLLER
LOAD
LIVE
BACKPLANE
–48V
(ADM1073)
HOT SWAP
FET
CONTROLLER
HOT SWAP
R
SENSE
SERIES BLOCKING DIODE
FET
LOAD
–48V
BLOCKING
FET
R
HOT SWAP
SENSE
SERIES BLOCKING FET REPLACES DIODE
FET
Figure 2. Alternative Solution—Blocking FET
Replaces Diode
Figure 1. Blocking Diode in Series with Hot Swap FET
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AN-694
–48VRTN
–48VIN
800k⍀
R9
500k⍀
R8
R10
250k⍀
OV
UV
SS
t
V
ON
V
EE
R1
30k⍀
IN
SUPPLYGOOD
LATCHEDOFF
SOFTRESEAT
ADM1073(B)
SENSE
GATE DRAIN
PWRGD
RESET
FET2
Figure 3. Full Implementation of Dual ADM1073 Solution for Blocking FET and Hot Swap FET Control
DETAILED DESCRIPTION
Figure 3 shows a full implementation of a dual ADM1073
solution for blocking FET and hot swap FET control.
FET1 is the hot swap FET. This device must also have a
low on resistance and a high reverse voltage capability. This device will be required to dissipate high power
during startup, so a D2PAK device may be required.
ADM1073(A) is the hot swap FET controller that controls FET1.
FET2 is the blocking FET. This device must have a low
on resistance to minimize power dissipation and a high
reverse voltage capability. This device will not have to
dissipate as much power so a smaller package may be
suitable (e.g., SOIC). ADM1073(B) is the blocking FET
controller that controls FET2.
A single sense element, R
, can be used for both
SENSE
ADM1073 devices. With this method, the ADM1073(A)
will limit forward load current to 100 mV/R
SENSE
the ADM1073(B) will limit reverse load current to
18 mV/100 mV.
Example Confi guration for ADM1073(A)
The undervoltage level is set by R5 and R6. R5 = 500 k;
R6 = 15 k will normally give a UV rising threshold of
32.3 V and a UV falling threshold of 29.8 V. In this case,
the UV rising level will actually be 32.9 V + FET1 body
diode voltage drop (~1 V) and UV falling level will be
29.8 V + I
2
R of FET2.
The overvoltage level is set by R3 and R4. R3 = 400 k;
R4 = 10 k will normally give an OV rising threshold
of 79.1 V and an OV falling threshold of 77.1 V. In this
case, the OV falling level will actually be 77.1 V + FET2
body diode voltage drop (~1 V) and the OV rising level
will be 79.1 V + I
2
R of FET1.
R2
30k⍀
V
IN
R3
R4
R5
500k⍀
R6
15k⍀
R
SENSE
0.010⍀
C
SS
2.2nF
C
t
82nF
OV
UV
SS
t
ON
ON
V
EE
400k⍀
10k⍀
The soft start time is set by C3. C3 = 2.2 nF = > tSS =
The tON time is selected by the CtON capacitor, e.g., CtON =
gives a t
rain fold back (for FET SOA protection) is set with
The d
of 5.8 ms at –48 V.
ON (MAX)
SUPPLYGOOD
LATCHEDOFF
SOFTRESEAT
ADM1073(A)
SENSE
GATE DRAIN
PWRGD
RESET
FET1
R
DRAIN
5M⍀
LOAD
0.9 ms.
82 nF
R7.
A 5 M resistor will be suffi cient to charge a 470 F load.
The dropper resistor R2 is set to 30 k for normal opera
tion.
The LATCHEDOFF o u t p ut is t ied bac k to the SO FTRESEAT
input to give a continuous retry with a 5 second cooling
off period under short- circuit condition.
The RESET input is used as the start-up control if it is
required.
The PWRGD output is used as a hot swap completion
fl ag, which is required.
The SUPPLYGOOD output is connected to the OV pin of the
ADM1073(B) to provide a start-up signal to the ADM1073(B)
based on the voltage detection in the ADM1073(A).
;
Example Confi guration for ADM1073(B)
The SENSE and V
pins connect across the ADM1073(A)
EE
sense resistor with connections reversed, i.e., the
ADM1073(B) SENSE pin is connected to the ADM1073(A)
V
pin and the ADM1073(B) VEE pin is connected to
EE
the ADM1073(A) SENSE pin. This will configure the
ADM1073(B) to regulate current in FET2 only if it sees a
reverse current fl owing in the sense resistor.
The Undervoltage (UV) pin is tied to a resistor divider
from the VIN pin. The resistor values should be chosen
so
that the voltage on the UV pin is always above the UV
threshold, e.g., R9 = 500 k; R10 = 250 k = > VUV = 4
The Overvoltage (OV) pin is connected to the SUP
V.
PLY-
GOOD output of the ADM1073(A) so that startup of the
–2–
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AN-694
ADM1073(B) is controlled by the ADM1073(A). A resistor to V
on this pin ensures that the voltage on the OV
EE
pin does not exceed 5 V when the supply of the chip on
the ADM1073(A) is high (e.g., R8 = 800 k = > OV = 4 V
when high plus pull-up from OV hysteresis, which will
bring it up to V
The Softstart (SS) pin is tied to V
of ADM1073(B) but not above this).
CC
. This fi xes the reverse
EE
current control level at 18 mV, as opposed to up to 97.5 mV
default. This limits the maximum reverse current to approximately 1/6th of the forward inrush current limit.
The t
will current limit at 18 mV/R
pin is left open. If reverse current is detected, it
ON
for only a few micro-
SENSE
seconds plus the time taken to charge the gate up to V
of the FET (the retry duty cycle should be less than 10%).
This will then retry seven times and then shut off, which
should take no more than ~0.5 ms.
The DRAIN pin is unused, so it should be tied to V
The dropper resistor R2 is set to 30 k for normal opera
.
EE
tion.
The LATCHEDOFF o u t p ut is t ied bac k to the SO FTRESEAT
input. If reverse current saturation persists for more than
0.5 ms, the blocking FET will shut off completely and then
retry after 5 seconds (e.g., if the input voltage is shor ted
for 100 ms, a small average reverse current would fl ow
for 0.5 ms. The FET would switch off 5 seconds after the
supply was good again, and the FET would turn back on
and shunt the diode current).
The RESET function is unused, so leave the RESET pin
disconnected.
The PWRGD function is unused, so leave the PWRGD pin
disconnected.
The SUPPLYGOOD function is unused, so leave the
SUP
PLYGOOD pin disconnected.
Example Comparison for Power Dissipation Using Both Methods
Assumptions:
= 5 A
I
LOAD
= 10 m
R
ONFET
= 1 V
V
DIODE
Standard confi guration using hot swap FET and blocking
diode:
Input Lower = 96 W
T
Hot Swap Power Loss = P
FET
+ P
DIODE
+ P
QUIESCENT
= (5 5 0.01) + (5 1) + (48 0.0026)
= 5.37 W
(= 5.6% power loss)
New confi guration using hot swap FET and blocking FET:
Input Power = 96 W
Hot Swap Power Loss = P
HSWAP-FET
+ P
BLK-FET
+ P
QUIESCENT
= (5 5 0.01) + (5 5 0.01) + (48 0.0026)
= 0.62 W
(= 0.65% total power loss)
Table I.
Described Above
Results Based on Example Confi guration
Power Percentage
Solution Loss Loss
Standard Diode Solution 5.37 W 5.6%
Dual ADM1073 Solution 0.62 W 0.65%
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E04578–0–11/03(0)
© 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
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