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AN2691
Application note
ST10 RPD pin:
functionality during reset and Power Down mode
Introduction
RPD is a dedicated timing pin for the return-from-power-down circuit. Additionally, when this
pin is recognized low, a reset event is taken as asynchronous. This application note gives
advice on configuring the external circuitry connected to the RPD pin in order to make it
work properly.
The information contained in this document is valid for ST10F27x and ST10R27x.
March 2008 Rev 1 1/10
www.st.com
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RPD functionality AN2691
1 RPD functionality
RPD is a dual-purpose dedicated pin. This section covers its functionality.
1.1 System reset and startup
Several ST10 reset events that may occur are summarized in the following table:
Table 1. Reset event definition
Reset Source Flag
Power-on reset PONR Low Power-on
Asynchronous hardware
reset
Synchronous long
hardware reset
Synchronous short
hardware reset
Watchdog timer reset WDTR
Software reset SWR
1. Flags can be read in the WDTCON register
2. The RPD status has no influence unless bidirectional reset is activated (bit BDRSTEN in SYSCON): RPD
low inhibits the bidirectional reset on SW and WDT reset events, that is RSTIN
(1)
LHWR
SHWR High
RPD
Status
Low t
High t
(2)
(2)
Conditions
> 500 ns
RSTIN
> (1032 + 12) TCL + max (4 TCL, 500 ns)
RSTIN
t
> max (4 TCL, 500 ns)
RSTIN
t
≤ (1032 + 12) TCL + max (4 TCL, 500 ns)
RSTIN
WDT overflow
SRST instruction execution
is not activated.
Therefore, roughly, the RPD pin level distinguishes between an asynchronous (low level)
and a synchronous reset (high level). The main difference between these two kinds of reset
is that the first immediately cancels pending internal hold states and if any, it aborts all
internal/external bus cycles whereas in the synchronous reset, after RSTIN
level is
detected, a short duration of a maximum of 12 TCL (six periods of CPU clock) elapses,
during which pending internal hold states are cancelled and the current internal access
cycle, if any, is completed. For this reason, if an asynchronous reset occurs during a read or
write phase in internal memories, the content of the memory itself could be corrupted. To
avoid this, synchronous reset usage is strongly recommended.
However, asynchronous reset must be used during the power-on of the device. Depending
on crystal or resonator frequency, the on-chip oscillator needs about 1 ms to 10 ms to
stabilize with an already stable V
. The logic of the ST10 does not need a stabilized clock
DD
signal to detect an asynchronous reset and is therefore suitable for power-on conditions.
On the contrary, the reset state machine needs a stabilized clock to operate correctly.
According to the length of pulse on RSTIN
long or short. Long and Short synchronous resets differ by the start-up configuration bits
latched:
– Long synchronous reset latches the entire Port0 configuration, including clock
frequency selection (P0[15:13])
– Short synchronous reset ignores the bits P0[15:13] and the same clock frequency
is applied.
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, the synchronous reset may be recognized as
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AN2691 RPD functionality
Refer to the product documentation for a full description of the reset mechanism.
The RSTIN
pin is an input of the device that can be configured as an output that shows a
low level during the internal reset condition. This is called bidirectional reset and is enabled
by setting the BDRSTEN bit in the SYSCON register.
When enabled, the open drain of the RSTIN
pin is activated, pulling down the reset signal
for the duration of the internal reset sequence (synchronous/asynchronous hardware,
synchronous software and synchronous watchdog timer resets). At the end of the internal
reset sequence (1024 TCL) the pull-down is released.
The figure below shows a simplified reset circuitry scheme.
Please refer to the product user
manual for more details and timings related to system reset.
Figure 1. Internal (simplified) reset circuitry
EINIT instruction
Clr
Internal
reset
signal
Reset state
machine
Clock
Trigger
Clr
Q
Set
SRST instruction
watchdog overflow
Reset sequence
(512 CPU clock cycles)
BDRSTEN
V
RSTOUT
DD
RSTIN
Asynchronous
reset
From/to exit
powerdown
circuit
V
DD
Weak pull-down
(–200 µA)
RPD
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RPD functionality AN2691
1.2 Power down
To reduce power consumption, the microcontroller can be switched to Power Down mode.
Clocking of all internal blocks is stopped, the contents of the internal RAM, however, are
preserved through the voltage supplied via the V
The ST10 provides two different operating Power Down modes:
● Protected Power Down mode
● Interruptible Power Down mode
The Power Down operating mode is selected by the bit PWDCFG in the SYSCON register.
pins (and on-chip voltage regulator).
DD
In the first case, the Power Down mode can only be entered if the NMI
(Non Maskable
Interrupt) pin is externally pulled low while the PWRDN instruction is executed and the only
way to exit the Power Down mode is with an external hardware reset.
In the second case, the Power Down mode can be entered if enabled Fast External Interrupt
pins (EXxIN pins, alternate functions of Port 2 pins, with x = 7...0) are at their inactive level.
This inactive level is configured with the EXIxES bit field in the EXICON register, as follows:
EXICON (F1C0H / E0H) ESFR Reset value: 0000H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXI7ES EXI6ES EXI5ES EXI4ES EXI3ES EXI2ES EXI1ES EXI0ES
RW RW RW RW RW RW RW RW
EXIxES
(x=7...0)
External Interrupt x Edge Selection Field (x=7...0)
‘00’: Fast external interrupts disabled: Standard mode.
EXxIN pin not taken into account for entering/exiting Power Down mode.
‘01’: Interrupt on positive edge (rising).
Enter Power Down mode if EXiIN = ‘0’, exit if EXxIN = ‘1’ (referred to as ‘high’ active level)
‘10’: Interrupt on negative edge (falling).
Enter Power Down mode if EXiIN = ‘1’, exit if EXxIN = ‘0’ (referred to as ‘low’ active level)
‘11’: Interrupt on any edge (rising or falling).
Always enter Power Down mode, exit if EXxIN level changed.
Interruptible Power Down mode can be exited by asserting either RSTIN or one of the
enabled EXxIN pins (Fast External Interrupt).
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AN2691 RPD functionality
Figure 2. Simplified power down exit circuitry
V
DD
en_clk_n
stop PLL
stop oscillator
exit_pwrd
V
DD
Pull-up
Weak pull-down
(–200 µA)
CPU and peripherals clocks
RPD
Enter
Power Down
External
interrupt
Reset
DQ
Q1
cd
V
DD
DQ
Q2
cd system clock
Q
Q
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External RPD circuitry examples AN2691
2 External RPD circuitry examples
To ensure that the two functions explained in the previous chapter work correctly, the
external circuitry must be connected to the RPD pin.
2.1 RC network
A simple RC network can be connected to the RPD pin leading to correct behavior during
both system reset and return from power down. The cases will be analyzed separately
considering that the resistor R and the capacitor C are connected as in Figure 3.
2.1.1 System reset
On power-up, the logical low level on the RPD pin forces an asynchronous hardware reset
when
RSTIN
is asserted low (see Figure 1). The external pull-up R will then charge the
capacitor C. Note that an internal pull-down device on the RPD pin is turned on when the
RSTIN
pin is low, and causes the external capacitor (C) to begin discharging at a typical rate
of 100 to 200 µA. With this mechanism, after a power-up reset, short low pulses applied on
RSTIN
produce synchronous hardware reset. If
needed for C to be discharged by the internal pull-down device, then the device is forced
into an asynchronous reset.
RSTIN
is asserted for longer than the time
2.1.2 Return from power down
To exit Power Down mode with external interrupt, an EXxIN pin must be asserted for at least
40 ns (x = 7...0). This signal enables the internal main oscillator (if not already running) and
PLL circuitry, and also turns on the internal weak pull-down on the RPD pin. The discharging
of the external capacitor C provides a delay that allows the oscillator and PLL circuits to
stabilize before the internal CPU and peripheral clocks are enabled. When the voltage on
the RPD pin drops below the threshold voltage, the CPU and peripheral clocks are enabled
and the device resumes code execution (see Figure 2 on page 5).
Figure 3. RPD pin: internal (simplified) and external circuitry
Driven by internal
reset/pwrnd
circuitry
V
DD
Pull-up
Weak pull-down
(–200 µA)
RPD
V
DD
R
+
C
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AN2691 External RPD circuitry examples
2.1.3 RC network sizing
To calculate the external C value, we will suppose that a time T is required to stabilize the
oscillator and PLL circuit. Regarding a generic inverter I/O characteristic, the output level V
of that inverter can be considered high as long as the input level V
(see Figure 4: Generic inverter I/O characteristics).
Figure 4. Generic inverter I/O characteristics
V
o
V
OHmin
V
OLmax
V
ILmax
V
IHmin
is higher than its V
i
V
i
IHmin
o
In the same way, as long as the RPD voltage is higher than V
, CPU and peripherals are
IH1
not fed with any clock (Figure 2: Simplified power down exit circuitry). Therefore, the
capacitor value must be chosen to maintain the voltage above V
T
required by the PLL and oscillator (also the input hysteresis on the RPD pin (V
restart
for at least the time
IH1
HYS4
)
must be considered).
Using the simple formula that controls the discharge of capacitor C, we obtain:
I
pulldownTrestart⋅
C
-----------------------------------------------------------------=
where I
pulldown
Supposing V
V
HYS4max
= 1500 mV, I
VDD V
is the current that flows internally through the weak pull-down.
= 5 V, since (see product datasheet) V
DD
pulldown
= 200 µA and T
–()–
IH1VHYS4
= 3.5 V, V
IH1
= 10.2 ms (crystal oscillator + PLL),
restart
HYS4min
= 500 mV,
it follows that:
I
C
pulldownTrestart⋅
--------------------------------------------------------------------------- -
VDD V
–()–
IH1VHYS4min
200 10
----------------------------------------------------------------------
6–
⋅⋅ ⋅
10 2, 10
2
3–
1 µF∼==
As during reset a pull-down is activated on the RPD pin, the capacitor C will be discharged.
Subsequently the voltage will drop, causing the RPD pin to be seen at a low level. Therefore,
an asynchronous reset will be detected.
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External RPD circuitry examples AN2691
Table 2.
RSTIN
pulse length and reset events in the presence of an RC network
Pulse length Event
t
<= 500 ns No effect (filtered)
RSTIN
500 ns < t
512 CPU clock cycles < t
t
> 10 ms Asynchronous reset
RSTIN
< 512 CPU clock cycles Short synchronous reset
RSTIN
< 10 ms Long synchronous reset
RSTIN
The value of the resistor R, instead, is linked to the time needed to charge the capacitor C.
Normally 220 kΩ < R < 1 MΩ
.
2.2 Alternate configuration
If both synchronous reset and interruptible power down modes are not required, it is
possible to connect the RPD pin to ground, directly or through a resistance.
Figure 5. RPD pin connected to ground
V
DD
Pull-Up
driven by internal
reset/pwrnd
circuitry
Weak Pull-Down
(~ 200 µA)
RPD
The internal pull-up is sized to allow a direct connection to ground without any problem to
the internal circuitry.
As already explained, with this kind of connection, any pulse longer than 500 ns on the
RSTIN
pin leads to an asynchronous reset. Moreover, it is not advised to use an interruptible
power-down.
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AN2691 Revision history
3 Revision history
Table 3. Document revision history
Date Revision Changes
06-Mar-2008 1 Initial release.
9/10
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AN2691
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