Page 1
2
3
8
1
6
5
IN(–)
IN(+)
INPUT BUFFERS
R
GAIN
100k
REF
100k
V
OUT
11k
11k
Precision Single Supply
1
2
3
4
8
7
6
5
AMP-04
R
GAIN
V+
V
OUT
REF
R
GAIN
–IN
+IN
V–
AMP-04
V+
R
GAIN
V
OUT
REF
R
GAIN
–IN
+IN
V–
a
FEATURES
Single Supply Operation
Low Supply Current: 700 mA max
Wide Gain Range: 1 to 1000
Low Offset Voltage: 150 mV max
Zero-In/Zero-Out
Single-Resistor Gain Set
8-Pin Mini-DIP and SO packages
APPLICATIONS
Strain Gages
Thermocouples
RTDs
Battery Powered Equipment
Medical Instrumentation
Data Acquisition Systems
PC Based Instruments
Portable Instrumentation
GENERAL DESCRIPTION
The AMP04 is a single-supply instrumentation amplifier
designed to work over a +5 volt to ± 15 volt supply range. It
offers an excellent combination of accuracy, low power consumption, wide input voltage range, and excellent gain
performance.
Gain is set by a single external resistor and can be from 1 to
1000. Input common-mode voltage range allows the AMP04 to
handle signals with full accuracy from ground to within 1 volt of
the positive supply. And the output can swing to within 1 volt of
the positive supply. Gain bandwidth is over 700 kHz. In addition to being easy to use, the AMP04 draws only 700 µA of sup-
ply current.
For high resolution data acquisition systems, laser trimming of
low drift thin-film resistors limits the input offset voltage to
under 150 µV, and allows the AMP04 to offer gain nonlinearity
of 0.005% and a gain tempco of 30 ppm/°C.
A proprietary input structure limits input offset currents to less
than 5 nA with drift of only 8 pA/°C, allowing direct connection
of the AMP04 to high impedance transducers and other signal
sources.
*Protected by U.S. Patent No. 5,075,633.
Instrumentation Amplifier
AMP04*
FUNCTIONAL BLOCK DIAGRAM
The AMP04 is specified over the extended industrial (–40°C to
+85°C) temperature range. AMP04s are available in plastic and
ceramic DIP plus SO-8 surface mount packages.
Contact your local sales office for MIL-STD-883 data sheet
and availability.
PIN CONNECTIONS
8-Lead Epoxy DIP
(P Suffix)
8-Lead Narrow-Body SO
(S Suffix)
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
Page 2
AMP04–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(VS = +5 V, VCM = +2.5 V, TA = +258C unless otherwise noted)
AMP04E AMP04F
Parameter Symbol Conditions Min Typ Max Min Typ Max Units
OFFSET VOLTAGE
Input Offset Voltage V
IOS
Input Offset Voltage Drift TCV
Output Offset Voltage V
OOS
IOS
–40°C ≤ T
–40°C ≤ T
≤ +85°C 300 600 µV
A
≤ +85°C3 6mV
A
30 150 300 µV
36µV/°C
0.5 1.5 3 mV
Output Offset Voltage Drift TCVoos 30 50 µV/°C
INPUT CURRENT
Input Bias Current I
B
Input Bias Current Drift TCI
Input Offset Current I
OS
Input Offset Current Drift TCI
B
OS
–40°C ≤ T
–40°C ≤ T
≤ +85°C50 60nA
A
≤ +85°C10 15nA
A
22 30 40 nA
65 65 pA/°C
15 10nA
8 8 pA/°C
INPUT
Common-Mode Input Resistance 4 4 GΩ
Differential Input Resistance 4 4 GΩ
Input Voltage Range V
IN
Common-Mode Rejection CMR 0 V ≤ V
≤ 3.0 V
CM
0 3.0 0 3.0 V
G = 1 60 80 55 dB
G = 10 80 100 75 dB
G = 100 90 105 80 dB
G = 1000 90 105 80 dB
Common-Mode Rejection CMR 0 V ≤ V
–40°C ≤ T
≤ 2.5 V
CM
A
≤ +85°C
G = 1 55 50 dB
G = 10 75 70 dB
G = 100 85 75 dB
G = 1000 85 75 dB
Power Supply Rejection PSRR 4.0 V ≤ V
–40°C ≤ T
≤ 12 V
S
≤ +85°C
A
G = 1 95 85 dB
G = 10 105 95 dB
G = 100 105 95 dB
G = 1000 105 95 dB
GAIN (G = 100 K/R
GAIN
)
Gain Equation Accuracy G = 1 to 100 0.2 0.5 0.75 %
G = 1 to 100
–40°C ≤ T
≤ +85°C 0.8 1.0 %
A
G = 1000 0.4 0.75 %
Gain Range G 1 1000 1 1000 V/V
Nonlinearity G = 1, R
G = 10, R
G = 100, R
= 5 kΩ 0.005 %
L
= 5 kΩ 0.015 %
L
= 5 kΩ 0.025 %
L
Gain Temperature Coefficient ∆G/∆T 30 50 ppm/°C
OUTPUT
Output Voltage Swing High V
Output Voltage Swing Low V
OH
OL
R
= 2 kΩ 4.0 4.2 4.0 V
L
R
= 2 kΩ
L
–40°C ≤ T
R
= 2 kΩ
L
–40°C ≤ T
≤ +85°C 3.8 3.8 V
A
≤ +85°C 2.0 2.5 mV
A
Output Current Limit Sink 30 30 mA
Source 15 15 mA
–2–
REV. A
Page 3
AMP04
AMP04E AMP04F
Parameter Symbol Conditions Min Typ Max Min Typ Max Units
NOISE
Noise Voltage Density, RTI e
Noise Current Density, RTI i
Input Noise Voltage e
N
N
p-p 0.1 to 10 Hz, G = 1 7 7 µV p-p
N
DYNAMIC RESPONSE
Small Signal Bandwidth BW G = 1, –3 dB 300 300 kHz
POWER SUPPLY
Supply Current I
Specifications subject to change without notice.
SY
f = 1 kHz, G = 1 270 270 nV/√Hz
f = 1 kHz, G = 10 45 45 nV/√
f = 100 Hz, G = 100 30 30 nV/√
f = 100 Hz, G = 1000 25 25 nV/√
f = 100 Hz, G = 100 4 4 pA/√Hz
0.1 to 10 Hz, G = 10 1.5 1.5 µV p-p
0.1 to 10 Hz, G = 100 0.7 0.7 µV p-p
550 700 700 µA
–40°C ≤ TA ≤ +85°C 850 850 µA
Hz
Hz
Hz
ELECTRICAL CHARACTERISTICS
Parameter Symbol Conditions Min Typ Max Min Typ Max Units
(VS = 65 V, VCM = 0 V, TA = +258C unless otherwise noted)
AMP04E AMP04F
OFFSET VOLTAGE
Input Offset Voltage V
IOS
Input Offset Voltage Drift TCV
Output Offset Voltage V
OOS
IOS
–40°C ≤ T
–40°C ≤ T
≤ +85°C 600 900 µV
A
≤ +85°C6 9mV
A
80 400 600 µV
36µV/°C
13 6 mV
Output Offset Voltage Drift TCVoos 30 50 µV/°C
INPUT CURRENT
Input Bias Current I
B
Input Bias Current Drift TCI
Input Offset Current I
OS
Input Offset Current Drift TCI
B
OS
–40°C ≤ T
–40°C ≤ T
≤ +85°C50 60nA
A
≤ +85°C15 20nA
A
17 30 40 nA
65 65 pA/°C
25 10nA
28 28 pA/°C
INPUT
Common-Mode Input Resistance 4 4 GΩ
Differential Input Resistance 4 4 GΩ
Input Voltage Range V
IN
Common-Mode Rejection CMR –12 V ≤ V
≤ +12 V
CM
–12 +12 –12 +12 V
G = 1 60 80 55 dB
G = 10 80 100 75 dB
G = 100 90 105 80 dB
G = 1000 90 105 80 dB
Common-Mode Rejection CMR –11 V ≤ V
–40°C ≤ T
≤ +11 V
CM
≤ +85°C
A
G = 1 55 50 dB
G = 10 75 70 dB
G = 100 85 75 dB
G = 1000 85 75 dB
Power Supply Rejection PSRR ±2.5 V ≤ V
–40°C ≤ T
≤ ±18 V
S
≤ +85°C
A
G = 1 75 70 dB
G = 10 90 80 dB
G = 100 95 85 dB
G = 1000 95 85 dB
REV. A
–3–
Page 4
AMP04
AMP04E AMP04F
Parameter Symbol Conditions Min Typ Max Min Typ Max Units
GAIN (G = 100 K/R
GAIN
)
Gain Equation Accuracy G = 1 to 100 0.2 0.5 0.75 %
G = 1000 0.4 0.75 %
G = 1 to 100
–40°C ≤ T
≤ +85°C 0.8 1.0 %
A
Gain Range G 1 1000 1 1000 V/V
Nonlinearity G = 1, R
G = 10, R
G = 100, R
= 5 kΩ 0.005 0.005 %
L
= 5 kΩ 0.015 0.015 %
L
= 5 kΩ 0.025 0.025 %
L
Gain Temperature Coefficient ∆G/∆T 30 50 ppm/°C
OUTPUT
Output Voltage Swing High V
Output Voltage Swing Low V
OH
OL
R
= 2 kΩ +13 +13.4 +13 V
L
R
= 2 kΩ
L
–40°C ≤ T
R
= 2 kΩ
L
–40°C ≤ T
≤ +85°C +12.5 +12.5 V
A
≤ +85°C –14.5 –14.5 V
A
Output Current Limit Sink 30 30 mA
Source 15 15 mA
NOISE
Noise Voltage Density, RTI e
N
f = 1 kHz, G = 1 270 270 nV/√Hz
f = 1 kHz, G = 10 45 45 nV/√
f = 100 Hz, G = 100 30 30 nV/√
f = 100 Hz, G = 1000 25 25 nV/√
Noise Current Density, RTI i
Input Noise Voltage e
N
p-p 0.1 to 10 Hz, G = 1 5 5 µV p-p
N
f = 100 Hz, G = 100 4 4 pA/√Hz
0.1 to 10 Hz, G = 10 1 1 µV p-p
0.1 to 10 Hz, G = 100 0.5 0.5 µV p-p
Hz
Hz
Hz
DYNAMIC RESPONSE
Small Signal Bandwidth BW G = 1, –3 dB 700 700 kHz
POWER SUPPLY
Supply Current I
SY
750 900 900 µA
–40°C ≤ TA ≤ +85°C 1100 1100 µA
Specifications subject to change without notice.
WAFER TEST LIMITS
(VS = +5 V, VCM = +2.5 V, TA = +258C unless otherwise noted)
Parameter Symbol Conditions Limit Units
OFFSET VOLTAGE
Input Offset Voltage V
Output Offset Voltage V
IOS
OOS
300 µV max
3 mV max
INPUT CURRENT
Input Bias Current I
Input Offset Current I
B
OS
40 nA max
10 nA max
INPUT
Common-Mode Rejection CMR 0 V ≤ V
≤ 3.0 V
CM
G = 1 55 dB min
G = 10 75 dB min
G = 100 80 dB min
G = 1000 80 dB min
Common-Mode Rejection CMR V
= ±15 V, –12 V ≤ VCM ≤ +12 V
S
G = 1 55 dB min
G = 10 75 dB min
G = 100 80 dB min
–4–
REV. A
Page 5
AMP04
Parameter Symbol Conditions Limit Units
G = 1000 80 dB min
Power Supply Rejection PSRR 4.0 V ≤ V
G = 1 85 dB min
G = 10 95 dB min
G = 100 95 dB min
G = 1000 95 dB min
≤ 12 V
S
GAIN (G = 100 K/R
GAIN
)
Gain Equation Accuracy G = 1 to 100 0.75 % max
OUTPUT
Output Voltage Swing High V
Output Voltage Swing Low V
OH
OL
R
= 2 kΩ 4.0 V min
L
R
= 2 kΩ 2.5 mV max
L
POWER SUPPLY
Supply Current I
SY
V
= ±15 900 µA max
S
700 µA max
NOTE
Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard
product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±18 V
Common-Mode Input Voltage
1
2
. . . . . . . . . . . . . . . . . . ±18 V
DICE CHARACTERISTICS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 36 V
Output Short-Circuit Duration to GND . . . . . . . . . . Indefinite
Storage Temperature Range
Z Package . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +175°C
P, S Package . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
AMP04A . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
AMP04E, F . . . . . . . . . . . . . . . . . . . . . . . . .–40°C to +85°C
Junction Temperature Range
Z Package . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +175°C
P, S Package . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering, 60 sec) . . . . . . . +300°C
Package Type θ
3
JA
θ
JC
Units
8-Pin Cerdip (Z) 148 16 °C/W
8-Pin Plastic DIP (P) 103 43 °C/W
8-Pin SOIC (S) 158 43 °C/W
NOTES
1
Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
2
For supply voltages less than ± 18 V, the absolute maximum input voltage is
equal to the supply voltage.
3
θJA is specified for the worst case conditions, i.e., θJA is specified for device in
socket for cerdip, P-DIP, and LCC packages; θJA is specified for device
soldered in circuit board for SOIC package.
ORDERING GUIDE
Temperature VOS @ +5 V Package Package
Model Range TA = +258C Description Option
AMP04EP XIND 150 µV Plastic DIP N-8
AMP04ES XIND 150 µV SOIC SO-8
AMP04FP XIND 300 µV Plastic DIP N-8
AMP04FS XIND 300 µV SOIC SO-8
AMP04FS-REEL XIND 150 µV SOIC SO-8
AMP04FS-REEL7 XIND 150 µV SOIC SO-8
AMP04GBC +25°C 300 µV
REV. A
–5–
AMP04 Die Size 0.075 × 0.99 inch, 7,425 sq. mils.
Substrate (Die Backside) Is Connected to V+.
Transistor Count, 81.
Page 6
AMP04
+10.00V
+10.01V
100k
100k
V
OUT
11k
–15V
+10.01V
100Ω
100µA
+15V
11k
+11.111V
+
–
0.1µA
100.1µA
–15V
+15V
+10V
APPLICATIONS
Common-Mode Rejection
The purpose of the instrumentation amplifier is to amplify the
difference between the two input signals while ignoring offset
and noise voltages common to both inputs. One way of judging
the device’s ability to reject this offset is the common-mode
gain, which is the ratio between a change in the common-mode
voltage and the resulting output voltage change. Instrumentation amplifiers are often judged by the common-mode rejection
ratio, which is equal to 20 × log
differential signal gain to the common-mode gain, commonly
called the CMRR. The AMP04 offers excellent CMRR, guaranteed to be greater than 90 dB at gains of 100 or greater. Input
offsets attain very low temperature drift by proprietary lasertrimmed thin-film resistors and high gain amplifiers.
Input Common-Mode Range Includes Ground
The AMP04 employs a patented topology (Figure 1) that
uniquely allows the common-mode input voltage to truly extend
to zero volts where other instrumentation amplifiers fail. To illustrate, take for example the single supply, gain of 100 instrumentation amplifier as in Figure 2. As the inputs approach zero
volts, in order for the output to go positive, amplifier A’s output
(V
) must be allowed to go below ground, to –0.094 volts.
OA
Clearly this is not possible in a single supply environment. Consequently this instrumentation amplifier configuration’s input
common-mode voltage cannot go below about 0.4 volts. In
comparison, the AMP04 has no such restriction. Its inputs will
function with a zero-volt common-mode voltage.
IN(–)
IN(+)
2
INPUT BUFFERS
3
1
of the ratio of the user-selected
10
100k
R
GAIN
8
V
OUT
6
Input Common-Mode Voltage Below Ground
Although not tested and guaranteed, the AMP04 inputs are biased in a way that they can amplify signals linearly with commonmode voltage as low as –0.25 volts below ground. This holds
true over the industrial temperature range from –40°C to +85°C.
Extended Positive Common-Mode Range
On the high side, other instrumentation amplifier configurations, such as the three op amp instrumentation amplifier, can
have severe positive common-mode range limitations. Figure 3
shows an example of a gain of 1001 amplifier, with an input
common-mode voltage of 10 volts. For this circuit to function,
V
must swing to 15.01 volts in order for the output to go to
OB
10.01 volts. Clearly no op amp can handle this swing range
(given a +15 V supply) as the output will saturate long before it
reaches the supply rails. Again the AMP04’s topology does not
have this limitation. Figure 4 illustrates the AMP04 operating at
the same common-mode conditions as in Figure 3. None of the
internal nodes has a signal high enough to cause amplifier saturation. As a result, the AMP04 can accommodate much wider
common-mode range than most instrumentation amplifiers.
+10.00V
+10.01V
200Ω
50µA
A
100k
100k
B
V
OA
V
OB
+5V
+15.01V
R
R
R
10.01
R
Figure 3. Gain = 1001, Three Op Amp Instrumentation
Amplifier
11k
11k
100k
REF
5
Figure 1. Functional Block Diagram
0.01V
+
V
IN
0V
–
Figure 2. Gain = 100 Instrumentation Amplifier
100k
0V
A
20k
4.7µA
4.7µA
V
OA
–.094V
2127Ω
20k
5.2µA
0.01V
B
100k
V
V
OB
OUT
Figure 4. Gain = 1000, AMP04
–6–
REV. A
Page 7
AMP04
Programming the Gain
The gain of the AMP04 is programmed by the user by selecting
a single external resistor—R
Gain = 100 kΩ/R
GAIN
:
GAIN
The output voltage is then defined as the differential input voltage times the gain.
V
OUT
= (V
IN+
– V
) × Gain
IN–
In single supply systems, offsetting the ground is often desired
for several reasons. Ground may be offset from zero to provide
a quieter signal reference point, or to offset “zero” to allow a
unipolar signal range to represent both positive and negative
values.
In noisy environments such as those having digital switching,
switching power supplies or externally generated noise, ground
may not be the ideal place to reference a signal in a high accuracy system.
Often, real world signals such as temperature or pressure may
generate voltages that are represented by changes in polarity. In
a single supply system the signal input cannot be allowed to go
below ground, and therefore the signal must be offset to accommodate this change in polarity. On the AMP04, a reference input pin is provided to allow offsetting of the input range.
The gain equation is more accurately represented by including
this reference input.
V
Grounding
OUT
= (V
IN+
– V
IN–
) × Gain + V
REF
The most common problems encountered in high performance
analog instrumentation and data acquisition system designs are
found in the management of offset errors and ground noise.
Primarily, the designer must consider temperature differentials
and thermocouple effects due to dissimilar metals, IR voltage
drops, and the effects of stray capacitance. The problem is
greatly compounded when high speed digital circuitry, such as
that accompanying data conversion components, is brought
into the proximity of the analog section. Considerable noise and
error contributions such as fast-moving logic signals that easily
propagate into sensitive analog lines, and the unavoidable noise
common to digital supply lines must all be dealt with if the accuracy of the carefully designed analog section is to be preserved.
Besides the temperature drift errors encountered in the amplifier, thermal errors due to the supporting discrete components
should be evaluated. The use of high quality, low-TC components where appropriate is encouraged. What is more important,
large thermal gradients can create not only unexpected changes
in component values, but also generate significant thermoelectric voltages due to the interface between dissimilar metals such
as lead solder, copper wire, gold socket contacts, Kovar lead
frames, etc. Thermocouple voltages developed at these junctions commonly exceed the TCV
contribution of the
OS
AMP04. Component layout that takes into account the power
dissipation at critical locations in the circuit and minimizes gradient effects and differential common-mode voltages by taking
advantage of input symmetry will minimize many of these errors.
High accuracy circuitry can experience considerable error contributions due to the coupling of stray voltages into sensitive
areas, including high impedance amplifier inputs which benefit
from such techniques as ground planes, guard rings, and
shields. Careful circuit layout, including good grounding and
signal routing practice to minimize stray coupling and ground
loops is recommended. Leakage currents can be minimized by
using high quality socket and circuit board materials, and by
carefully cleaning and coating complete board assemblies.
As mentioned above, the high speed transition noise found in
logic circuitry is the sworn enemy of the analog circuit designer.
Great care must be taken to maintain separation between them
to minimize coupling. A major path for these error voltages will
be found in the power supply lines. Low impedance, load related variations and noise levels that are completely acceptable
in the high thresholds of the digital domain make the digital
supply unusable in nearly all high performance analog applications. The user is encouraged to maintain separate power and
ground between the analog and digital systems wherever possible, joining only at the supply itself if necessary, and to observe careful grounding layout and bypass capacitor scheduling
in sensitive areas.
Input Shield Drivers
High impedance sources and long cable runs from remote transducers in noisy industrial environments commonly experience
significant amounts of noise coupled to the inputs. Both stray
capacitance errors and noise coupling from external sources can
be minimized by running the input signal through shielded
cable. The cable shield is often grounded at the analog input
common, however improved dynamic noise rejection and a reduction in effective cable capacitance is achieved by driving the
shield with a buffer amplifier at a potential equal to the voltage
seen at the input. Driven shields are easily realized with the
AMP04. Examination of the simplified schematic shows that the
potentials at the gain set resistor pins of the AMP04 follow the
inputs precisely. As shown in Figure 5, shield drivers are easily
realized by buffering the potential at these pins by a dual, single
supply op amp such as the OP213. Alternatively, applications
with single-ended sources or that use twisted-pair cable could
drive a single shield. To minimize error contributions due to
this additional circuitry, all components and wiring should remain in proximity to the AMP04 and careful grounding and bypassing techniques should be observed.
1/2 OP-213
2
3
1
8
1/2 OP-213
V
OUT
6
Figure 5. Cable Shield Drivers
REV. A
–7–
Page 8
2
3
8
1
6
5
IN(–)
IN(+)
INPUT BUFFERS
R
GAIN
100k
REF
100k
V
OUT
11k
11k
R
GAIN
C
EXT
ƒ
LP =
1
2π (100k) C
EXT
7
1
6
5
4
3
2
8
+15V
–15V
100
0.15µF
10
90
100
0%
5mV
10ms
AMP04
Compensating for Input and Output Errors
To achieve optimal performance, the user needs to take into
account a number of error sources found in instrumentation
amplifiers. These consist primarily of input and output offset
voltages and leakage currents.
The input and output offset voltages are independent from one
another, and must be considered separately. The input offset
component will of course be directly multiplied by the gain of
the amplifier, in contrast to the output offset voltage that is independent of gain. Therefore, the output error is the dominant
factor at low gains, and the input error grows to become the
greater problem as gain is increased. The overall equation for
offset voltage error referred to the output (RTO) is:
V
(RTO) = (V
OS
where V
is the input offset voltage and V
IOS
voltage, and G is the programmed amplifier gain.
The change in these error voltages with temperature must also
be taken into account. The specification TCV
output, is a combination of the input and output drift specifications. Again, the gain influences the input error but not the output, and the equation is:
TCV
(RTO) = (TCV
OS
In some applications the user may wish to define the error contribution as referred to the input, and treat it as an input error.
The relationship is:
TCV
(RTI) = TCV
OS
The bias and offset currents of the input transistors also have an
impact on the overall accuracy of the input signal. The input
leakage, or bias currents of both inputs will generate an additional offset voltage when flowing through the signal source resistance. Changes in this error component due to variations with
signal voltage and temperature can be minimized if both input
source resistances are equal, reducing the error to a commonmode voltage which can be rejected. The difference in bias current between the inputs, the offset current, generates a differential error voltage across the source resistance that should be
taken into account in the user’s design.
In applications utilizing floating sources such as thermocouples,
transformers, and some photo detectors, the user must take care
to provide some current path between the high impedance inputs and analog ground. The input bias currents of the AMP04,
although extremely low, will charge the stray capacitance found
in nearby circuit traces, cables, etc., and cause the input to drift
erratically or to saturate unless given a bleed path to the analog
common. Again, the use of equal resistance values will create a
common input error voltage that is rejected by the amplifier.
Reference Input
The V
input is used to set the system ground. For dual sup-
REF
ply operation it can be connected to ground to give zero volts
out with zero volts differential input. In single supply systems it
could be connected either to the negative supply or to a pseudoground between the supplies. In any case, the REF input must
be driven with low impedance.
Noise Filtering
Unlike most previous instrumentation amplifiers, the output
stage’s inverting input (Pin 8) is accessible. By placing a capacitor across the AMP04’s feedback path (Figure 6, Pins 6 and 8)
IOS
IOS
× G) + V
IOS
OOS
OOS
× G) + TCV
+ (TCV
OOS
the output offset
, referred to the
OS
OOS
/ G)
Figure 6. Noise Band Limiting
a single-pole low-pass filter is produced. The cutoff frequency
(f
) follows the relationship:
LP
fLP=
2π (100 kΩ) C
1
EXT
Filtering can be applied to reduce wide band noise. Figure 7a
shows a 10 Hz low-pass filter, gain of 1000 for the AMP04. Figures 7b and 7c illustrate the effect of filtering on noise. The
photo in Figure 7b shows the output noise before filtering. By
adding a 0.15 µF capacitor, the noise is reduced by about a
factor of 4 as shown in Figure 7c.
Figure 7a. 10 Hz Low-Pass Filter
Figure 7b. Unfiltered AMP04 Output
–8–
REV. A
Page 9
AMP04
1mV
100
90
10
0%
2s
Figure 7c. 10 Hz Low-Pass Filtered Output
Power Supply Considerations
In dual supply applications (for example ± 15 V) if the input is
connected to a low resistance source less than 100 Ω, a large
current may flow in the input leads if the positive supply is applied before the negative supply during power-up. A similar
condition may also result upon a loss of the negative supply. If
these conditions could be present in you system, it is recommended that a series resistor up to 1 kΩ be added to the input
leads to limit the input current.
This condition can not occur in a single supply environment as
losing the negative supply effectively removes any current return
path.
Offset Nulling in Dual Supply
Offset may be nulled by feeding a correcting voltage at the V
REF
pin (Pin 5). However, it is important that the pin be driven with
a low impedance source. Any measurable resistance will degrade
the amplifier’s common-mode rejection performance as well as
its gain accuracy. An op amp may be used to buffer the offset
null circuit as in Figure 8.
R
G
AMP-04
–
INPUT
+
1
2
3
4
V–
–5V
* OP-90 FOR LOW POWER
OP-113 FOR LOW DRIFT
REF
8
+5V
–5V
+5V
OUTPUT
*
±5mV
ADJ
RANGE
+5V
50k
100Ω
50k
–5V
7
V+
6
5
First, the potentiometer should be adjusted to cause the
output to swing in the positive direction; then adjust it in
the reverse direction, causing the output to swing toward
ground, until the output just stops changing. At that point
the output is at the saturation limit.
R
G
AMP-04
INPUT
1
2
3
4
8
OP-113
+5V
OUTPUT
100Ω
+5V
50k
7
6
5
Figure 9. Offset Adjust for Single Supply Applications
Alternative Nulling Method
An alternative null correction technique is to inject an offset current into the summing node of the output amplifier
as in Figure 10. This method does not require an external
op amp. However the drawback is that the amplifier will
move off its null as the input common-mode voltage
changes. It is a less desirable nulling circuit than the previous method.
V+ V–
100k
R
GAIN
IN(–)
IN(+)
2
INPUT BUFFERS
3
1
100k
REF
5
8
11k
11k
V
OUT
6
Figure 10. Current Injection Offsetting Is Not
Recommended
Figure 8. Offset Adjust for Dual Supply Applications
Offset Nulling in Single Supply
Nulling the offset in single supply systems is difficult because
the adjustment is made to try to attain zero volts. At zero volts
out, the output is in saturation (to the negative rail) and the output voltage is indistinguishable from the normal offset error.
Consequently the offset nulling circuit in Figure 9 must be used
with caution.
REV. A
–9–
Page 10
AMP04
APPLICATION CIRCUITS
Low Power Precision Single Supply RTD Amplifier
Figure 11 shows a linearized RTD amplifier that is powered off
a single +5 volt supply. However, the circuit will work up to 36
volts without modification. The RTD is excited by a 100 µA
constant current that is regulated by amplifier A (OP295). The
0.202 volts reference voltage used to generate the constant current is divided down from the 2.500 volt reference. The AMP04
amplifies the bridge output to a 10 mV/°C output coefficient.
BALANCE
R1
26.7k
R
SENSE
1k
RTD
100Ω
R3
500Ω
R2
26.7k
1
R4
100Ω
23
R5
1.02k
1/2
OP-295
2.5V
REF-43
A
0.202V
6
OUT
GND
4
C3
+5V
0.1µF
3
2
R7
121k
R6
11.5k
IN
NOTES: ALL RESISTORS ±0.5%, ±25 PPM/°C
ALL POTENTIOMETERS ±25 PPM/°C
AMP-04
2
7
7
C2
0.1µF
383Ω
1
4
+5V
8
4
+5V
R8
5
1/2
OP-295
8
R9
50Ω
100Ω
6
6
5
B
R10
FULL-SCALE
ADJ
C1
0.47µF
V
OUT
0→4.00V
(0°C TO 400°C)
50k
LINEARITY
ADJ.
(@1/2 FS)
Figure 11. Precision Single Supply RTD Thermometer
Amplifier
The RTD is linearized by feeding a portion of the signal back to
the reference circuit, increasing the reference voltage as the temperature increases. When calibrated properly, the RTD’s nonlinearity error will be canceled.
To calibrate, either immerse the RTD into a zero-degree ice
bath or substitute an exact 100 Ω resistor in place of the RTD.
Then adjust bridge BALANCE potentiometer R3 for a 0 volt
output. Note that a 0 volt output is also the negative output
swing limit of the AMP04 powered with a single supply. Therefore, be sure to adjust R3 to first cause the output to swing
positive and then back off until the output just stop swinging
negatively.
Next, set the LINEARITY ADJ. potentiometer to the midrange. Substitute an exact 247.04 Ω resistor (equivalent to
400°C temperature) in place of the RTD. Adjust the
FULL-SCALE potentiometer for a 4.000 volts output.
Finally substitute a 175.84 Ω resistor (equivalent to 200°C
temperature), and adjust the LINEARITY ADJ potentiometer
for a 2.000 volts at the output. Repeat the full-scale and the
half-scale adjustments as needed.
When properly calibrated, the circuit achieves better than
±0.5°C accuracy within a temperature measurement range from
0°C to 400°C.
Precision 4-20 mA Loop Transmitter With Noninteractive
Trim
Figure 12 shows a full bridge strain gage transducer amplifier
circuit that is powered off the 4-20 mA current loop. The
AMP04 amplifies the bridge signal differentially and is converted to a current by the output amplifier. The total quiescent
current drawn by the circuit, which includes the bridge, the amplifiers, and the resistor biasing, is only a fraction of the 4 mA
null current that flows through the current-sense resistor
R
. The voltage across R
SENSE
feeds back to the OP90’s in-
SENSE
put, whose common-mode is fixed at the current summing
reference voltage, thus regulating the output current.
With no bridge signal, the 4 mA null is simply set up by the
50 kΩ NULL potentiometer plus the 976 kΩ resistors that inject an offset that forces an 80 mV drop across R
SENSE
. At a
50 mV full-scale bridge voltage, the AMP04 amplifies the
voltage-to-current converter for a full-scale of 20 mA at the output. Since the OP90’s input operates at a constant 0 volt
common-mode voltage, the null and the span adjustments do
Figure 12. Precision 4-20 mA Loop Transmitter Features Noninteractive Trims
–10–
REV. A
Page 11
AMP04
1
2
3
4
8
7
6
5
AMP-04
V–
REF
V+
–
+
INPUT
V
OUT
+5V
TO +30V
R
G
R
G
0.1µF
0.22µF
100k
10.9k
3
14
715Ω
200Ω
200Ω
6
11
4
5
ADG221
+5V TO +30V
13
10
9
7
8
15
16
2
1
12
+
10µF
0.1µF
GAIN OF 500
WR
GAIN OF 100
GAIN OF 10
GAIN CONTROL
not interact with one another. Calibration is simple and easy
with the NULL adjusted first, followed by SPAN adjust. The
entire circuit can be remotely placed, and powered from the
4-20 mA 2-wire loop.
4-20 mA Loop Receiver
At the receiving end of a 4-20 mA loop, the AMP04 makes a
convenient differential receiver to convert the current back to a
usable voltage (Figure 13). The 4-20 mA signal current passes
through a 100 Ω sense resistor. The voltage drop is differentially
amplified by the AMP04. The 4 mA offset is removed by the
offset correction circuit.
4–20mA
TRANS-
MITTER
IN4002
4–20mA
4–20mA
+–
POWER
SUPPLY
1k
100Ω 1%
1k
WIRE RESISTANCE
–
+
3
2
+15V
7
1
AMP-04
4
–15V
–15V
100k
5
6
27k
0.15µF
8
6
OP-177
–0.400V
3
AD589
V
OUT
0–1.6V FS
2
10k
+–
Single Supply Programmable Gain Instrumentation Amplifier
Combining with the single supply ADG221 quad analog switch,
the AMP04 makes a useful programmable gain amplifier that
can handle input and output signals at zero volts. Figure 15
shows the implementation. A logic low input to any of the gain
control ports will cause the gain to change by shorting a gainset resistor across AMP04’s Pins 1 and 8. Trimming is required
at higher gains to improve accuracy because the switch ONresistance becomes a more significant part of the gain-set
resistance. The gain of 500 setting has two switches connected
in parallel to reduce the switch resistance.
Figure 13. 4-to-20 mA Line Receiver
Low Power, Pulsed Load-Cell Amplifier
Figure 14 shows a 350 Ω load cell that is pulsed with a low duty
cycle to conserve power. The OP295’s rail-to-rail output capability allows a maximum voltage of 10 volts to be applied to the
bridge. The bridge voltage is selectively pulsed on when a measurement is made. A negative-going pulse lasting 200 ms should
be applied to the MEASURE input. The long pulse width is
necessary to allow ample settling time for the long time constant
of the low-pass filter around the AMP04. A much faster settling
time can be achieved by omitting the filter capacitor.
+12V
OUT
1N4148
IN
REF-01
GND
50k
MEASURE
V
OUT
330Ω
350Ω
Figure 14. Pulsed Load Cell Bridge Amplifier
1/2
OP-295
+12V
3
AMP-04
2
7
4
1
1k
2N3904
5
10k
10V
0.22µF
8
6
REV. A
Figure 15. Single Supply Programmable Gain Instrumentation Amplifier
The switch ON resistance is lower if the supply voltage is
12 volts or higher. Additionally the overall amplifier’s temperature coefficient also improves with higher supply voltage.
–11–
Page 12
AMP04
120
0
0.5
60
20
–0.4
40
–0.5
100
80
0.40.20.10 0.3–0.1–0.2–0.3
NUMBER OF UNITS
INPUT OFFSET VOLTAGE – mV
BASED ON 300 UNITS
3 RUNS
TA = +25°C
V
S
= ±15V
V
CM
= 0V
120
0
5
60
20
–4
40
–5
100
80
42103–1–2–3
NUMBER OF UNITS
OUTPUT OFFSET – mV
BASED ON 300 UNITS
3 RUNS
TA = +25°C
V
S
= ±15V
V
CM
= 0V
120
100
80
60
40
NUMBER OF UNITS
20
BASED ON 300 UNITS
3 RUNS
TA = +25°C
V
= +5V
S
V
= 2.5V
CM
0
–160
–200
Figure 16. Input Offset (V
120
100
80
60
40
NUMBER OF UNITS
20
0
0.25
0
INPUT OFFSET VOLTAGE – µV
) Distribution @ +5 V
IOS
TCV
– µV/ °C
IOS
Figure 18. Input Offset Drift (TCV
16080400 120–40–80–120
300 UNITS
= +5V
V
S
V
= 2.5V
CM
2.50
2.251.751.501.25 2.001.000.750.50
) Distribution @ +5 V
IOS
200
Figure 17. Input Offset (V
120
100
80
60
40
NUMBER OF UNITS
20
0
0.25
0
) Distribution @ ±15 V
IOS
TCV
– µV/°C
IOS
Figure 19. Input Offset Drift (TCV
300 UNITS
VS = ±15V
VCM = 0V
2.50
2.251.751.501.25 2.001.000.750.50
) Distribution @ ±15 V
IOS
Figure 20. Output Offset (V
120
BASED ON 300 UNITS
3 RUNS
100
80
60
40
NUMBER OF UNITS
20
0
–1.6
–2.0
OUTPUT OFFSET – mV
TA = +25°C
V
V
) Distribution @ +5 V
OOS
= +5V
S
CM
= 2.5V
1.60.80.40 1.2–0.4–0.8–1.2
2.0
Figure 21. Output Offset (V
–12–
) Distribution @ ±15 V
OOS
REV. A
Page 13
120
NUMBER OF UNITS
TCV
OOS
– µV/ °C
120
0
24
60
20
4
40
2
100
80
22181614 20121086
300 UNITS
VS = ±15V
VCM = 0V
TEMPERATURE – °C
15.0
–15.1
100
–14.8
–15.0
–25
–14.9
–50
12.5
–14.7
–14.6
13.0
13.5
14.0
14.5
7550250
RL = 100k
–OUTPUT SWING – Volts
+OUTPUT SWING – Volts
RL = 10k
RL = 2k
RL = 100k
RL = 10k
VS = +5V
RL = 10k
RL = 2k
RL = 100k
RL = 10k
RL = 2k
RL = 100k
AMP04
100
80
60
40
NUMBER OF UNITS
20
0
2
0
TCV
OOS
– µV/ °C
Figure 22. Output Offset Drift (TCV
@ +5 V
5.0
4.8
4.6
RL = 100k
4.4
300 UNITS
V
= +5V
S
V
= 0V
CM
18141210 16864
) Distribution
OOS
VS = +5V
20
Figure 23. Output Offset Drift (TCV
±
15 V
@
) Distribution
OOS
Figure 24. Output Voltage Swing vs. Temperature
@ +5 V
REV. A
4.2
RL = 10k
4.0
OUTPUT VOLTAGE SWING – Volts
3.8
–50
40
35
30
25
20
15
10
INPUT BIAS CURRENT – nA
5
0
–25
–25–50
TEMPERATURE – °C
TEMPERATURE – °C
RL = 2k
VS = +5V, V
VS = ±15V, V
VS = +5V
VS = ±15V
CM
7550250
CM
= 2.5V
= 0V
7550250
100
100
Figure 26. Input Bias Current vs. Temperature
–13–
Figure 25. Output Voltage Swing vs. Temperature
+15 V
@
8
VS = +5V, V
VS = ±15V
6
4
VS = +5V
2
INPUT OFFSET CURRENT – nA
0
–50 100
–25
TEMPERATURE – °C
50 75250
= 2.5V
CM
, VCM
VS = ±15V
= 0V
Figure 27. Input Offset Current vs. Temperature
Page 14
AMP04
50
G = 100
40
30
G = 10
20
10
G = 1
VOLTAGE GAIN – dB
0
–10
–20
1k 1M100k10k100
FREQUENCY – Hz
TA = +25°C
VS = ±15V
Figure 28. Closed-Loop Voltage Gain vs. Frequency
120
100
G = 100
80
60
40
TA = +25°C
VS = ±15V
VCM = 2V
G = 10
P-P
120
100
OUTPUT IMPEDANCE – Ω
TA = +25°C
G = 1
80
60
40
20
0
100 100k10k1k10
FREQUENCY – Hz
VS = ±15V
VS = +5V
Figure 29. Closed-Loop Output Impedance vs. Frequency
120
TA = +25°C
VS = ±15V
110
VCM = 2V
P-P
100
90
80
20
COMMON-MODE REJECTION – dB
0
–20
1 10 100k10k1k100
G = 1
FREQUENCY – Hz
Figure 30. Common-Mode Rejection vs. Frequency
140
120
100
80
60
40
POWER SUPPLY REJECTION – dB
20
0
10 100 1M100k10k1k
G = 100
G = 1
FREQUENCY – Hz
TA = +25°C
VS = ±15V
∆VS = ±1V
G = 10
Figure 32. Positive Power Supply Rejection vs. Frequency
70
COMMON-MODE REJECTION – dB
60
50
110 1k100
VOLTAGE GAIN – G
Figure 31. Common-Mode Rejection vs. Voltage Gain
140
120
100
80
60
40
POWER SUPPLY REJECTION – dB
20
0
10 100 1M100k10k1k
G = 100
G = 1
FREQUENCY – Hz
TA = +25°C
VS = ±15V
∆VS = ±1V
G = 10
Figure 33. Negative Power Supply Rejection vs. Frequency
–14–
REV. A
Page 15
1k
1k
100
1
110 1k100
10
VOLTAGE GAIN – G
TA = +25°C
VS = ±15V
ƒ = 1kHz
VOLTAGE NOISE – nV/ Hz
16
8
0
100 100k10k1k10
4
12
10
6
2
14
LOAD RESISTANCE – Ω
TA = +25°C
V
S
= ±15V
OUTPUT VOLTAGE – V
TA = +25°C
VS = ±15V
ƒ = 100Hz
100
10
VOLTAGE NOISE – nV/ Hz
1
110 1k100
VOLTAGE GAIN – G
Figure 34. Voltage Noise Density vs. Gain
140
120
100
TA = +25°C
V
= ±15V
S
G = 100
AMP04
Figure 35. Voltage Noise Density vs. Gain, f = 1 kHz
20mV
100
90
1s
80
60
40
VOLTAGE NOISE DENSITY – nV/ Hz
20
0
10 10k1k1001
FREQUENCY – Hz
Figure 36. Voltage Noise Density vs. Frequency
1200
1000
800
600
400
SUPPLY CURRENT – µA
200
0
–50
–25
VS = ±15V
VS = +5V
TEMPERATURE – °C
100
7550250
Figure 38. Supply Current vs. Temperature
10
0%
VS = ±15V, GAIN = 1000, 0.1 TO 10 Hz BANDPASS
Figure 37. Input Noise Voltage
Figure 39. Maximum Output Voltage vs. Load Resistance
REV. A
–15–
Page 16
AMP04
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic DIP (N-8)
8
1
0.430 (10.92)
0.348 (8.84)
0.210
(5.33)
MAX
0.160 (4.06)
0.115 (2.93)
0.022 (0.558)
0.014 (0.356)
0.005 (0.13) MIN 0.055 (1.4) MAX
1
0.405 (10.29) MAX
0.200
(5.08)
MAX
0.200 (5.08)
0.125 (3.18)
5
0.280 (7.11)
0.240 (6.10)
4
0.070 (1.77)
0.100
(2.54)
BSC
0.045 (1.15)
0.015
(0.381) TYP
SEATING
PLANE
0.130
(3.30)
MIN
0°- 15°
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
8-Lead Cerdip (Q-8)
58
0.310 (7.87)
0.220 (5.59)
4
0.070 (1.78)
0.030 (0.76)
0.060 (1.52)
0.015 (0.38)
0.150
(3.81)
MIN
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
0.195 (4.95)
0.115 (2.93)
C1720–24–10/92
0.023 (0.58)
0.014 (0.36)
0.100 (2.54)
BSC
0°-15°
SEATING PLANE
8-Lead Narrow-Body SO (S0-8)
–16–
PRINTED IN U.S.A.
REV. A
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