Datasheet AM79C984AKCW, AM79C984AJC Datasheet (AMD Advanced Micro Devices)

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PRELIMINARY

Am79C984A

enhanced Integrated Multiport Repeater (eIMR™)

DISTINCTIVE CHARACTERISTICS

Repeater functions comply with IEEE 802.3
Repeater Unit specifications

Four integral 10BASE-T transceivers with on­chip filtering that eliminate the need for external
filter modules on the 10BASE-T transmit-data
(TXD) and receive-data (RXD) lines

One Reversible Attachment Unit Interface
(RAUI™) port that can be used either as a
standard IEEE-compliant AUI port for
connection to a Medium Attachment Unit (MAU),
or as a reversed port for direct connection to a
Media Access Controller (MAC)

Low cost suitable for non-managed multiport
repeater designs

Expandable to increase number of repeater
ports with support for up to seven eIMR devices
without the need for an external arbiter

All ports can be individually isolated
(partitioned) in response to excessive collision
conditions or fault conditions.

Full LED support for individual port status LEDs
and network utilization LEDs

Programmable extended distance mode on the
RXD lines, allowing connection to cables longer
than 100 meters

Twisted Pair Link Test capability conforming to
the 10BASE-T standard. The Link Test function
and the transmission of Link Test pulses can be
optionally disabled through the control port to
allow devices that do not implement the Link Test
function to work with the eIMR device.

Programmable option of automatic polarity
detection and correction permits automatic
recovery due to wiring errors

Full amplitude and timing regeneration for
retransmitted waveforms

CMOS device with a single +5-V supply

GENERAL DESCRIPTION

The enhanced Integrated Multiport Repeater (eIMR)
device is a VLSI integrated circuit that provides a sys­tem-level solution to designing non-managed multiport
repeaters. The device integr ates the repeater functions
specified in Section 9 of the IEEE 802.3 standard and
Twisted Pair Transceiver functions complying with the
10BASE-T standard.

his document contains information on a product under development at Advanced Micro Devices. The

information is intended to help you evaluate this product. AMD reserves the right to change or discontinue

ork on this proposed product without notice.

The eIMR device provides four Twisted Pair (TP) ports
and one RAUI port for direct connection to a MAC. The
total number of ports per repeater unit can be in­creased by connecting multiple eIMR devices through
their expansion ports, hence, minimizing the total cost
per repeater port.

The device is fabricated in CMOS technology and
requires a single +5-V supply.

Publication# 20650 Rev: B Amendment/0
Issue Date: January 1998

P R E L I M I N A R Y

ORDERING INFORMATION
Standard Products

AMD standard products are available in se v eral packages and oper ating ranges. The order number (Valid Combination) is f ormed
by a combination of the elements below.

Am79C984A

CJ

\W

ALTERNATE PACKAGING OPTION

\W = Trimmed and formed in a tray

TEMPERATURE RANGE

C = Commercial (0˚C to +70˚C)

P ACKA GE TYPE

J = 84-Pin Plastic Leaded Chip Carrier (PL 084)
K = 100-Pin Plastic Quad Flat Pack (PQR100)

SPEED OPTION

Not Applicable

DEVICE NUMBER/DESCRIPTION

Am79C984A
enhanced Integrated Multiport Repeater (eIMR)

Valid Combinations

Am79C984A JC, KC\W

2 Am79C984A

Valid Combinations

Valid Combinations list configurations planned to
be supported in volume for this device. Consult
the local AMD sales office to confirm availability
of specific valid combinations and to check on
newly released combinations.

BLOCK DIAGRAM

P R E L I M I N A R Y

DAT

JAM

COL

ACK

SELI[1:0]

TX

MUX

Preamble

Jam Sequence

SELO

LDA[4:0], LDB[4:0]

LDGA, LDGB

LDC[2:0]

LED

Interface

Expansion Port

ACT[7:0]

SI

SO

SCLK

Test

and

AMODE

Port

Control

20650B-1

20650A-1

FIFO

Decoder

Manchester

RX

RX

AUI

Port

DI±

CI±

MUX

MUX

DO±

Lock

Phase

FIFO

CONTROL

Loop

TP

RXD±

0

Port

TXD±

Encoder

Manchester

Control

eIMR Chip

3

TP

Port

RXD±

TXD±

Link T est

Partitioning

Reset

RST

Clock

Timers

Gen

CLK

Am79C984A 3

RELATED AMD PRODUCTS

P R E L I M I N A R Y

Part No.

Am7990
Am7992B Serial Interface Adapter (SIA)

Am7996 IEEE 802.3/Ethernet/Cheapernet Transceiver
Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE)
Am79C98 Twisted Pair Ethernet Transceiver (TPEX)
Am79C100 Twisted Pair Ethernet Transceiver Plus (TPEX+)
Am79C981 Integrated Multiport Repeater Plus (IMR+™)
Am79C982 basic Integrated Multiport Repeater (bIMR™)
Am79C987 Hardware Implemented Management Information Base (HIMIB™)
Am79C988 Quad Integrated Ethernet Transceiver (QuIET™)
Am79C900 Integrated Local Area Communications Controller (ILACC™)
Am79C940 Media Access Controller for Ethernet (MACE™)
Am79C960 PCnet™-ISA Single-Chip Ethernet Controller (for ISA bus)
Am79C961 PCnet™-ISA+ Single-Chip Ethernet Controller for ISA (with Microsoft® Plug n’ Play® Support)
Am79C961A PCnet™-ISA II Full Duplex Single-Chip Ethernet Controller for ISA
Am79C965 PCnet™-32 Single-Chip 32-Bit Ethernet Controller
Am79C970 PCnet™-PCI Single-Chip Ethernet Controller (for PCI bus)
Am79C970A PCnet™-PCI II Full Duplex Single-Chip Ethernet Controller (for PCI bus)
Am79C974 PCnet™-SCSI Combination Ethernet and SCSI Controller for PCI Systems
Am79C983 Integrated Multiport Repeater 2 (IMR2™)
Am79C985 enhanced Integrated Multiport Repeater Plus (eIMR+™)

Description

Local Area Network Controller for Ethernet (LANCE)

4 Am79C984A

TABLE OF CONTENTS

DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-29

ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-30

STANDARD PRODUCTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30

BLOCK DIAGRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31

RELATED AMD PRODUCTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-32

CONNECTION DIAGRAM (PL 084) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-35

CONNECTION DIAGRAM (PQR100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-36

LOGIC SYMBOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-37

LOGIC DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-37

PIN DESIGNATIONS (PL 084). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-38

Listed by Pin Number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-38

PIN DESIGNATIONS (PQR100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-39

Listed by Pin Number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-39

PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-40

AUI Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-40

Twisted Pair Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-40

Expansion Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-40

Control Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-41

LED Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-41

Miscellaneous Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-41

FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-43

Basic Repeater Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-43

Repeater Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-43

Signal Regeneration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-43

Jabber Lockup Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-43

Collision Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-43

Fragment Extension. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-43

Auto Partitioning/Reconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-43

Detailed Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-44

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-44

AUI Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-44

TP Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-44

Twisted Pair Transmitters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-44

Twisted Pair Receivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-44

Link Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-45

Polarity Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-45

Visual Status Monitoring (LED) Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-45

Network Activity Display. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-46

Expansion Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-48

Internal Arbitration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-48

IMR+ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-48

Control Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-49

Command/Response Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-50

Control Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-50

SET (Write Commands) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52

P R E L I M I N A R Y

Chip Programmable Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-52

Alternate AUI Partitioning Algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-52

Alternate TP Partitioning Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-52

AUI Port Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-52

AUI Port Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-52

TP Port Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-52

TP Port Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-52

Disable Link Test Function (Per TP port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-52

Enable Link Test Function (Per TP port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-52

Disable Link Pulse (Per TP Port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-52

Am79C984A 5

P R E L I M I N A R Y

Enable Link Pulse (Per TP Port). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-52

Disable Automatic Receiver Polarity Reversal (Per TP Port). . . . . . . . . . . . . . . . .1-53

Enable Automatic Receiver Polarity Reversal (Per TP Port) . . . . . . . . . . . . . . . . .1-53

Disable Receiver Extended Distance Mode (Per TP Port). . . . . . . . . . . . . . . . . . .1-53

Enable Receiver Extended Distance Mode (Per TP Port) . . . . . . . . . . . . . . . . . . .1-53

Disable Software Override of LEDs 5

(Per Port - AUI and TP, Global) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-53

Enable Software Override of Bank A LEDs (Per Port - AUI and TP, Global). . . . .1-53

Enable Software Override of Bank B LEDs (Per Port - AUI and TP, Global). . . . .1-54

Software Override of LED Blink Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-54

GET (Read Commands). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-54

AUI Port(s) Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-54

Alternate AUI Port(s) Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-54

TP Port Partitioning Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-54

Bit Rate Error Status of TP Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-54

Link Test Status of TP ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-55

Receive Polarity Status of TP Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-55

MJLP Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-55

Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-55

SYSTEMS APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-55

eIMR to TP Port Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-55

Twisted Pair Transmitters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-55

Twisted Pair Receivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-55

MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-57

Internal Arbitration Mode Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-57

IMR+ Mode External Arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-57

Visual Status Display. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-59

ABSOLUTE MAXIMUM RATINGS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-60

OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-60

DC CHARACTERISTICS over operating ranges unless otherwise specified . . . . . . . . . . . . . . . . .1-60

SWITCHING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-62

KEY TO SWITCHING WAVEFORMS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-64

SWITCHING WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-64

SWITCHING TEST CIRCUIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-69

6 Am79C984A

P R E L I M I N A R Y

CONNECTION DIAGRAM (PL 084)

REXT
AVSS

DI+
DI–

VDD

CI+
CI–

AVSS

DO+

DO–

AMODE

VDD

DVSS

VDD

VDD

VDD
RST

CLK

DVSS
SELI_0
SELI_1

12
13
14
15
16
17
18

19
20
21

23
24

25

26

27
28
29
30
31
32

RXD3–

102211

33

34

SELO

RXD3+

RXD2–

8

9

35

36

COL

DVSS

RXD1–

RXD2+

7

6

38

37

DAT

ACK

RXD0–

RXD1+

5

39

JAM

VDD

TXD3–

VDD

RXD0+

3

4

2

eIMR

Am79C984A

41

42

40

SI

NC

DVSS

1

43

SO

AVSS

TXD3+

84

83

45

44

SCLK

TXD2+

TXD2–

81

82

46

47

VDD

ACT0

VDD

80

48

ACT1

TXD1–

TXD1+

78

79

50

49

ACT2

DVSS

TXD0–

AVSS

77

51

ACT4

ACT3

TXD0+

76

52

ACT5

75

53

VDD

74

73
72
71
70
69
68
67

66

65
64

63

62

61

60

59

58

57
56

55

54

ACT6

LDC2
LDC1
LDC0
VDD
LDGB
LDGA
LDB4

DVSS
LDA4
LDB3
LDA3
DVSS
LDB2

LDA2

VDD

LDB1
LDA1
DVSS
LDB0
LDA0
ACT7

20650A-2

20650B-2

Am79C984A 7

CONNECTION DIAGRAM (PQR100)

RXD3+

RXD2–NCRXD2+

RXD1–

RXD1+

99

98

97969594939291908988878685

RXD3–

NC
NC

NC
REXT
AVSS

DI+
DI–

VDD

CI+
CI–

AVSS

DO+
DO–

AMODE

VDD

DVSS

VDD
VDD
VDD

RST

NC

CLK

DVSS
SELI_0
SELI_1

NC
NC
NC

SELO

100

1
2
3

4

5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

31323334353637383940414243444546474849

P R E L I M I N A R Y

RXD0–

RXD0+

VDD

TXD3–

TXD3+

AVSS

TXD2–

TXD2+

VDD

TXD1–

TXD1+

848281

eIMR

Am79C984A

AVSS

TXD0–

83

TXD0+

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52

51

50

VDD
NC
NC
NC
LDC2
LDC1
LDC0
VDD
LDGB
LDGA
LDB4
DVSS
LDA4
LDB3
LDA3
DVSS
LDB2
LDA2
VDD
LDB1
LDA1
NC
DVSS
LDB0
LDA0
ACT7
NC
NC
NC
ACT6

COL

NC

DVSS

ACK

DAT

VDD

JAM

NC

SI

DVSS

SO

VDD

SCLK

ACT0

ACT1

8 Am79C984A

ACT2

DVSS

ACT3

ACT4

ACT5

20650B-3

LOGIC SYMBOL

Expansion

Port

Test and

Control

Port

DAT
JAM

ACK
COL
SELO
SELI[1:0]

SI
SO
SCLK
AMODE

CLK

RST

P R E L I M I N A R Y

V

DD

Am79C984

LDA[4:0], LDB[4:0]

TXD+

TXD–
RXD+
RXD–

DO+

DO–

DI+
DI–
CI+
CI–

LDGA, LDGB

LDC[2:0]
ACT[7:0]

Twisted Pair

Ports

(4 Ports)

AUI

LED

Interface

LOGIC DIAGRAM

LED
Port

Control

Port

DV

SS

AV

AUI

Repeater

State

Machine

SS

20650A-4

20650B-4

Expansion

Port

Twisted Pair

Port 0

Twisted Pair

Port 3

20650A-5

20650B-5

Am79C984A 9

PIN DESIGNATIONS (PL 084)
Listed by Pin Number

P R E L I M I N A R Y

Pin No .

1
2 TXD3- 23 VDD 44 SCLK 65 LDB3
3 VDD 24 DVSS 45 VDD 66 LDA4
4 RXD0+ 25 VDD 46 ACT0 67 DVSS
5 RXD0- 26 VDD 47 ACT1 68 LDB4
6 RXD1+ 27 VDD 48 ACT2 69 LDGA
7 RXD1- 28 RST 49 DVSS 70 LDGB
8 RXD2+ 29 CLK 50 ACT3 71 VDD

9 RXD2- 30 DVSS 51 ACT4 72 LDC0
10 RXD3+ 31 SELI_0 52 ACT5 73 LDC1
11 RXD3- 32 SELI_1 53 ACT6 74 LDC2
12 REXT 33 SELO 54 ACT7 75 VDD
13 AVSS 34 COL 55 LDA0 76 TXD0+
14 DI+ 35 DVSS 56 LDB0 77 TXD0­15 DI- 36 ACK 57 DVSS 78 AVSS
16 VDD 37 DAT 58 LDA1 79 TXD1+
17 CI+ 38 VDD 59 LDB1 80 TXD1­18 CI- 39 JAM 60 VDD 81 VDD
19 AVSS 40 NC 61 LDA2 82 TXD2+
20 DO+ 41 DVSS 62 LDB2 83 TXD2­21 DO- 42 SI 63 DVSS 84 AVSS

Pin Name

TXD3+ 22 AMODE 43 SO 64 LDA3

Pin No .

Pin Name

Pin No .

Pin Name

Pin No. Pin Name

10 Am79C984A

PIN DESIGNATIONS (PQR100)
Listed by Pin Number

P R E L I M I N A R Y

Pin No .

1

2 NC 27 NC 52 NC 77 NC

3 NC 28 NC 53 NC 78 NC

4 NC 29 NC 54 NC 79 NC

5 REXT 30 SELO 55 ACT7 80 VDD

6 AVSS 31 COL 56 LDA0 81 TXD0+

7 DI+ 32 DVSS 57 LDB0 82 TXD0-

8 DI- 33 NC 58 DVSS 83 AVSS

9 VDD 34 ACK 59 NC 84 TXD1+
10 CI+ 35 DAT 60 LDA1 85 TXD1­11 CI- 36 VDD 61 LDB1 86 VDD
12 AVSS 37 JAM 62 VDD 87 TXD2+
13 DO+ 38 NC 63 LDA2 88 TXD2­14 DO- 39 DVSS 64 LDB2 89 AVSS
15 AMODE 40 SI 65 DVSS 90 TXD3+
16 VDD 41 SO 66 LDA3 91 TXD3­17 DVSS 42 SCLK 67 LDB3 92 VDD
18 VDD 43 VDD 68 LDA4 93 RXD0+
19 VDD 44 ACT0 69 DVSS 94 RXD0­20 VDD 45 ACT1 70 LDB4 95 RXD1+
21 RST 46 ACT2 71 LDGA 96 RXD1­22 NC 47 DVSS 72 LDGB 97 RXD2+
23 CLK 48 ACT3 73 VDD 98 NC
24 DVSS 49 ACT4 74 LDC0 99 RXD2­25 SELI_0 50 ACT5 75 LDC1 100 RXD3+

Pin Name

RXD3- 26 SELI_1 51 ACT6 76 LDC2

Pin No .

Pin Name

Pin No .

Pin Name

Pin No. Pin Name

Notes:

1. Pin 40 has a bonding option depending on internal device name.

2. NC = No Connection.

Am79C984A 11

P R E L I M I N A R Y

DI ±

DO ±

CI ±

PIN DESCRIPTION
AUI Port

DI+, DI–
Data In
Differential Input

are differential, Manchester receiver pins. The sig-

nals comply with IEEE 802.3, Section 7.

DO+, DO–
Data Out
Differential Output

are differential, Manchester output driver pins. The

signals comply with IEEE 802.3, Section 7.

CI+, CI–
Collision Input
Differential Input/Output

are differential, Manchester I/O signals. As an input,
CI is a collision-receive indicator . As an output, CI gen­erates a 10-MHz signal if the eIMR device senses a
collision.

Twisted Pair Ports

TXD+
Transmit Data

Differential Output

TXD ± are 10BASE-T port differential drivers (4 ports).

RXD+
Receive Data

Differential Input

RXD ± are 10BASE-T port differential receive inputs
(4 ports).

0-3

0-3

, TXD–

, RXD–

0-3

0-3

Expansion Bus

DAT
Data
Input/Output/3-State

If the SELO
collision conditions, the eIMR device drives NRZ data
onto the DAT line, regenerating the preamble if neces­sary. During a collision, when JAM is HIGH, D A T is used
to differentiate between single-port (DAT=1) and multi­port (DAT=0) collisions. DAT is an output when ACK is
asserted and the eIMR device’s ports are active; DAT
is an input when ACK is asserted and the ports are
inactive. If ACK is not asserted, DAT is in the high-im­pedance state. It is recommended that DAT be pulled
up or down via a high value resistor.

JAM
Jam
Input/Output/3-State

The active eIMR device drives JAM HIGH, if it detects
a collision condition on one or more of its ports. The

and ACK pins are asserted during non-

state of the DAT pin is used in conjunction with JAM to
indicate a single port (DA T =1) or multiport (DAT=0) col­lision. J AM is in the high-impedance state if neither the
SEL

nor ACK signal is asserted. It is recommended that

JAM be pulled up or down via a high value resistor.

SELI

0-1

Select In
Input, Active LOW

When the expansion bus is configured f or Internal Arbi­tration mode, these signals indicate that another eIMR
device is active; SELI
the upstream device. At reset, SELI

or SELI

0

is driven by SELO from

1

selects between

0

the Internal Arbitration mode and the IMR+ mode of the
expansion bus; a HIGH selects the Internal Arbitration
mode and a LOW selects the IMR+ mode.

SELI_1 SELI_0

X 1 Internal
X 0 IMR+

Arbitration

Mode

SELO
Select Out
Output, Active LOW

If the expansion bus is configured f or Internal Arbitration
mode, an eIMR device drives this pin LOW when it is
active or when either of its SELI

pins is LOW. An

0-1

active eIMR device is defined as having one or more
ports receiving or colliding and/or is still transmitting
data from the internal FIFO, or extending a pack et to the
minimum of 96 bit times. When the expansion bus is
configured for IMR+ mode, SELO

is active when the

eIMR device is active (acquiring the functionality of the

pin on the Am79C971 IMR+ device).

REQ

ACK
Acknowledge
Input/Output, Active LOW, Open Drain

This signal is asserted to indicate that an eIMR device
is active. It also signals to the other eIMR devices the
presence of a valid collision status on the JAM line and
valid data on the DAT line. When the eIMR device is
configured for Internal Arbitration mode, ACK is an I/O,
and must be pulled to VDD via a minimum equivalent
resistance of 1 k
for IMR+ mode, A

When the eIMR device is configured

Ω.

CK is an input driven by an external

arbiter.

COL
Collision
Input/Output, Active LOW, Open Drain

When asserted, COL indicates that more than one eIMR
device is active. Each eIMR device generates the Col­lision Jam sequence independently . When the eIMR de­vice is configured for Internal Arbitration mode, COL is

12 Am79C984A

P R E L I M I N A R Y

an I/O and must be pulled to VDD via a minimum equiv­alent resistance of 1 k
sion port is configured for IMR+ mode, COL

Ω.

When the eIMR device expan-

is an input

driven by an external arbiter.

Control Port

AMODE
AUI Mode
Input

At reset, this pin sets the AUI port to either normal or
reversed mode. If AMODE is LOW at the rising edge of

, the AUI port is set to the normal mode; if AMODE

RST
is HIGH, the AUI port is set to the reversed mode.

SCLK
Serial Clock In
Input

Serial data (input or output) is clocked (in or out) on the
rising edge of the signal on this pin. SCLK is asynchro­nous to CLK and can operate at frequencies up to 10
MHz.

SI
Serial In
Input

The SI pin is used as a test/control serial input port.
Control commands are clocked in on this pin synchro­nous to SCLK input.

At reset, SI sets the state of the Automatic P olarity Re­versal function. If SI is HIGH at the rising edge of RST
Automatic Polarity Reversal is disabled. If SI is LOW at
the rising edge of RST, Automatic Polar ity Reversal is
enabled.

SO
Serial Out
Output

The SO pin is used as a control command serial output
port. Responses to control commands are clocked out
on this pin synchronous to the SCLK input.

LED Interface

LDA
LED Drivers

Output, Open Drain

LDA
respectively. LDA
AUI port; LDA
four TP ports. The port attributes monitored by LDA
and LDB

LDGA
Global LED Driver, Bank A
Output, Open Drain

LDGA is the Global LED driver for LED Bank A. The
signal represents global CRS or COL conditions. In a

, LDB

0-4

0-4

0-4

and LDB

are programmed by three pins, LDC

0-4

drive LED Bank A and LED Bank B,

0-4

and LDB

0

and LDB

1-4

indicate the status of the

0

indicate the status of the

1-4

0-2

0-4

.

multiple-eIMR configuration, LDGA from each of the
eIMR devices can be tied together to drive a single glo­bal LED in Bank A.

LDGB
Global LED Driver, Bank B
Output, Open Drain

LDGB is the Global LED driver for LED Bank B. The
signal represents global CRS or JAB conditions. In a
multiple eIMR configuration, LDGB from each of the
eIMR devices can be tied together to drive a single glo­bal LED in Bank B.

LDC

0-2

LED Control
Input

These pins select the attributes that will be displayed
on LDA

0-4

, LDB

, LDGA, and LDGB. If an LED is pro-

0-4

grammed to display two attributes , the attribute associ­ated with the periodic blink takes precedence.

ACT

0-7

Activity Display
Output

These signals drive the activity LEDs, which indicate
the percentage of network utilization. The displa y is up­dated every 250 ms.

Miscellaneous Pins

RST

,

Reset
Input, Active LOW

When RST is LOW , the eIMR device resets to its def ault
state. On the rising (trailing) edge of RST , the eIMR also
monitors the state of the SELI
to configure the operating mode of the device. In multi­ple eIMR systems, the falling (leading) edge of the RST
signal must be synchronized to CLK.

CLK
Master Clock In
Input

This pin is a 20-MHz clock input.

REXT
External Reference
Input

This pin is used for an internal current reference. It must
be tied to VDD via a 13-kΩ resistor with 1% tolerance.

VDD
Power
Power Pin

This pin supplies power to the device.

, SI, and AMODE pins,

0-1

Am79C984A 13

P R E L I M I N A R Y

AVSS
Analog Ground
Ground Pin

This pin is the ground reference for the differential
receivers and drivers.

DVSS
Digital Ground
Ground Pin

This pin is the ground reference for all the digital logic
in the eIMR device.

14 Am79C984A

P R E L I M I N A R Y

FUNCTIONAL DESCRIPTION

The Am79C984A eIMR device is a single-chip imple­mentation of an IEEE 802.3/Ethernet repeater (or hub).
It is offered with four integr al 10BASE-T ports plus one
RAUI port comprising the basic repeater. The eIMR de­vice is also expandable, enab ling the implementation of
high port count repeaters based on several eIMR de­vices.

The eIMR chip complies with the full set of repeater
basic functions as defined in Section 9 of ISO 8802.3
(ANSI/IEEE 802.3c). The basic repeaters functions are
summarized in the paragraphs below.

Basic Repeater Functions

The Am79C984A chip implements the basic repeater
functions as defined by Section 9.5 of the ANSI/IEEE

802.3 specification.

Repeater Function

If any single network port senses the start of a valid
packet on its receive lines , the eIMR device will retrans­mit the received data to all other enabled network ports
(except when contention exists among an y of the ports
or when the receive port is partitioned). To allow multi­ple eIMR device configurations, the data will also be re­peated on the expansion bus data line (DAT).

Signal Regeneration

When retransmitting a packet, the eIMR device en­sures that the outgoing packet complies with the IEEE

802.3 specification in terms of preamble structure and
timing characteristics. Specifically, data packets re­peated by the eIMR device will contain a minimum of 56
preamble bits before the Start-of-Frame Delimiter. In
addition, the eIMR restores the voltage amplitude of
the repeated waveform to levels specified in the IEEE

802.3 specification. Finally, the eIMR device restores
signal symmetry to repeated data packets, removing jit­ter and distortion caused by the network cabling. Jitter
present at the output of the AUI port will be better than

0.5 ns; jitter at the TP outputs will be better than 1.5 ns .
The start-of-packet propagation delay for a repeater set

is the time delay between the first edge transition of a
data packet on its input port to the first edge transition
of the repeated packet on its output ports. The start-of­packet propagation delay for the eIMR is within the
specification given in Section 9.5.5.1 of the IEEE 802.3
standard.

Jabber Lockup Protection

The eIMR device implements a built-in jabber protec­tion scheme to ensure that the network is not disabled
by the transmission of excessively long data packets.
This protection scheme causes the eIMR device to in­terrupt transmission for 96 bit-times if the device has
been transmitting continuously for more than 65,536 bit

times. This is referred to as MAU Jabber Lockup Pro­tection (MJLP). The MJLP status for the eIMR device
can be read through the Control Port, using the Get
MJLP Status command.

Collision Handling

The eIMR device will detect and respond to collision
conditions as specified in the IEEE 802.3 specification.
Repeater configurations consisting of multiple eIMR
devices also comply with the IEEE 802.3 specification,
using status signals provided by the expansion bus. In
particular, a repeater based on one or more eIMR de­vices will handle the transmit collision and one-port-left
collision conditions correctly, as specified in Section 9
of the IEEE 802.3 specification.

Fragment Extension

If the total packet length received is less than 96 bits,
including preamble, the eIMR device will e xtend the re­peated packet length to 96 bits by appending a J am se­quence to the original fragment.

Auto Partitioning/Reconnection

Any of the TP ports or the A UI port can be partitioned if
the duration or frequency of collisions becomes exces­sive. The eIMR device will continue to transmit data
packets to a partitioned port, but will not respond, as a
repeater, to activity on the partitioned port’s receiver.
The eIMR device will monitor the port and reconnect it
once certain criteria are met. The criteria for reconnec­tion are specified by the IEEE 802.3 standard. In addi­tion to the standard reconnection algorithm, the eIMR
device implements an alternative reconnection algo­rithm, which provides a more robust partitioning func­tion for the TP ports and/or AUI port. The eIMR device
partitions each TP port and the AUI port separately and
independently of other network ports.

The eIMR device will partition an enabled network port
if either of the following conditions occurs at that port:

a. A collision condition exists continuously for more

than 2048 bit times. (AUI port—SQE signal active;
TP port—simultaneous transmit and receive).

b. A collision condition occurs during each of 32 con-

secutive attempts to transmit to that port.

In the AUI port, a collision condition is indicated by an
active SQE signal. In a TP port, a collision condition is
indicated when the port is simultaneously attempting to
transmit and receive.

Once a network port is partitioned, the eIMR device will
reconnect that port, according to the selected recon­nection algorithm, as follows:

a. Standard reconnection algorithm—A data packet

longer than 512-bit times (nominal) is transmitted or
received by the partitioned port without a collision.

Am79C984A 15

P R E L I M I N A R Y

b. Alternative reconnection algorithm—A data packet

longer than 512-bit times (nominal) is transmitted by
the partitioned port without a collision.

A partitioned port can also be reconnected by disab ling
and re-enabling the port.

All TP ports use the same reconnection algorithm; ei­ther they must all use the standard algorithm, or they
must all use the alternative reconnection algorithm.
Howev er, the reconnection algorithm for the A UI port is
programmed independently from that of the TP ports.

Detailed Functions

Reset

The eIMR device enters the reset state when the reset
(RST) pin is driven LOW. After the initial application of
power, the RST pin must be held LOW for a minimum

power is maintained to the eIMR device, a reset dura­tion of only 4 µs is required. This allows the eIMR de­vice to reset its internal logic. During reset, the eIMR
registers are set to their default values. Also during re­set, the eIMR device sets the output signals to their in­active state; that is, all analog outputs are placed in
their idle state, no bidirectional signals are driven, all
active-HIGH signals are driven LOW and all active­LOW signals are driven HIGH. In a multiple eIMR sys­tem, the reset signal must be synchronized to CLK.
See Figure 10 in the

Systems Applications

section.

The eIMR device also monitors the state of the SELI
SI, and AMODE pins on the rising (trailing) edge of
RST to configure the operating mode of the device.

Table 1 summarizes the state of the eIMR chip following
reset.

of 150 µs. If the RST pin is subsequently asserted while

Table 1. eIMR States after Reset

Function State after Reset Pull Up/Pull Down

Active-LOW Outputs HIGH No
Active-HIGH Outputs LOW No
SO Output HIGH No
DAT, JAM HIGH IMPEDANCE Either
Transmitters (TP and AUI) IDLE No
Receivers (TP and AUI) ENABLED Terminated
AUI Partitioning/Reconnection Algorithm STANDARD ALGORITHM N/A
TP Partitioning/Reconnection Algorithm STANDARD ALGORITHM N/A
Link Test Functions for TP Ports ENABLED, TP PORTS IN LINK FAIL N/A
Automatic Receiver Polarity Reversal Function DISABLED IF SI PIN IS HIGH

ENABLED IF SI PIN IS LOW

N/A

0-1

,

AUI Port

The AUI Port is fully compatible with the IEEE 802.3,
Section 7 requirement for an A UI port. It has the signals
associated with an AUI port: DO, DI, and CI.

The AUI port has two modes of operation: normal and
reverse. When configured for normal operation, the
functionality is that of an AUI port on a MAC (CI is an
input). When configured f or rev erse operation, the func­tionality is that of an AUI on a MAU (CI is an output).
The mode of the AUI port is set during the trailing (ris­ing) edge of the reset pulse, by the state of the AMODE
pin. A LO W sets the AUI port to its normal mode (CI In­put) and a HIGH sets the AUI port to its reversed (CI
Output) mode.

The eIMR device can be connected directly to a MAC
through the AUI port. This requires that the AUI port be
configured for reverse operation. Refer to the

Applications

section for more details.

Systems

TP Port Interface

Twisted Pair Transmitters

TXD is a differential twisted-pair driver. When properly
terminated, TXD will meet the electrical requirements
for 10BASE-T transmitters as specified in IEEE 802.3,
Section 14.3.1.2.

The TXD signal is filtered on the chip to reduce har­monic content per IEEE 802.3, Section 14.3.2.1
(10BASE-T). Since filtering is perf ormed in silicon, TXD
can connect directly to a standard transformer, thereb y,
eliminating the need for external filtering modules.
Proper termination is shown in the

tions

Twisted Pair Receivers

RXD is a differential twisted-pair receiver. When prop­erly terminated, RXD will meet the electrical require­ments for 10BASE-T receivers as specified in IEEE

802.3, Section 14.3.1.3. The receivers do not require

16 Am79C984A

Systems Applica-

section.

P R E L I M I N A R Y

external filter modules. Proper termination is shown in
the

Systems Applications

section.

The receiver’ s threshold voltage can be programmed to
an extended-distance mode. In this mode, the diff eren­tial receiver’s threshold is reduced to allow a longer
cable than the 100 meters specified in the IEEE 802.3
standard. For programming details, refer to the

Commands

section.

Control

Link Test

The integrated TP ports implement the Link Test func­tion, as specified in the IEEE 802.3 10BASE-T stan­dard. The eIMR device will transmit Link Test pulses to
any TP port after that port’s transmitter has been inac­tive for more than 8 ms to 17 ms. Conversely, if a TP
port does not receive any data packets or Link Test
pulses for more than 65 ms to 132 ms and the Link Test
function is enabled for that port, then that port will enter
the link-fail state. The eIMR device will disable a port in
link-fail state (i.e., disable repeater tr ansmit and receive
functions) until it receives either four consecutive Link
Test pulses or a data packet.

The Link Test function can be disabled via the eIMR
control port on a por t-by-port basis, to allow the eIMR
device to operate with pre-10BASE-T networks that do
not implement the Link Test function. When the Link
Test function is disabled, the eIMR device will not allow
the TP port to enter link-fail state, even if no Link Test
pulses or data packets are being received. Note, how­ever , that the eIMR de vice will always tr ansmit Link Test
pulses to all TP ports, regardless of whether or not the
port is enabled, partitioned, in link-fail state, or has its
Link Test function disabled. Separate control com­mands exist for enab ling and disabling the transmission
of Link Test pulses on a port-by-port basis.

Polarity Reversal

The TP ports can be programmed to receive data if a
wiring error results in a data packet being received at a
TP port with reversed polarity. This function will be en­abled upon reception of a negative End Transmit Delim­iter (ETD) or negative pulses and allows subsequent
packets to be received with the correct polarity. The po­larity-reversal function is executed once following reset
or link-fail and can be programmed via the control port
to be enabled or disabled on a port-by-port basis. The
function may be enabled or disabled, following a reset,
depending on the level of the SI signal on the rising
edge of the RST

pulse.

Visual Status Monitoring (LED) Support

The eIMR status port can be connected to LEDs to fa­cilitate the visual monitoring of repeater port status.
The status port has twelve output signals, LDA
LDB

, LDGA, and LDGB. LDA

0-4

and LDB

0-4

0-4

0-4

, and

repre­sent the four TP ports and AUI port. LDGA and LDGB
are global indicators. Attributes that may be monitored
are Carrier Sense (CRS), Collision (COL), Partition
(PAR), Link Status (LINK), Loopback (LB), Port Dis­abled (DIS), and Jabber (JAB). Three control bits,

, select the particular attributes to be displayed

LDC

0-2

on the LEDs. Table 2 shows how the programming
combinations for LDC

control the attributes that will

0-2

be monitored.
Each LED drive pin (LDGA, LDGB, LDA

, and LDB

0-4

0-4

has two states: Off and LOW. When none of the se­lected attributes are true, the driver is off and the diode
is unlit. When an attribute is true, the driver is LO W , and
the corresponding LEDs in Bank A or Bank B will be lit.

Some of the settings (LDC2 = 1) include a blink func­tion. This allows tw o attributes to be selected for a giv en
state on the pin. As an example when LDC

= 110,

0-2

the LDA outputs relating to TP ports will be solidly lit
when there is a link established at that port. However,
whenever there is activity on a port, the corresponding
LDA pin will switch on (LOW) and off at a period of 130
ms. Note that a partition on that port will also cause the
pin to go LOW.

On LDC settings that have two attributes for a state on
a pin (blink or solid-on), the attribute causing the output
to blink has priority. (Those attributes are shown in
Table 2 with a blink period specified next to it.) If an at­tribute has no blink period specified, the LED indicates
the attribute by being solidly lit.

The LEDs can also be controlled via the control port.
The Enable Software Override commands turn the
LEDs on regardless of the attributes selected for dis­play through the LDC setting. Enable Software Over­ride of Bank A LEDs causes the LDA

and LDGA pins

0-4

to be driven LOW, and Enable Software Override of
Bank B LEDs causes the LDB

and LDGB pins to be

0-4

driven LOW. The blink r ate is set b y the Softw are Ov er­ride LED Blink Rate command. The periods are off,
512 ms, 1560 ms, or solid on.

)

Am79C984A 17

P R E L I M I N A R Y

Table 2. LED Attribute-Monitoring Program Options

LED Control Global LEDs TP LEDs AUI LEDs

LDC2LDC1LDC

0 0 0 CRS COL LINK (Note 2) PAR LB PAR
0 0 1 CRS COL LINK CRS LB CRS
0 1 0 Reserved (Note 5)
0 1 1 Reserved (Note 5)
1 0 0

1 0 1 COL JAB LINK (Note 3)

1 1 0 CRS COL LINK

1 1 1 CRS COL LINK (Note 4)

0

Notes:

1. CRS = Carrier Sense, COL = Collision, JAB = Jabber, LINK = Link, LB = Loop Back, PAR = Partition, DIS = Port Disabled,
blk = Blink (Number = period of Blink).

2. For the LDC

setting of 000: If the port is partitioned, the LINK LED is off.

0-2

3. All LEDs blink 16 times at 260 ms per blink after reset.

4. All LEDs are on for approximately 4 seconds after reset.

5. LDC

= ‘010’ and ‘011’ are undefined.

0-2

LDGA LDGB LDA

CRS 260-ms blk COL 260-ms blk

1-4

LINK

CRS 260-ms blk

CRS 512-ms blk

CRS 130-ms blk

PAR 1.56-s blk

LDB

1-4

PAR

COL 260-ms blk CRS 260-ms blk

PAR (Note 3) (Note 3)

PAR or DIS

COL (Note 4) (Note 4)

LDA

0

CRS 512-ms blk

CRS 130-ms blk

PAR 1.56-s blk

LDB

0

PAR

COL 260-ms blk

PAR (Note 3)

PAR or DIS

PAR (Note 4)

LED software override is executed in two stages, by
first issuing the blink rate (Software Override of LED
Blink Rate) and then issuing the command to enable
the particular por t LEDs (Enable Software Override of
Bank A/B LEDs). All port combinations selected for
software override control will reference the blink rate
last issued by the Software Override of the LED Blink
Rate command.

LDA

0-4

, LDB

, LDGA, and LDGB are open drain out-

0-4

put drivers that sink 12 mA of current to turn on the
LEDs. In a multiple eIMR configuration, the outputs
from the global LED drivers (LDGA and LDGB) of each
chip can be tied together to drive a single pair of global
status LEDs.

CRS and COL are extended to make it easier f or visual
recognition; that is, they will remain active for some
time even if the corresponding condition has expired.
Once carrier sense is active, CRS will remain active f or
a minimum of 4 ms. Once a collision is detected, COL
is active for at least 4 ms. The exception to this rule is
for selection LDC

= 111. For this selection, COL is

0-2

stretched to 100 µs.
When LDC

= 000 or LDC

0-2

= 001, the loopback at-

0-2

tribute (LB) for the A UI port is display ed on LDA0. LB is
true when DO on the MAU is successfully looped back
to DI on the AUI port. LB is f alse (off) if a loopbac k error
is detected, or if the AUI port is disabled or in the re­verse mode. Transmit carrier sense is sampled at the
end of packet to determine the state of LB. The state of
LB remains latched until carrier sense is sampled again
for the next pac ket. The default/power-up state f or LB is
false (off).

Figure 1 shows the recommended connection of LEDs.
When LDA

0-4

, LDB

, LDGA, or LDGB are LOW, the

0-4

LED lights.

V

DD

eIMR
LED
Interface

R

LDA[4:0]
LDB[4:0]

LDGA
LDGB

Typical

20650B-6

20650A-6

Figure 1. Visual Monitoring Application—Direct

LED Drive

Network Activity Display

The eIMR status port can drive up to eight LEDs to in­dicate the network-utilization level as a percentage of
bandwidth. The status por t uses eight dedicated out­puts (ACT

) to drive a series of LEDs. The number of

0-7

LEDs in the series that will be lit increases as the
amount of network activity increases. ACT0 represents
the lowest level of activity; ACT7 represents the high­est. ACT

are open-drain outputs that typically sink

0-7

12 mA of current to turn on the LEDs. See Figure 2.

18 Am79C984A

eIMR
LED
Interface

ACT[0]
ACT[1]
ACT[2]
ACT[3]
ACT[4]
ACT[5]
ACT[6]
ACT[7]

P R E L I M I N A R Y

Figure 2. Network Activity Display

V

DD

20650A-7

Table 3 shows ACT

as a function of the percentage

0-7

of network utilization. The table uses a scale that is
more sensitive at low utilization levels. 100% utilization
represents the maximum number of events that could
occur in a given window of time.

The update rate and corresponding internal sampling
window for ACT[7:0] is 250 ms. During this sampling
window , a counter is used to count the number of times
repeater transmit activity is TRUE. The counter uses a
free-running clock which has the granularity to detect
the minimum packet size of 96 bit times.

Figure 3 shows the timing relationship between the
sampling window, counting clock, and transmit activity.

counter is active

Sampling

Window

Counting

Clock

Xmit

Activity

Number of LEDs

Lit by ACT

latch data;
update display;
clear counter

next counting cycle

Table 3. Network Utilization

Percentage Utilization

7-0

8 >80%
7 >64%
6 >32%
5 >16%
4 >8%
3 >4%
2 >2%
1 >1%

20650B-8

Figure 3. Activity Sampling

Am79C984A 19

P R E L I M I N A R Y

Expansion Bus Interface

The eIMR device expansion bus allows multiple eIMR
devices to be interconnected.

The expansion bus supports two modes of operation:
internal arbitration mode and IMR+ mode. The internal
arbitration mode uses a modified daisy-chain scheme
to eliminate the need for any external arbitration cir­cuitry. The IMR+ mode maintains the full functionality of
the IMR+ (Am79C981) expansion bus and benefits
from minimum delays. In this mode, the eIMR device
requires external circuitry to handle arbitration for con­trol of the bus.

The eIMR arbitration mode is determined at reset. This
occurs on the trailing edge of RST
state of SELI

, as illustrated in Figure 4.

0-1

Internal Arbitration Mode

The internal arbitration mode uses a daisy-chain (cas­cade) configuration. SELI

are arbitration inputs and

0-1

SELO is the arbitration output. SELO goes LOW when
there is activity on one or more of the eIMR ports, or a
SELI input is LOW. The SEL lines are connected as
shown in Figure 5. This technique allo ws activity indica­tion to propagate down the chain to the end device. All
unused SELI inputs must be tied to VDD.

ACK and COL are global activity I/O pins. When the
eIMR device senses activity, it drives ACK LOW.

.

RST

SELI_0

SELI_1 SELI_0

X 1 Internal
X 0 IMR+

Mode Selection

Figure 4. Expansion Bus Mode Selection

An eIMR device drives COL LO W when it senses more
than one device is active; that is, if the device has an
active port AND a SELI input is LOW , OR both SELI in­puts are LOW . In Boolean notation, the f ormula for COL
is:

COL = (Active port & (SELI1 + SELI0))+

(SELI1 & SELI0)

where

& represents the Boolean AND operation
+ represents the Boolean OR operation

according to the

Arbitration

Mode

20650B-9

A

CK and COL are mutually exclusive. If an eIMR driv­ing ACK senses COL LOW, the device will deassert
ACK.

DAT and JAM are synchronized to CLK. D AT is the rep­etition of data from any connected port (either TP or
AUI port) encoded in NRZ format. JAM is an internal
collision indicator. If JAM is HIGH, the active eIMR de­vice has detected an internal collision across one or
more of its ports. When this occurs , the DAT signal dis­tinguishes between single-port collisions and multiport
collisions. DAT = 1 indicates a single port collision;
DAT = 0 indicates a multiport collision.

The drive capabilities of the I/O signals on the expan­sion bus (DAT, JAM, A

CK, and COL) are sufficient to
allow seven eIMR devices to be connected together
without the use of external transceivers or buffers.

The maximum number of eIMR devices that can be
daisy chained is limited by the propagation delay of the
eIMR devices. In practice, the depth of the cascade is
limited to three eIMR devices, thus allowing a maxi­mum of seven eIMR devices connected together via
this expansion bus as shown in Figure 5.

The active device will not drive the data line, DAT,
until one bit time (100 ns) after SELO goes LOW. This
is to avoid a situation where two devices drive DAT
simultaneously.

IMR+ Mode

In IMR+ mode, the expansion bus requires an external
arbiter. The arbiter allows only one eIMR device to con­trol the expansion bus. If more than one device at­tempts to take control, the arbiter terminates all access
and signals a collision condition.

In IMR+ mode, DAT and JAM retain the same function­ality as in internal arbitration mode, but ACK and COL
are inputs to the eIMR device, driven b y the external ar­biter. The arbiter should drive ACK LOW when exactly
one eIMR device is active. It should drive COL when
more than one eIMR device is active. SELO is an out­put from the eIMR device. It indicates that the eIMR de­vice has an active port and is requesting access to the
bus.

When ACK is HIGH, DAT and JAM are in the high­impedance state. DAT and JAM go active when ACK
goes LOW. Refer to the

Systems Applications

section
(Figure 13) for the configuration of IMR+ mode of
operation.

Note: The IMR+ mode is recommended when arbitrating
between multiple boards.

.

20 Am79C984A

P R E L I M I N A R Y

V

DD

1kΩ

SELI_0
SELI_1

DAT

SELI_0
SELI_1

DAT

SELI_0
SELI_1

DAT

JAM

JAM

JAM

ACK

ACK

ACK

SELO

COL

SELO

COL

SELO

COL

SELI_0
SELI_1

DAT

SELI_0
SELI_1

DAT

JAM

JAM

ACK

ACK

SELO

COL

SELO

COL

SELI_0
SELI_1

DAT

JAM

ACK

SELO

COL

SELI_0
SELI_1

DAT

JAM

ACK

SELO

COL

Figure 5. Internal Arbitration—eIMR Devices in Cascade

Control Functions

The eIMR device receives control commands in the
form of byte-length data on the serial input pin, SI. If the
eIMR device is expected to pro vide data in response to
the command, it will send byte-length data to the serial­output pin, SO. Both the input and output data streams
are clocked with the rising edge of the SCLK signal.
The byte-length data is in RS232 serial-data format;
that is, one start bit followed by eight data bits. The ex­ternally generated clock at the SCLK pin may be either

Am79C984A 21

20650A-10

20650B-10

a free-running clock synchronized to the input bit pat­terns, or a series of individual transitions meeting the
setup-and-hold times with respect to the input bit pat­tern. If the latter method is used, 20 SCLK clock transi­tions are required for control commands that produce
SO data, and 14 SCLK clock transitions are required
for control commands that do not produce SO data.

P R E L I M I N A R Y

Command/Response Timing

Figure 6 shows the command/response timing. At the

.

SCLK

SI

SO

ST D0 D1 D2 D3 D4 D5 D6 D7

ST D0 D1 D2 D3 D4 D5 D6 D7

Figure 6. Control Get Command/Response

Control Commands

The following section details the operation of each con­trol commands available in the eIMR device. In all
cases, the individual bits in each command are shown
with the most-significant bit (bit 7) on the left and the
least-significant bit (bit 0) on the right. Table 4 and Table
5 show a summary of default states and a summary of
control commands, respectively.

Note: Data is transmitted and received on the serial
data lines least-significant bit first and most-significant
bit last.

end of a GET command, the eIMR device waits two
SCLK cycles and then transmits the response on SO.

20650A-11

20650B-11

Table 4. Summary of Default States after Reset

eIMR Programmable Option—S Off
AUI Partitioning Algorithm Normal
TP Partitioning Algorithm Normal
AUI/TP Port Enabled
Link Test Enabled
Link Pulse Enabled
Automatic Receiver Polarity

Reversal

State of SI at reset

Extended Distance Mode Disabled
Blink Rate Off
Software Override of LEDs Disabled

22 Am79C984A

P R E L I M I N A R Y

Table 5. Control Port Command Summary

Commands

SI Data SO Data

Set (Write Commands)

eIMR Chip Programmable Options

0000 10S0
Alternate AUI Partitioning Algorithm 0001 1111
Alternate TP Partitioning Algorithm 0001 0000
AUI Port Disable 0010 1111
AUI Port Enable 0011 1111
TP Port Disable 0010 00##
TP Port Enable 0011 00##
Disable Link Test Function (per TP port) 0100 00##
Enable Link Test Function (per TP port) 0101 00##
Disable Link Pulse (per TP port) 0100 10##
Enable Link Pulse (per TP port) 0101 10##
Disable Automatic Receiver Polarity Reversal

0110 00##
(per TP port)

Enable Automatic Receiver Polarity Reversal

0111 00##
(per TP port)

Disable Receiver Extended Distance Mode

0110 10##
(per TP port)

Enable Receiver Extended Distance Mode

0111 10##
(per TP port)

Disable Software Override of LEDs

1001 ####
(per Port - AUI & TP)

Enable Software Override of Bank A LEDs

1011 ####
(per Port - AUI & TP, Global)

Enable Software Override of Bank B LEDs

1100 ####
(per Port - AUI & TP, Global)

Software Override LED Blink Rate 1110 1###

Get (Read Commands)

AUI Port Status (B, S, and L Cleared)

1000 1111 PBSL 0000
AUI Port Status (B Cleared) 1000 1101 PBSL 0000
AUI Port Status (S, L, Cleared) 1000 1011 PBSL 0000
AUI Port status (None Cleared) 1000 1001 PBSL 0000
TP Port Partitioning Status 1000 0000 0000 C3..C0
Bit Rate Error Status of TP Ports 1010 0000 0000 E3..E0
Link Test Status of TP Ports 1101 0000 0000 L3..L0
Receive Polarity Status of TP Ports 1110 0000 0000 P3..P0
MJLP Status 1111 0000 M000 0000
Version 1111 1111 0000 0011

Am79C984A 23

P R E L I M I N A R Y

SET (Write Commands)

Chip Prog

SI Data 0000 10S0
SO Data None

The eIMR chip programmable option can be enabled
(or disabled) by setting (or resetting) the S bit in the
command string.

rammable Option

S AUI SQE Test Mask

Setting this bit allows the eIMR chip to ignore activity on
the CI signal pair, during the SQE test window , follo wing
a transmission on the AUI port. Enabling this function
does not prevent the reporting of this condition by the
eIMR device. The two functions oper ate independently.

The SQE Test Window, as defined in IEEE 802.3 (Sec­tion 7.2.2.2.4) is from 6 bit times to 34 bit times (0.6 µ s
to 3.4 µ s). This includes the delay introduced by a 50­meter AUI. CI activity that occurs outside this windo w is
not ignored and is treated as a true collision.

nate AUI Partitioning Algorithm

Alter

SI Data 0001 1111
SO Data None

Invoking this command sets the partition/reconnection
scheme for the A UI port to the alternate (transmit-only)
reconnection algorithm. To return the AUI port to the
standard (transmit or receive) reconnection algorithm,
it is necessary to reset the eIMR device. The standard
partitioning algorithm is selected on reset.

nate TP Partitioning Algorithm

Alter

SI Data 0001 0000
SO Data None

Invoking this command sets the partition/reconnection
scheme for the TP ports to the alternate (transmit-only)
reconnection algorithm. To return the TP ports to the
standard (transmit or receive) reconnection algorithm,
it is necessary to reset the eIMR device. The standard
partitioning algorithm is selected on reset.

UI Port Disable

A

SI 0010 1111
SO Data None

This command disables the AUI port. Subsequently , the
eIMR chip will ignore all inputs to this port and will not
transmit a DAT or JAM pattern on the AUI port. Disab ling
the AUI port also sets the partitioning state machine of
the AUI port to the idle state. Therefore, a partitioned
port can be reconnected by first disabling the AUI port
and then enabling the AUI port.

UI Port Enable

A

SI 0011 1111
SO Data None

This command enables the AUI port.

ort Disable

TP P

SI Data 0010 00##
SO Data None

This command disables the TP port designated by the
two least-significant bits of the command byte. Subse­quently, the eIMR chip will ignore all inputs to the des­ignated port and will not transmit a DAT or JAM pattern
on that port. Disabling the TP port also sets the parti­tioning state machine of that port to the idle state. There­fore, a partitioned port can be reconnected by first
disabling the port and then enabling it.

ort Enable

TP P

SI Data 0011 00##
SO Data None

This command enables the TP port designated by the
two least-significant bits of the command byte.

le Link Test Function (Per TP port)

Disab

SI Data 0100 00##
SO Data None

This command disables the Link Test function of the TP
port designated by the two least-significant bits of the
command data. As a consequence of this, the port will
no longer be disconnected if it fails the Link Test. If a
port has the Link Test disabled, reading the Link Test
Status indicates a ‘Link Pass’.

le Link Test Function (Per TP port)

Enab

SI Data 0101 00##
SO Data None

This command enables the Link Test function of the TP
port designated by the two least-significant bits of the
command data. As a consequence of this, the port is
disconnected if it fails the Link Test.

le Link Pulse (Per TP Port)

Disab

SI Data 0100 10##
SO Data None

This command disables the transmission of the Link
pulse on the TP port designated by the two least­significant bits of the command byte.

le Link Pulse (Per TP Port)

Enab

SI Data 0101 10##
SO Data None

This command enables the transmission of the Link
pulse on the TP port designated by the two least­significant bits of the command byte.

24 Am79C984A

P R E L I M I N A R Y

le Automatic Receiver Polarity Reversal (Per TP

Disab
Port)

SI Data 0110 00##
SO Data None

This command disables the Automatic Receiv er Polarity
Reversal function f or the TP port designated by the two
least-significant bits in the command byte. If this func­tion is disabled on a TP port receiving with reversed
polarity (due to a wiring error), the TP port will fail the
Link Test due to the incorrect polarity of the received
Link pulses.

The state of Automatic P olarity Re versal function is set
by SI on reset. If SI is HIGH at the rising edge of RST
the eIMR device disables Automatic Polarity Reversal.
If SI is LOW at the rising edge of RST, the eIMR device
enables Automatic Polarity Reversal.

le Automatic Receiver Polarity Reversal (Per TP

Enab
Port)

SI Data 0111 00##
SO Data None

This command enables the Automatic Receiv er Polarity
Reversal function f or the TP port designated by the two
least-significant bits in the command byte. If enabled in
a TP port, the eIMR chip will automatically invert the
polarity of that port’s receiver circuitry if the TP port is
detected as having reversed polarity (due to wiring er­ror). After reversing the receiver polarity, the TP port
could then receive subsequent (reverse polarity)
packets correctly.

le Receiver Extended Distance Mode (Per TP

Disab
Port)

SI Data 0110 10##
SO Data None

This command disables the Receiver Extended
Distance Mode and restores the RXD circuit of the trans­ceiver to normal squelch levels for the TP port driver
designated by the two least-significant bits of the com­mand data.

le Receiver Extended Distance Mode (P er TP Port)

Enab

SI Data 0111 10##
SO Data None

This command modifies the RXD circuit of the trans­ceiver for the TP port driver designated by the two least­significant bits of the command data. The RXD squelch­threshold value is lowered to accommodate signal at­tenuation associated with lines longer than 100 meters.
At reset, Receiver Extended Distance Mode is disabled
and the RXD circuit defaults to normal squelch-thresh­old values.

le Software Override of LEDs

Disab
(Per Port - AUI and TP, Global)

SI Data 1001 ####
SO Data None

This command disables Software Override of the Port
LEDs.

Individual LEDs and combinations of LEDs can be
selected via the lower four bits of the command b yte as
follows:

####

Port(s) affected

0000-0011 TP0 - TP3

,

0100-0111 Reserved
1000 AUI port
1001 Reserved
1010 Reserved
1011 All TP ports
1100 All ports
1101 Global
1110 Reserved
1111 Reserved

Following command e x ecution, the attributes displa y ed
on the LEDs will be determined by LDC
Override of LEDs is disabled after reset.

le Software Override of Bank A LEDs (Per Port -

Enab
AUI and TP, Global)

SI Data 1011 ####
SO Data None

This command forces the LEDs in Bank A to blink. In­dividual LEDs and combinations of LEDs can be select­ed via the lower four bits of the command b yte as follows:

####

Port(s) affected

0000-0011 TP0 - TP3
0100-0111 Reserved
1000 AUI port
1001 Reserved
1010 Reserved
1011 All TP ports
1100 All ports
1101 Global
1110 Reserved
1111 Reserved

The designated LED driver(s) will switch between LO W
and ‘off’ at the rate set by the Software Override Blink
Rate command. Enable Software Override of Bank A
LEDs references the blink rate last issued and o verrides
any other attribute specified by LDC

. Softw are Over-

0-2

ride of LEDs is disabled after reset.

. Software

0-2

Am79C984A 25

P R E L I M I N A R Y

le Software Override of Bank B LEDs (Per Port -

Enab
AUI and TP, Global)

SI Data 1100 ####
SO Data None

This command forces the LEDs in Bank B to blink. In­dividual LEDs and combinations of LEDs can be select­ed via the lower four bits of the command b yte as follows:

####

0000-0011 TP0 - TP3
0100-0111 Reserved
1000 AUI port
1001 Reserved
1010 Reserved
1011 All TP ports
1100 All ports
1101 Global
1110 Reserved
1111 Reserved

The designated LED driver(s) will switch between LO W
and ‘off’ at the rate set by the Softw are Override of LED
Blink Rate command. Enable Software Override of
Bank B LEDs references the blink rate last issued and
overrides any other attribute specified by LDC
ware Override of LEDs is disabled after reset.

are Override of LED Blink Rate

Softw

SI Data 1110 1###
SO Data None

This command sets the blink period of the LEDs with
Software Override enabled. The duty cycle is 50%. This
command defaults to ‘off’ at reset.

Setting

1110 1000 Off
1110 1001 512 ms
1110 1010 1560 ms
1110 1011 Solid On

These settings apply to the blink rate for both Bank A
and Bank B. This command must precede the Enable
Software Override of Bank A/B LEDs command. All LED
combinations selected for Software Override will refer­ence the blink rate last issued.

Port(s) affected

Blink Period

0-2

. Soft-

GET (Read Commands)

UI Port(s) Status

A

SI Data 1000 1111
SO Data PBSL 0000

The combined AUI status of the eIMR device allows a
single instruction to be used to monitor the AUI port.
The four local status bits are:

P Partitioning Status

This bit is ‘0’ if the AUI port is par titioned and ‘1’ if the
AUI port is connected.

B Bit Rate Error

This bit is set to ‘1’ if there is an instance of FIFO overflo w
or underflow. The bit is cleared when the eIMR device
is read.

S SQE Test Status

This bit is set to ‘1’ if the SQE test error is detected by
the eIMR chip. The bit is cleared when the status is read.

L Loopback Error

The MAU attached to the AUI port is required to loop­back data transmitted to DO onto the DI circuit. If the
loopback carrier is not detected by the eIMR device, this
bit is set to ‘1’. This bit is cleared when the status is read.

nate AUI Port(s) Status

Alter

There are three further variations of the AUI Port Status
Command allowing selective clearing of a combination
of B,S, and L bits. These are the following:

Alternate 1: B is not cleared, S and L are Cleared

SI Data 1000 1011
SO Data PBSL 0000

Alternate 2: S and L are not cleared, B is Cleared

SI Data 1000 1101
SO Data PBSL 0000

Alternate 3: None of S, B, and L are Cleared

SI Data 1000 1001
SO Data PBSL 0000

ort Partitioning Status

TP P

SI Data 1000 0000
SO Data 0000 P3..P0

P

n

= 0 TP Port Partitioned

P

n

= 1 TP port Connected

where

n

is a port number in the range 0–3.

The response to this command gives the partitioning
status of all four TP ports. If a port is disabled, reading
its partitioning status will indicate that it is connected.

Bit Rate Error Status of

SI Data 1010 0000
SO Data 0000 E3..E0

E

n

= 0 No Error

E

n

= 1 FIFO Overflow

where

n

is a port number in the range 0–3.

The response to this command gives the bit-rate-over­flow or underflow (data rate mismatch) condition of all
the TP ports. A 1 indicates that the FIFO has overflow ed
or underflowed due to the amount of data received by
the corresponding port.

TP Ports

26 Am79C984A

P R E L I M I N A R Y

Test Status of TP ports

Link

SI Data 1101 0000
SO Data 0000 L3..L0

L

n

= 0 TP Port n in Link Test Failed

L

n

= 1 TP port n in Link Test Passed

where

n

is a port number in the range 0–3.

The response to this command gives the Link Test sta­tus of all the TP ports. A disabled port continues to report
Link Test status. Re-enabling the port causes the port
to be placed in the Link Test Fail state.

e Polarity Status of TP Ports

Receiv

SI Data 1110 0000

SO Data 0000 P3......P0

P

n

= 0 TP Port n Polarity Correct

P

n

= 1 TP port n Polarity Reversed

where

n

is a port number in the range 0–3.

The response to this command gives the Received Po­larity status of all the TP ports. If the polarity is detected
as reversed f or a TP port, then the eIMR device will set
the appropriate bit in this command’s result only if the
Polarity Reversal Function is enabled for that port.

MJLP Status

SI Data 1111 0000
SO Data M000 0000

Each eIMR device contains an independent MAU Jab­ber Lock Up Protection timer. The timer is designed to
inhibit the transmit function of the eIMR device if it has
been transmitting continuously for more than 65536 bit
times. This bit remains set and is only cleared when the
MJLP status is read using this command.

ersion

V

SI Data 1111 1111
SO Data 0000 0011

The response to this command gives the version of the
eIMR device. 0011 was chosen to help distinguish the
eIMR device from the IMR (Am79C980) and the IMR+
(Am79C981) devices.

SYSTEMS APPLICATIONS
eIMR to TP Port Connection

The eIMR device provides a system solution to designing
non-managed multiport repeaters. The eIMR device con­nects directly to AC coupling modules for a 10BASE-T
hub. Figure 7 shows the simplified connection.

Twisted Pair Transmitters

TXD signals need to be properly terminated to meet the
electrical requirement for 10BASE-T transmitters. Prop­er termination is shown in Figure 8 which consists of a
110- Ω resistor and a 1:1 transformer. The load is a twisted­pair cable that meets IEEE 802.3, Section 14.4 specifi­cations. The cable is terminated at the opposite end by
100 Ω .

Twisted Pair Receivers

RXD signals need to be properly terminated to meet the
electrical requirements for 10BASE-T receivers. Proper
termination is shown in Figure 9. Note that the receiv ers
do not require external filter modules.

Am79C984A 27

P R E L I M I N A R Y

RST

CLK

eIMR

TXD0+
TXD0–

RXD0+

RXD0–

TXD1+
TXD1–

RXD1+

RXD1–

TXD2+
TXD2–

RXD2+

RXD2–

TXD3+
TXD3–

RXD3+

RXD3–

TP Connector

1:1

110 Ω

1:1

100 Ω

TP Connector

1:1

110 Ω

1:1

100 Ω

TP Connector

1:1

110 Ω

1:1

100 Ω

TP Connector

1:1

110 Ω

1:1

100 Ω

20650A-12

Figure 7. Simplified 10BASE-T Connection

TXD+

110Ω

1:1

Twisted Pair

100Ω

TXD-

20650A-13

20650B-13

Figure 8. TXD Termination

RXD+

1:1

100Ω

RXD–

Twisted Pair

100Ω

Figure 9. RXD Termination

28 Am79C984A

20650A-14

20650A-14

20650B-14

P R E L I M I N A R Y

MAC Interface

The eIMR device can be connected directly to a MAC
through the AUI port. This requires that the AUI port be
configured in the reverse mode and connected as
shown in Figure 10a. Notice that DI is connected to DO

Am79C940 eIMR Am7996 eIMR

DO+
DO–

40 Ω

DI+
DI–

40 Ω

CI+
CI–

0.1 µF 0.1 µF

40 Ω

40 Ω

40 Ω

DI+
DI–

40 Ω

DO+
DO–

CI+
CI–

of the MAC and DO is connected to DI of the MAC,
because the reverse configuration only affects CI.
Where CI is an input in the normal mode, in the reverse
mode, CI is an output. Figure 10b shows the normal AUI
configuration for reference.

DI+

DI–

DO+

DO–

40 Ω

CI+

CI–

39 – 150 Ω

1:1

40 Ω

1:1

40 Ω

1:1

40 Ω

0.1 µF

DI+
DI–

40 Ω

DO+
DO–

0.1 µF

CI+
CI–

40 Ω

0.1 µF

a) Reverse Mode (with MAC) b) Normal Mode (with MAU)

Figure 10. AUI Port Interconnections

Internal Arbitration Mode Connection

The internal arbitration mode uses a modified daisy­chain scheme to eliminate the need for any external
arbiter. In this mode, A
up through a minimum resistance of 1 k Ω. The DAT and
JAM pins also need to be pulled down via a high value
resistor. Refer to Figure 11.

CK and COL need to be pulled

–9 V

20650B-15

20650A-16

IMR+ Mode External Arbitration

The IMR+ mode maintains the full functionality of AMD’s
IMR+ (Am79C981) device’s expansion bus. In this
mode, the eIMR device requires external circuitry to
handle arbitration for control of the bus . Figure 12 shows
the configuration for the IMR+ mode of operation.

Am79C984A 29

P R E L I M I N A R Y

V

DD

(Note: In a multiple eIMR system, the reset
signal must be synchronized to CLK.)

RST

20 MHz

OSC

74LS74

D

Q

D

Q

P C

Q

P C

Q

Figure 11. eIMR Internal Arbitration Mode Connection

eIMR eIMR

SELI_0

SELO

SELI_1

DAT JAM ACK COL

SELI_0
SELI_1

RST
CLK

DAT

JAM

ACK

SELI_0
SELI_1

RST

CLK

DAT

JAM

SELI_0

SELI_1

DAT JAM ACK COL

eIMR

SELO

COL

eIMR

SELO

ACK

COL

SELO

1 kΩ

SELI_0
SELI_1

RST

CLK

DAT

JAM

SELI_0

SELI_1

DAT JAM ACK COL

eIMR

SELO

ACK

eIMR

COL

~1 kΩ

SELO

~1 kΩ

20650B-16

V

DD

V

DD

1 kΩ

COL ACK SEL1 SEL2 SEL3

Figure 12. IMR+ Mode External Arbitration

30 Am79C984A

Arbiter

GCOL

20650B-17

P R E L I M I N A R Y

Visual Status Display

LDA/B[4:0] and LDGA/B provide visual status indicators
for the eIMR. LDA/B[4:0] displays Link, Carrier Sense,
Collision, and Partition information for the TP and AUI
ports. LDGA/B display global Carrier Sense, Collision,
and Jabber information.

In a multiple eIMR configuration, the global LED drivers
(LDGA/B) from each chip can be tied together to drive
a single pair of global status LEDs. The open dr ain out­put of these drivers facilitate this configuration. Refer to
Figure 13.

LDA[4:0]
LDB[4:0]

LDGA
LDGB

LDA[4:0]
LDB[4:0]

LDGA
LDGB

VDD

20650B-18

20650A-19

Figure 13. Visual Status Display Connection

Am79C984A 31

µ

µ

µ

DI ±

V

µ

P R E L I M I N A R Y

ABSOLUTE MAXIMUM RATINGS

Storage Temperature . . . . . . . . . .–65 ° C to +150 ° C

Ambient Temperature Under Bias . . . . 0 ° C to +70 ° C

Supply Voltage referenced to
AV

or DV

SS

Stresses above those listed under ABSOLUTE MAXI-

SS

(AV

DD

, DV

). . . . . . . –0.3 V to +6.0 V

DD

OPERATING RANGES

Commercial (C) Devices

Temperature (T
Supply Voltages (V

Operating ranges define those limits between which the
functionality of the device is guaranteed.

). . . . . . . . . . . . . . . . . 0 ° C to +70 ° C

A

) . . . . . . . . . . . . . . . . . +5 V ± 5%

DD

MUM RATINGS may cause permanent device failure.
Functionality at or above these limits is not implied. Ex­posure to Absolute Maximum Ratings for e xtended pe­riods may affect reliability . Programming conditions ma y
differ .

DC CHARACTERISTICS over operating ranges unless otherwise specified

Parameter

Symbol

Digital I/O

V
V
V

V

I

ILSTR

V

OLOD

Input LOW Voltage

IL

Input HIGH Voltage

IH

Output LOW Voltage

OL

Output HIGH Voltage

OH

I

Input Leakage Current

IL

Input Leakage Current for STR pin
Open Drain Output LOW Voltage (LED pins)

AUI Ports

I

IAXD

V
V

AICM
AIDV

Input Current at DI ±

, CI ± Open Circuit Input Voltage Range

Differential Mode Input Voltage Range
(DI, CI)

V

V
V

V

ASQ
ATH
AOD
AOC

DI, CI Squelch Threshold
DI Switching Threshold
Differential Output Voltage  (DO+) – (DO) 
Differential Output Voltage  (CI+) – (CI–) 

(Reverse Mode)
DO Differential Output Voltage Imbalance

DO Differential Idle Output Voltage R

OFF

DO Differential Idle Output Current R

OFF

DO+, DO- Common Mode Output Voltage

V

I

AOD

V

AOD

V

AOCM

AODI

Twisted Pair Ports

I

IRXD

Input Current at RXD ±

and CI ± Pairs
R
V

RXD

TIVB

RXD Differential Input

RXD+, RXD– Open Circuit

Input V oltage (bias)

V

TID

Differential Mode Input

Range (RXD)

Parameter Description

and CI ± Pairs

Test Conditions

Min

V

SS

V

SS

I

= 4.0 mA

OL

= –0.4 mA

I

OH

V

<V

SS

<V

V

SS

I

OLOD

<V

V

SS

I

IN

V

DD

= 0.0 V
= 0.0 V

<V

IN

<V

IN

= 12 mA

<V

IN

DD

= 0

= 5.0 V

DD
DD

–0.5 0.8 V

2.0 0.5 + V
– 0.4 V

2.4 – V
–
–
– 0.4 V

–500

V

DD

– 3.0

V

DD

–2.5 +2.5 V

– –275 –160 mV

(Note 1) -35 +35 mV

R

= 78 Ω

L

= 78 Ω

R

L

= 78 Ω

R

L

= 78 Ω

L

= 78 Ω (Note 1)

L

R

= 78 Ω

L

<V

SS

<V

IN

AV

DD

620
620

–25
–40

–1.0 +1.0 mA

2.5

–500

(Note 1) 10 – k Ω

V

DD

= 5.0 V

V

– 3.0

DD

–3.1 +3.1 V

V

Max

DD

Unit

10
50

500

– 1.0

1100 mV
1100 mV

+25 mV
+40 mV

V

DD

500

– 1.5

DD

V

A
A

A

V

A

V

32 Am79C984A

P R E L I M I N A R Y

DC CHARACTERISTICS (continued)

Parameter

Symbol

Parameter Description

Test Conditions

Twisted Pair Ports (Continued)

V

TSQ+

V

TSQ–

V

THS+

V

THS–

V

LTSQ+

V

LTSQ–

V

LTHS+

V

LTHS–

V

RXDTH

RXD Positive Squelch Threshold
(peak)

RXD Negative Squelch Threshold
(peak)

RXD Post-Squelch Positive
Threshold (peak)

RXD Post-Squelch Negative
Threshold (peak)

RXD Positive Squelch Threshold
(peak) - Extended Distance Mode

RXD Negative Squelch Threshold
(peak) - Extended Distance Mode

RXD Post-Squelch Positive
Threshold - Extended Distance Mode

RXD Post-Squelch Negative
Threshold - Extended Distance Mode

RXD Switching Threshold

Sinusoid
5 MHz<f<10 MHz

Sinusoid
5 MHz<f<10 MHz

Sinusoid
5 MHz<f<10 MHz

Sinusoid
5 MHz<f<10 MHz

Sinusoid
5 MHz<f<10 MHz

Sinusoid
5 MHz<f<10 MHz

Sinusoid
5 MHz<f<10 MHz

Sinusoid
5 MHz<f<10 MHz

(Note 1) –60 60 mV

Power Supply Current

I

DD

Power Supply Current
(Idle) (Note 2)

Power Supply Current
(Transmitting)

CLK = 20 MHz
V

= +5.25V

DD

CLK = 20 MHz
V

= +5.25V

DD

Notes:

1. Parameter not tested.

2. LED current not included. Maximum current rating on LED drivers is 12 mA.

Min

Max

Unit

300 520 mV

–520 –300 mV

150 293 mV

–293 –150 mV

180 365 mV

–365 –180 mV

90 175 mV

–175 –90 mV

– 100 mA

– 350 mA

Am79C984A 33

SWITCHING CHARACTERISTICS

P R E L I M I N A R Y

Parameter

Symbol

Parameter Description

Clock and Reset Timing

t

CLK

t

CLKH

t

CLKL

t

CLKR

t

CLKF

t

PRST

t

RST

t

RSTSET

CLK Clock Period
CLK Clock High
CLK Clock Low
CLK Rise Time
CLK Fall Time
Reset Pulse Width after Power On 150 –
Reset Pulse Width
Reset HIGH Setup Time with respect to

CLK

t

RSTHLD

t

XRS

Reset LOW Hold Time 0 – ns
AMODE, SELI

to Rising Edge of RST

t

XRH

AMODE,SELI
from Rising Edge of RST

AUI Port Timing

t

DOTD

t

DOTR

t

DOTF

t

DORM

t

DOETD

t

PWODI

t

PWKDI

CLK Rising Edge to DO Toggle
DO+, DO– Rise Time (10% to 90%) – 7.0 ns
DO+, DO– Fall Time (90% to 10%) – 7.0 ns
DO+, DO– Rise and Fall Time Mismatch – 1.0 ns
DO± End of Transmission 275 375 ns
DI Pulse Width Accept/Reject Threshold |VIN|>|V
DI Pulse Width Not to Turn-off Internal

Carrier Sense

t

PWOCI

t

PWKCI

t

CITR

t

CITF

t

CIRM

CI Pulse Width Accept/Reject Threshold |VIN|>|V
CI Pulse Width Not to Turn-off Threshold |VIN|>|V
CI Rise Time (In Reverse Mode) – 7.0 ns
CI Fall Time (In Reverse Mode) – 7.0 ns
CI+, CI– Rise and Fall Time Mismatch

(AUI in Reverse Mode)

Expansion Bus Timing

t

CLKHRL

t

CLKHRH

t

CLKHDR

t

CLKHDZ

t

DJSET

t

DJHOLD

t

CASET

t

CAHLD

t

SCLKHLD

CLK HIGH to SELO Driven LOW CL = 50 pF 15 30 ns
CLK HIGH to SELO Driven HIGH CL = 50 pF 15 30 ns
CLK HIGH to DAT/JAM Driven CL = 100 pF 14 30 ns
CLK HIGH to DAT/JAM Not Driven CL = 100 pF 14 30 ns
DAT/JAM Setup Time to CLK 10 – ns
DAT/JAM Hold Time from CLK 9 – ns
COL/ACK Setup Time to CLK 10 – ns
COL/ACK Hold Time from CLK 9 – ns
SI, SCLK Hold Time 50 – ns

, and SI_D Setup Time

0

, and SI_D Hold Time

0

Test Conditions

ASQ

|VIN|>|V

ASQ

ASQ
ASQ

Min

Max

Unit

49.995 50.005 ns
20 30 ns
20 30 ns

– 10 ns
– 10 ns

µ

4 –

µ

15 – ns

0 – ns

400 – ns

– 30 ns

| (Note 2) 15 45 ns
| (Note 3) 136 200 ns

| (Note 4) 10 26 ns
| (Note 5) 75 160 ns

– 1.0 ns

s
s

34 Am79C984A

P R E L I M I N A R Y

SWITCHING CHARACTERISTICS (continued)

Parameter

Symbol

Parameter Description

Twisted Pair Port Timing

t

TXTD

t

TETD

t

PWKRD

CLK Rising Edge to TXD± Transition Delay – 50 ns
Transmit End of Transmission 250 375 ns
RXD Pulse Width Maintain/Turn-off

Threshold

t

PERLP

t

PWLP

Idle Signal Period 8 24 ms
Idle Link Test Pulse Width 75 120 ns

Control Port Timing

t

SCLK

t

SCLKH

t

SCLKL

t

SCLKR

t

SCLKF

t

SISET

t

SIHLD

t

SODLY

SCLK Clock Period 100 – ns
SCLK Clock HIGH 30 – ns
SCLK Clock LOW 30 – ns
SCLK Clock Rise Time – 10 ns
SCLK Clock Fall Time – 10 ns
SI Input Setup Time to SCLK Rising Edge 10 – ns
SI Input Hold Time from SCLK Rising Edge 10 – ns
SO Output Delay from SCLK Rising Edge CL = 100 pF – 40 ns

Notes:

1. Parameter not tested.

2. DI pulses narrower than t

3. DI pulses narrower than t

PWODI
PWKDI

carrier sense off.

4. CI pulses narrower than t

5. CI pulses narrower than t

PWOCI
PWKCI

carrier sense off.

6. RXD pulses narrower than t
RXD carrier sense off.

Test Conditions

|VIN|>|V

(min) will be rejected; pulses wider than t

| (Note 6) 136 200 ns

THS

(max) will turn internal DI carrier sense on.

PWODI

(min) will maintain internal DI carrier on; pulses wider than t

(min) will be rejected; pulses wider than t

(max) will turn internal CI carrier sense on.

PWOCI

(min) will maintain internal CI carrier on; pulses wider than t

(min) will maintain internal RXD carrier sense on; a pulse wider than t

PWKRD

Min

Max

(max) will turn internal DI

PWKDI

(max) will turn internal CI

PWKCI

(max) will turn

PWKRD

Unit

Am79C984A 35

KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

P R E L I M I N A R Y

SWITCHING WAVEFORMS

Must be
Steady

May
Change
from H to L

May
Change
from L to H

Don’t Care,
Any Change
Permitted

Does Not
Apply

Will be
Steady

Will be
Changing
from H to L

Will be
Changing
from L to H

Changing,
State
Unknown

Center
Line is High­Impedance
“Off” State

KS000010-PAL

CLK

t

CLKR

t

CLK

t

CLKH

t

CLKF

t

CLKL

Figure 14. Clock Timing

20650A-20

20650B-19

36 Am79C984A

P R E L I M I N A R Y

SWITCHING WAVEFORMS (continued)

t

SCLK

SCLK

t

SCLKH

SI

t

SODLY

SO

Figure 15. Control Port Timing

t

SCLKL

t

SISET

t

SCLKR

t

SIHLD

t

SCLKF

20650B-20

20650A-21

CLK

t

RSTHLD

RST

t

RST

TCLK

or t

PRST

Note: TCLK represents internal eIMR timing

Figure 16. Reset Timing

AMODE, SELI_0

RST

t

XRS

t

RSTSET

t

XRH

20650B-21

20650A-22

Figure 17. Mode Initialization

Am79C984A 37

20650B-22

P R E L I M I N A R Y

SWITCHING WAVEFORMS (continued)

CLK

TCLK

SELO

ACK

COL

DAT/JAM

Note: TCLK represents internal eIMR timing

Figure 18. Expansion Bus Input Timing

CLK

TCLK

t

CLKHRH

t

SELO

ACK

COL

t

CASET

t

CLKHDR

t

CLKHRL

t

DJSET

CAHLD

IN

t

DJHOLD

t

CLKHDZ

t

CASET

20650B-23

DAT/JAM

Note: TCLK represents internal eIMR timing

Figure 19. Expansion Bus Output Timing

38 Am79C984A

OUT

20650B-24

P R E L I M I N A R Y

SWITCHING WAVEFORMS (continued)

CLK

TCLK

SELO

t

CLKHRL

ACK

COL

t

CLKHRH

t

CASET

t

CASET

t

CAHLD

DAT/JAM

Note: TCLK represents internal eIMR timing

Figure 20. Expansion Bus Collision Timing

CLK

t

DOTD

t

DOTR

DO+

DO–

Figure 21. AUI Timing Diagram

t

PWKDI

(t

)

PWKCI

t

DOTF

t

PWKDI

(t

PWKCI

t

DOETD

)

ININ

20650B-25

20650A-26

20650B-26

DI+
(CI±)

t

PWODI

(t

PWOCI

V

ASQ

)

20650A-28

20650B-27

Figure 22. AUI Receive Diagram

Am79C984A 39

P R E L I M I N A R Y

SWITCHING WAVEFORMS (continued)

1 0 1 1 1 0 1 0 ETD

01

CLK

t

TXETD

TXD+

TXD–

Figure 23. TP Ports Output Timing Diagram

t

TXETD

20650A-29

20650B-28

RXD+/–

V

TSQ–

V

TSQ+

t

PWLP

t

PERLP

Figure 24. TP Idle Link Test Pulse

t

PWKRD

t

PWKRD

Figure 25. TP Receive Timing Diagram

t

PWKRD

V
V

THS+
THS–

40 Am79C984A

SWITCHING TEST CIRCUIT

P R E L I M I N A R Y

V

DD

Pin

Test Point

V

SS

Figure 26. Switching Test Circuit

20650A-32

20650B-31

Am79C984A 41

P R E L I M I N A R Y

PHYSICAL DIMENSIONS
PL 084
84-Pin Plastic LCC (measured in inches)

.062

1.185

1.195

1.150

1.156

.042
.056

.083

1.185

1.195

1.150

1.156

.026
.032

Pin 1 I.D.

TOP VIEW

.050 REF

.007
.013

.090
.130

.165
.180

SIDE VIEW

1.090

1.130

1.000
REF

.013
.021

SEATING PLANE

16-038-SQ
PL 084
DF79
8-1-95 ae

42 Am79C984A

P R E L I M I N A R Y

PHYSICAL DIMENSIONS
PQR100
100-Pin Plastic Quad Flat Pack

17.00

17.40

Pin 80

18.85
REF

19.90

20.10

23.00

23.40

Pin 100

12.35
REF

Pin 1 I.D.

13.90

14.10

Pin 30

0.25
MIN

2.70

2.90

0.65 BASIC

Pin 50

3.35
MAX

SEATING PLANE

16-038-PQR-2
PQR100
DA92
8-2-94 ae

Am79C984A 43

Trademarks

Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
Am186, Am386, Am486, Am29000,

PCnet-

FAST

, PCnet-

FAST

Micro Devices, Inc.
Microsoft is a registered trademark of Microsoft Corporation.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

+, PCnet-Mobile, QFEX, QFEXr, QuASI

b

IMR, eIMR, eIMR+, GigaPHY, HIMIB, ILACC, IMR, IMR+, IMR2, ISA-HUB, MACE, Magic Packet, PCnet,

,

QuEST , QuIET, T AXIchip, TPEX, and TPEX Plus are trademarks of Advanced